Philips LPC2131, LPC2132, LPC2134, LPC2136, LPC2138 User Guide

UM10120

Volume 1: LPC213x User Manual

Rev. 01 — 24 June 2005 User manual

Document information

Info Content Keywords LPC2131, LPC2132, LPC2134, LPC2136, LPC2138, LPC2000, LPC213x,

ARM, ARM7, embedded, 32-bit, microcontroller

Abstract An initial LPC213x User Manual revision

Philips Semiconductors

Volume 1 LPC2131/2/4/6/8 UM

Revision history

Rev Date Description

01 20050624 Initial version

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Contact information

For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

User manual Rev. 01 — 24 June 2005 2

1.1 Introduction

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Chapter 1: General information

Rev. 01 — 24 June 2005 User manual

The LPC2131/32/34/36/38 microcontrollers are based on a 16/32 bit ARM7TDMI-S™ CPU with real-time emulation and embedded trace support, that combines the microcontroller with 32 Flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb® Mode reduces code by more than 30 performance penalty.

Due to their tiny size and low power consumption, these microcontrollers are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. With a wide range of serial comm unications interfaces and on-chip SRAM options of 8/16/32 converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit 8

channel ADC(s), 10-bit D AC, PWM channels and 47 GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.

kB, 64 kB, 128 kB, 256 kB and 512 kB of embedded high speed

% with minimal

kB, they are very well suited for communication gateways and protocol

1.2 Features

• 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package

• 8/16/32 kB of on-chip static RAM and 32/64/128/256/512 kB of on-chip Flash program

memory. 128 bit wide interface/accelerator enables high speed 60

• In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.

Single Flash sector or full chip erase in 400

• EmbeddedICE

on-chip RealMonitor™ software and high speed tracing of instruction execution.

and Embedded Trace interfaces offer real-time debugging with the

ms and 256 bytes programming in 1 ms.

• One (LPC2131/2) or two (LPC2134/6/8) 8 channel 10-bit A/D converters provide(s) a

total of up to 16 analog inputs, with conversion times as low as 2.44

• Single 10-bit D/A converter provides variable analog output. (LPC2132/4/6/8 only).

• Two 32-bit timers/external event counters (with four capture and four compare

channels each), PWM unit (six outputs) and watchdog.

• Low power Real-time clock with independent po wer an d dedicated 32 kHz clock input.

• Multiple serial interfaces including two UARTs (16C550), two Fast I

SPI™ and SSP with buffering and variable data length capabilities.

• Vectored interrupt controller with configurable priorities and vector addresses.

MHz operation.

µs per channel.

C (400 kbit/s),

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Volume 1 Chapter 1: Introductory information

• Up to 47 of 5 V tolerant general purpose I/O pins in tiny LQFP64 package.

• Up to nine edge or level sensitive external interrupt pins available.

• 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked

Loop (PLL) with settling time of 100

• On-chip integrated oscillator operates with external crystal in range of 1 MHz to

• Power saving modes include Idle and Power-down.

• Individual enable/disable of peripheral functions as well as peripheral clock scaling

down for additional power optimization.

• Processor wake-up from Power-down mode via external interrupt or Real-time Clock.

• Single power supply chip with Power-On Reset (POR) and Brown-Out Detection

(BOD) circuits:

– CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O

1.3 Applications

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µs.

MHz or with external oscillator from 1 MHz to 50 MHz.

pads

• Industrial control

• Medical systems

• Access control

• Point-of-sale

• Communication gateway

• Embedded soft modem

• General purpose applications

1.4 Device information

Table 1: LPC2131/2132/2134/2136/2138 device information

Device Number of

LPC2131 64 8 kB 32 kB 8 - LPC2132 64 16 kB 64 kB 8 1 LPC2134 64 16 kB 128 kB 16 1 UART1 with fu ll

LPC2136 64 32 kB 256 kB 16 1 UART1 with fu ll

LPC2138 64 32 kB 512 kB 16 1 UART1 with fu ll

pins

On-chip SRAM

On-chip FLASH

Number of 10-bit ADC channels

Number of 10-bit DAC channels

Note

modem interface

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Volume 1 Chapter 1: Introductory information

1.5 Architectural overview

The LPC2131/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The LPC2131/2/4/6/8 configures the ARM7TDMI-S processor in little-endian byte order.

AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4

gigabyte ARM memory space. Each AHB peripheral is a llocated a 16 kB address space within the AHB address space. LPC2131/2/4/6/8 peripheral functions (other than the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2 addresses, beginning at the 3.5 a 16

kB address space within the VPB address space.

The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block (see chapter "Pin Connect Block" on specific application requirements for the use of peripheral functions and pins.

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megabyte range of

gigabyte address point. Each VPB peripheral is allocated

page 73). This must be configured by software to fit

1.6 ARM7TDMI-S processor

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architectu re is base d on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employ ed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM instruction set.

• A 16-bit THUMB instruction set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connecte d to a 16 -b it me m ory system.

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Volume 1 Chapter 1: Introductory information

The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website.

1.7 On-chip Flash memory system

The LPC2131/2/4/6/8 incorporates a 32, 64, 128, 256 and 512 kB Flash memory system respectively. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways: over the serial builtin JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application Programming (IAP) capabilities. The application program, using the IAP functions, may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. When the LPC2131/2/4/6/8 on-chip bootloader is used, 32/64/128/256/500 kB of Flash memory is available for user code.

The LPC2131/2/4/6/8 Flash memory provides minimum of 10,000 er ase/write cycles and 10 years of data-retention.

1.8 On-chip Static RAM (SRAM)

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On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2131/2/4/6/8 provide 8/16/32 kB of static RAM respectively.

The LPC2131/2/4/6/8 SRAM is designed to be accessed as a byte-addressed memory. Word and halfword accesses to the memory ignore the alignment of the address and access the naturally-aligned value that is addressed (so a memory access ignores address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses). Therefore valid reads and writes require data accessed as halfwords to originate from addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in hexadecimal nottaion) and data accessed as words to originate from adresses with address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal notation). This rule applies to both off and on-chip memory usage.

The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-bac k writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when sof tware does anot her write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write oper ation). An y softwar e that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset.

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Volume 1 Chapter 1: Introductory information

1.9 Block diagram

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EINT3:0

8 × CAP0

8 × MAT

AD0.7:0

AD1.7:0

AOUT

P0.31:0

P1.31:16

PWM6:1

LPC2131/2132/2134/2136/2138

ARM7 local bus

INTERNAL

SRAM

CONTROLLER

8/16/32 kB

SRAM

INTERRUPTS

TIMER 0/TIMER 1

A/D CONVERTERS

(1)

(2)

D/A CONVERTER

PURPOSE I/O

INTERNAL

CONTROLLER

32/64/128/

256/512 kB

EXTERNAL

CAPTURE/ COMPARE

(1)

0 AND 1

GENERAL

PWM0

FLASH

(2)

TMS

(3)

TRST

ARM7TDMI-S

(3)

TDI

(3)

TCK

TEST/DEBUG

INTERFACE

AHB BRIDGE

AHB TO VPB

BRIDGE

(3)

TDO

PLL

MODULE

system

clock

EMULATION TRACE

(Advanced High-performance Bus)

VPB (VLSI

peripheral bus)

AMBA AHB

VPB

DIVIDER

C SERIAL

INTERFACES 0 AND 1

SPI AND SSP

SERIAL INTERFACES

UART0/UART1

REAL TIME CLOCK

WATCHDOG

TIMER

XTAL2

XTAL1

FUNCTIONS

VECTORED INTERRUPT

CONTROLLER

RST

SYSTEM

AHB

DECODER

SCL0,1

SDA0,1

SCK0,1 MOSI0,1 MISO0,1 SSEL0,1

TXD0,1 RXD0,1

(1)

DSR1

(1)

RTS1

(1)

DCD1

RTXC1 RTXC2 V

BAT

,CTS1

, DTR1

(1)

,RI1

(1)

SYSTEM

CONTROL

002aab067

(1) LPC2134/2136/2138 only. (2) LPC2132/2134/2136/2138 only. (3) Pins shared with GPIO.

Fig 1. LPC2131/2/4/6/8 block diagram

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2.1 Memory maps

The LPC2131/2/4/6/8 incorporates several distinct memory regions, shown in the following figures. user program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.

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Chapter 2: LPC2131/2/4/6/8 Memory Addressing

Rev. 01 — 24 June 2005 User manual

Figure 2 shows the overall map of the entire address space from the

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

AHB PERIPHERALS

VPB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK

(REMAPPED FROM ON-CHIP FLASH MEMORY)

32 kB ON-CHIP STATIC RAM (LPC2136/2138)

16 kB ON-CHIP STATIC RAM (LPC2132/2134)

8 kB ON-CHIP STATIC RAM (LPC2131)

RESERVED ADDRESS SPACE

0xFFFF FFFF

0xF000 0000

0xE000 0000

0xC000 0000

0x8000 0000

0x4000 8000 0x4000 7FFF

0x4000 4000 0x4000 3FFF

0x4000 2000 0x4000 1FFF

0x4000 0000

RESERVED ADDRESS SPACE

0x0008 0000

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2138)

TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2136)

TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2134)

TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2132)

TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY

0.0 GB

Fig 2. System memory map

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(LPC2131)

0x0007 FFFF 0x0004 0000

0x0003 FFFF 0x0002 0000

0x0001 FFFF 0x0001 0000

0x0000 FFFF 0x0000 8000

0x0000 7FFF 0x0000 0000

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Volume 1 Chapter 2: Memory map

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4.0 GB

4.0 GB - 2 MB

Notes:

- AHB section is 128 x 16 kB blocks (totaling 2 MB).

- VPB section is 128 x 16 kB blocks (totaling 2 MB).

3.75 GB

0xFFFF FFFF

AHB PERIPHERALS

0xFFE0 0000 0xFFDF FFFF

RESERVED

0xF000 0000 0xEFFF FFFF

RESERVED

3.5 GB + 2 MB VPB PERIPHERALS

3.5 GB

Fig 3. Peripheral memory map

Figures 3 through 5 show differe nt views of the peripheral address space. Both the AHB and VPB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the

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0xE020 0000 0xE01F FFFF

0xE000 0000

Philips Semiconductors

Volume 1 Chapter 2: Memory map

address decoding for each peripheral. All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word r egister separately.

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VECTORED INTERRUPT CONTROLLER

(AHB PERIPHERAL #126)

(AHB PERIPHERAL #125)

(AHB PERIPHERAL #124)

(AHB PERIPHERAL #3)

0xFFFF F000 (4G - 4K)

0xFFFF C000

0xFFFF 8000

0xFFFF 4000

0xFFFF 0000

0xFFE1 0000

0xFFE0 C000

(AHB PERIPHERAL #2)

0xFFE0 8000

(AHB PERIPHERAL #1)

0xFFE0 4000

(AHB PERIPHERAL #0)

0xFFE0 0000

Fig 4. AHB peripheral map

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SYSTEM CONTROL BLOCK

(VPB PERIPHERAL #127)

(VPB PERIPHERALS #28-126)

NOT USED

DAC

(VPB PERIPHERAL #27)

SSP

(VPB PERIPHERAL #26)

NOT USED

(VPB PERIPHERAL #25)

10 BIT AD1 (LPC2138)

(VPB PERIPHERAL #24)

(VPB PERIPHERAL #23)

(VPB PERIPHERAL #14-22)

(VPB PERIPHERAL #13)

(VPB PERIPHERAL #12)

PIN CONNECT BLOCK

(VPB PERIPHERAL #11)

(VPB PERIPHERAL #10)

(VPB PERIPHERAL #9)

(VPB PERIPHERAL #8)

(VPB PERIPHERAL #7)

(VPB PERIPHERAL #6)

(VPB PERIPHERAL #5)

(VPB PERIPHERAL #4)

(VPB PERIPHERAL #3)

(VPB PERIPHERAL #2)

(VPB PERIPHERAL #1)

WATCHDOG TIMER

(VPB PERIPHERAL #0)

NOT USED

10 BIT ADO

NOT USED

GPIO

RTC

SPI0

NOT USED

PWM

UART1

URT0

TIMER1

TIMER0

0xE01F FFFF 0xE01F C000

0xE007 0000

0xE006 C000

0xE006 8000

0xE006 4000

0xE006 0000

0xE005 C000

0xE003 8000

0xE003 4000

0xE003 0000

0xE002 C000

0xE002 8000

0xE002 4000

0xE002 0000

0xE001 C000

0xE001 8000

0xE001 4000

0xE001 0000

0xE000 C000

0xE000 8000

0xE000 4000

0xE000 0000

Fig 5. VPB peripheral map

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Volume 1 Chapter 2: Memory map

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2.2 LPC2131/2132/2134/2136/2138 memory re-mapping and boot block

2.2.1 Memory map concepts and operating modes

The basic concept on the LPC2131/2/4/6/8 is that each memory area has a "natural" location in the memory map. This is the address ran ge f or which code re siding in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.

Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of interrupts in the different operating modes described in interrupts is accomplished via the Memory Mapping Control feature ( Section 3. 6 “Memory

mapping control” on page 25).

Table 2: ARM exception vector locations

Address Exception

0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort (instruction fetch memory fault) 0x0000 0010 Data Abort (data access memory fault) 0x0000 0014 Reserved

0x0000 0018 IRQ 0x0000 001C FIQ

0000 through 0x0000 001C, as shown in Table 2 below), a small portion of the

Table 3. Re-mapping of the

Note: Identified as reserved in ARM documentation, this location is used by the Boot Loader as the Valid User Program key. This is descibed in detail in "Flash Memory System and Programming" chapter on

page 216.

Table 3: LPC2131/2/4/6/8 memory mapping modes

Mode Activation Usage

Boot Loader mode

User Flash mode

User RAM mode

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Hardware activation by any Reset

Software activation by Boot code

Software activation by User program

The Boot Loader always executes after any reset. The Boot Block interrupt vectors are mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process.

Activated by Boot Loader when a valid User Program Signature is recognized in memory and Boot Loader operation is not forced. Interrupt vectors are not re-mapped and are found in the bottom of the Flash memory.

Activated by a User Program as desired. Interrupt vectors are re-mapped to the bottom of the Static RAM.

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Volume 1 Chapter 2: Memory map

2.2.2 Memory re-mapping

In order to allow for compatibility with future derivatives, the entire Boot Block is mapped to the top of the on-chip memory space. In this manner, the use of larger or smaller flash modules will not require changing the location of the Boot Block (which would require changing the Boot Loader code itself) or changin g the mapping of t he Boot Bloc k interrupt vectors. Memory spaces other than the interrupt vectors remain in fixed locations.

Figure 6 shows the on-chip memory mapping in the modes defined above.

The portion of memory that is re-mapped to allow interrupt processing in different modes includes the interrupt vector area (32 64

bytes. The re-mapped code locations overlay addresses 0x0000 0000 through 0x0000 handler at address 0x0000 vector contained in the SRAM, e xternal memory, and Boot Block must contain br anches to the actual interrupt handlers, or to other instructions that accomplish the branch to the interrupt handlers.

There are three reasons this configuration was chosen:

1. To give the FIQ handler in t he Flash memory the advantage of not having to take a memory boundary caused by the remapping into account.

2. Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space.

3. To provide space to store constants for jumping beyond the range of single word branch instructions.

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bytes) and an additional 32 bytes, for a total of

003F. A typical user program in the Flash memory can place the entire FIQ

001C without any need to consider memory boundaries. The

Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to appear in their original location in addition to the re-mapped address.

Details on re-mapping and examples can be found in Section 3.6 “ Memory mapping

control” on page 25.

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2.0 GB - 12 kB

2.0 GB

12 kB BOOT BLOCK

(RE-MAPPED FROM TOP OF FLASH MEMORY)

(BOOT BLOCK INTERRUPT VECTORS)

RESERVED ADDRESSING SPACE

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0x8000 0000 0x7FFF FFFF

1.0 GB

32 kB ON-CHIP SRAM

(SRAM INTERRUPT VECTORS)

RESERVED ADDRESSING SPACE

(12 kB BOOT BLOCK RE-MAPPED TO HIGHER ADDRESS RANGE)

512 kB FLASH MEMORY

0x4000 8000 0x4000 7FFF

0x4000 0000 0x3FFF FFFF

0x0008 0000 0x0007 FFFF

0.0 GB

Note: Memory regions are not drawn to scale.

Fig 6. Map of lower memory is showing re-mapped and re-mappable areas (LPC2138

with 512 kB Flash)

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ACTIVE INTERRUPT VECTORS (FROM FLASH, SRAM, OR BOOT BLOCK)

0x0000 0000

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Volume 1 Chapter 2: Memory map

2.3 Prefetch abort and data abort exceptions

The LPC2131/2/4/6/8 generates the approp riate bus cycle abort exception if an access is attempted for an a ddress t hat is in a re serve d or u nassign ed addre ss r eg ion. T he regi ons are:

• Areas of the memory map that are not implemented for a specific ARM derivative. F or

the LPC2131/2/4/6/8, this is: – Address space between On-Chip Non-Volatile Memory and On-Chip SRAM,

labelled "Reserved Address Space" in device this is memory address range from 0x0000 8000 to 0x3FFF FFFF, for 64 kB Flash device this is memory address range from 0x0001 128

kB Flash device this is memory address range from 0x0002 0000 to 0x3FFF 0x0004 0x0008

– Address space between On-Chip Static RAM and the Boot Block. Labelled

"Reserved Address Space" in address range from 0x4000 2000 to 0x7FFF CFFF, for 16 kB SRAM device this is memory address range from 0x4000 device this range is from 0x4000

– Address space between 0x8000 0000 and 0xDFFF FFFF, labelled "Reserved

Adress Space".

– Reserved regions of the AHB and VPB spaces. See Figure 3.

• Unassigned AHB peripheral spaces. See Figure 4.

• Unassigned VPB peripheral spaces. See Figure 5.

FFFF, for 256 kB Flash device this is memory address range from 0000 to 0x3FFF FFFF while for 512 kB Flash device this range is from 0000 to 0x3FFF FFFF.

Figure 2. For 8 kB SRAM device this is memory

8000 to 0x7FFF CFFF.

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Figure 2 and Figure 6. For 32 kB Flash

0000 to 0x3FFF FFFF, for

4000 to 0x7FFF CFFF, while for 32 kB SRAM

For these areas , both at tempt ed data access and inst ruction fetch generate an exception. In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to an AHB or VPB peripheral address.

Within the address space of an existing VPB peripheral , a data abort exception is not generated in response to an access to an undefined address. Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself. For example, an access to address 0 xE000 within the UART0 space) may result in an access to the register defined at address 0xE000 in the LPC2131/2/4/6/8 documentation and are not a supported feature.

Note that the ARM core stores the Prefetch Abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary.

C000. Details of such address aliasing within a peripheral space are not defined

D000 (an undefined address

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Chapter 3: System Control Block

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3.1 Summary of system control block functions

The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include:

• Crystal Oscillator

• External Interrupt Inputs

• Memory Mapping Control

• PLL

• Power Contro l

• Reset

• VPB Divider

• Wakeup Timer

Each type of function has its own register(s) if any are required and unneeded bits are defined as reserved in order to allow future expansion. Unrelated functions never share the same register addresses

3.2 Pin description

Table 4 shows pins that are associated with System Control block functions.

Table 4: Pin summary

Pin name Pin

X1 Input Crystal Oscillator Input - Input to the oscillator and internal clock

X2 Output Crystal Oscillator Output - Output from the oscillator amplifier EINT0 Input External Interrupt Input 0 - An active low/high level or

EINT1 Input External Interrupt Input 1 - See the EINT0 description above.

Pin description

direction

generator circuits

falling/rising edge general purpose interrupt input. This pin may be used to wake up the processor from Idle or Power-down modes.

Pins P0.1 and P0.16 can be selected to perform EINT0 function.

Pins P0.3 and P0.14 can be selected to perform EINT1 function. Important: LOW level on pin P0.14 immediately after reset is

considered as an external hardware request to start the ISP command handler. More details on ISP and Serial Boot Loader can be found in "Flash Memory System and Programming" chapter on page 216.

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Table 4: Pin summary

Pin name Pin

EINT2 Input External Interrupt Input 2 - See the EINT0 description above.

EINT3 Input External Interrupt Input 3 - See the EINT0 description above.

RESET Input External Reset input - A LOW on this pin resets the chip, causing

3.3 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

Table 5: Summary of system control registers

Name Description Access Reset

External Interrupts

EXTINT External Interrupt Flag Register R/W 0 0xE01F C140 EXTWAKE External Interrupt Wakeup Register R/W 0 0xE01F C144 EXTMODE External Interrupt Flag register R/W 0 0xE01F C148 EXTPOLAR External Interrupt Wakeup Register R/W 0 0xE01F C14C

Memory Mapping Control

MEMMAP Memory Mapping Control R/W 0 0xE01F C040

Phase Locked Loop

PLLCON PLL Control Register R/W 0 0xE01F C080 PLLCFG PLL Configuration Register R/W 0 0xE01F C084 PLLSTAT PLL Status Register RO 0 0xE01F C088 PLLFEED PLL Feed Register WO NA 0xE01F C08C

Power Control

PCON Power Control Register R/W 0 0xE01F C0C0 PCONP Power Control for Peripherals R/W 0x03BE 0xE01F C0C4

VPB Divider

VPBDIV VPB Divider Control R/W 0 0xE01F C100

Reset

RSID Reset Source Identification Register R/W 0 0xE01F C180

Code Security/Debugging

CSPR Code Secur ity Protection Register RO o 0xE01F C184

direction

UM10120

Pin description

Pins P0.7 and P0.15 can be selected to perform EINT2 function.

Pins P0.9, P0.20 and P0.30 can be selected to perform EINT3 function.

I/O ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000

value

0000.

Address

[1]

[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.

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3.4 Crystal oscillator

While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz can be used by the LPC2131/2/4/6/8 if supplied to its input XTAL1 pin, this microcontroller’s onboard oscillator circuit supports external crystals in the range of 1 to 30

MHz only. If the on-chip PLL system or the boot-loader is used, the inp ut clock

frequency is limited to an exclusive range of 10

UM10120

MHz

MHz to 25 MHz.

The oscillator output frequency is called F referred to as CCLK f or purposes of rate equations , etc. else where in this d ocument. F

and the ARM processor clock frequency is

OSC

and CCLK are the same value unless the PLL is running and connected. Refer to the

Section 3.7 “Phase Locked Loop (PLL)” on page 26 for details and frequency limitations.

The onboard oscillator in the LPC2131/2/4/6/8 can operate in one of two modes: slave mode and oscillation mode.

In slave mode th e input clock signal should be coupled by means of a capacitor of 100 pF (C

in Figure 7, drawing a), with an amplitude of at least 200 mVrms. The X2 pin in this

configuration can be left not connected. If sla ve mode is se lected, the F duty cycle can range from 1

MHz to 50 MHz.

signal of 50-50

OSC

External components and models used in oscillation mode are shown in Figure 7, drawings b and c, and in Table 6. Since the feedbac k resistance is int egr ated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, C R

). Capacitance CP in Figure 7, drawing c, represents the parallel package capacitance

and

and should not be larger than 7 pF. Param eters FC, CL, RS and CP are supplied by the crystal manufacturer.

Choosing an oscillation mode as an on-board oscillator mode of operation limits F clock selection to 1

MHz to 30 MHz.

OSC

LPC2131/2/4/6/8 LPC2131/2/4/6/8

X1X1 X2X2

Clock

a) b) c)

Fig 7. Oscillator modes and m ode ls: a) slave mode of operation, b) oscillation mode of

operation, c) external crystal model used for C

User manual Rev. 01 — 24 June 2005 18

Xtal

X1/X2

< = >

evaluation

Philips Semiconductors

Volume 1 Chapter 3: System Control Block

UM10120

Table 6: Recommended values for C

in oscillation mode (crystal and external

X1/X2

components parameters)

Fundamental oscillation frequency F

Crystal load capacitance C

Maximum crystal

series resistance R

External load capacitors CX1,

1 MHz - 5 MHz 10 pF NA NA

20 pF NA NA 30 pF < 300 Ω 58 pF, 58 pF

5 MHz - 10 MHz 10 pF < 300 Ω 18 pF, 18 pF

20 pF < 300 Ω 38 pF, 38 pF 30 pF < 300 Ω 58 pF, 58 pF

10 MHz - 15 MHz 10 pF < 300 Ω 18 pF, 18 pF

20 pF < 220 Ω 38 pF, 38 pF 30 pF < 140 Ω 58 pF, 58 pF

15 MHz - 20 MHz 10 pF < 220 Ω 18 pF, 18 pF

20 pF < 140 Ω 38 pF, 38 pF 30 pF < 80 Ω 58 pF, 58 pF

20 MHz - 25 MHz 10 pF < 160 Ω 18 pF, 18 pF

20 pF < 90 Ω 38 pF, 38 pF 30 pF < 50 Ω 58 pF, 58 pF

25 MHz - 30 MHz 10 pF < 130 Ω 18 pF, 18 pF

20 pF < 50 Ω 38 pF, 38 pF 30 pF NA NA

CX2

selection

OSC

True

MIN f

= 10 MHz

OSC

MAX f

(Figure 7, mode a and/or b) (Figure 7, mode a) (Figure 7, mode b)

Fig 8. F

User manual Rev. 01 — 24 June 2005 19

OSC

= 25 MHz

OSC

selection algorithm

On-chip PLL used

in application?

False

ISP used for initial

code download?

False

External crystal oscillator used?

False

MIN f

= 1 MHz

OSC

MAX f

= 50 MHz

OSC

True

MIN f

MAX f

= 1 MHz

OSC

= 30 MHz

OSC

Philips Semiconductors

Volume 1 Chapter 3: System Control Block

3.5 External interrupt inputs

The LPC2131/2/4/6/8 includes four External Interrupt Inputs as selectable pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.

3.5.1 Register description

The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags, and the EXTWAKEUP register contains bits that enable individual external interrupts to wake up the microcontroller from Power-down mode. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.

Table 7: External interrupt registers

Name Description Access Reset

EXTINT The External In terrupt Flag Register contains

interrupt flags for EINT0, EINT1, EINT2 and EINT3. See

INTWAKE The Interrupt Wakeup Register contains four

enable bits that control whether each external interrupt will cause the processor to wake up from Power-down mode. See

EXTMODE The External Interrupt Mode Register controls

whether each pin is edge- or levelsensitive.

EXTPOLAR The External Interrupt Polarity Register controls

which level or edge on each pin will cause an interrupt.

Table 8.

Table 9.

UM10120

Address

[1]

value

R/W 0 0xE01F C140

R/W 0 0xE01F C144

R/W 0 0xE01F C148

R/W 0 0xE01F C14C

[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.

3.5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)

When a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in this register. This asserts the corresponding interrupt request to the VIC, which will cause an interrupt if interrupts from the pin are enabled.

Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive state.

Once a bit from EINT0 to EINT3 is set and an appropriate code starts to e xecut e (handling wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise the event that was just triggered by activity on the EINT pin will not be recognized in the future.

Important: whenever a change of external interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in the EXTINT register must be cleared! For details see

3.5.4 “External Interrupt Mode register (EXTMODE - 0xE01F C148)” and Section 3.5.5 “External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”.

Section

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For example, if a system wakes up from power-down using a low level on external interrupt 0 pin, its post-wakeup code m ust reset the EINT0 bit in order to allow futur e entry into the power-down mode. If the EINT0 bit is left set to 1, subsequent attempt(s) to invoke power-down mode will fail. The same goes for external interrupt handling.

More details on power-down mode will be discussed in the following chapters.

Table 8: External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description

Bit Symbol Description Reset

0 EINT0 In le v el-sensitiv e mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin.

Up to two pins can be selected to perform the EINT0 function (see P0.1 and P0.16 description in "Pin Configuration" chapter

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its activ e state (e.g. if EINT0 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).

1 EINT1 In le v el-sensitiv e mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin.

Up to two pins can be selected to perform the EINT1 function (see P0.3 and P0.14 description in "Pin Configuration" chapter on page 64.)

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT1 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).

2 EINT2 In le v el-sensitiv e mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin.

Up to two pins can be selected to perform the EINT2 function (see P0.7 and P0.15 description in "Pin Configuration" chapter on page 64.)

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT2 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).

3 EINT3 In le v el-sensitiv e mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin.

Up to three pins can be selected to perform the EINT3 function (see P0.9, P0.20 and P0.30 description in "Pin Configuration" chapter on page 64.)

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT3 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).

7:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved

bit is not defined.

page 64.)

UM10120

value

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3.5.3 Interrupt Wakeup register (INTWAKE - 0xE01F C144)

Enable bits in the INTWAKE register allow the external interrupts to wake up the processor if it is in Po we r-do wn mode . The relate d EINTn function m ust be mapped to the pin in order for the wakeup process to take place. It is not necessary for the interrupt to be enabled in the Vectored Interrupt Controller for a wakeup to take place. This arrang ement allows additional capabilities, such as having an external interrupt input wake up the processor from P ower-down mode without causing an interrupt (simply resuming operation), or allowing an interrupt to be enabled during Power-down without waking the processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application).

For an external interrupt pin to be a source that would wake up the microcontroller from Po wer-down mode, it is also necessary to clear the corresponding bit in the External Interrupt Flag register (

Table 9: Interrupt Wakeup register (INTW AKE - address 0xE01F C144) bit description

Bit Symbol Description Reset

0 EXTWAKE0 When one, assertion of EINT0 will wake up the processor from

1 EXTWAKE1 When one, assertion of EINT1 will wake up the processor from

2 EXTWAKE2 When one, assertion of EINT2 will wake up the processor from

3 EXTWAKE3 When one, assertion of EINT3 will wake up the processor from

13:4 - Reserved, user software should not write ones to reserved bits.

14 BODWAKE When one, a BOD interrupt will wake up the processor from

15 RTCWAKE When one, assertion of an RTC interrupt will wake up the

Section 3.5.2 on page 20).

Power-down mode.

The value read from a reserved bit is not defined.

Power-down mode.

processor from Power-down mode.

UM10120

value

3.5.4 External Interrupt Mode register (EXTMODE - 0xE01F C148)

The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function (see chapter Pin Connect Block on enabled via the VICIntEnable register (Section 5.4.4 “Interrupt Enable register

(VICIntEnable - 0xFFFF F010)” on page 52) can cause interrupts from the External

Interrupt function (though of course pins selected for other functions may cause interrupts from those functions).

Note: Software should only change a bit in this register when its interrupt is disabled in the VICIntEnable register, and should write the corresponding 1 to the EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear the EXTINT bit that could be set by changing the mode.

User manual Rev. 01 — 24 June 2005 22

page 73) and

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Volume 1 Chapter 3: System Control Block

Table 10: External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit

Bit Symbol Value Description Reset

0 EXTMODE0 0 Level-sensitivity is selected for EINT0. 0

1 EXTMODE1 0 Level-sensitivity is selected for EINT1. 0

2 EXTMODE2 0 Level-sensitivity is selected for EINT2. 0

3 EXTMODE3 0 Level-sensitivity is selected for EINT3. 0

7:4 - - Reserved, user software should not write ones to reserved

3.5.5 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)

In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive . Only pins that are selected for the EINT function (see "Pin Connect Block" chapter on

“Interrupt Enable register (VICIntEnable - 0xFFFF F010)” on page 52) can cause

interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functio ns ).

UM10120

description

value

1 EINT0 is edge sensitive.

1 EINT1 is edge sensitive.

1 EINT2 is edge sensitive.

1 EINT3 is edge sensitive.

bits. The value read from a reserved bit is not defined.

page 73) and enabled in the VICIntEnable register (Section 5.4.4

Table 11: External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit

description

Bit Symbol Value Description Reset

value

0 EXTPOLAR0 0 EINT0 is low-active or falling-edge sensitive (depending on

EXTMODE0).

1 EINT0 is high-active or rising-edge sensitive (depending on

EXTMODE0).

1 EXTPOLAR1 0 EINT1 is low-active or falling-edge sensitive (depending on

EXTMODE1).

1 EINT1 is high-active or rising-edge sensitive (depending on

EXTMODE1).

2 EXTPOLAR2 0 EINT2 is low-active or falling-edge sensitive (depending on

EXTMODE2).

1 EINT2 is high-active or rising-edge sensitive (depending on

EXTMODE2).

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Table 11: External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit

Bit Symbol Value Description Reset

3 EXTPOLAR3 0 EINT3 is low-active or falling-edge sensitive (depending on

7:4 - - Reserved, user software should not write ones to reserved

3.5.6 Multiple external interrupt pins

Software can select multiple pins f or each of EINT3:0 in t he Pin Select registers , which are described in chapter Pin Connect Block on of EINT3:0 receives the state of all of its associated pins from the pins’ receivers, along with signals that indicate whether each pin is selected for the EINT function. The external interrupt logic handles the case when more than one pin is so selected, diff erently according to the state of its Mode and Polarity bits:

UM10120

description

value

EXTMODE3).

1 EINT3 is high-active or rising-edge sensitive (depending on

EXTMODE3).

bits. The value read from a reserved bit is not defined.

page 73. The external interrupt logic for each

• In Low-Active Le v el Sensitiv e mode , the states o f all pins selected f or the same EINTx

functionality are digitally combined using a positive logic AND gate.

• In High-Active Level Sensitive mode, the states of all pins selected for the same

EINTx functionality are digitally combined using a positive logic OR gate.

• In Edge Sensitive mode, regardless of polarity, the pin with the lowest GPIO port

number is used. (Selecting multiple pins for an EINTx in edge-sensitive mode could be considered a programming error.)

The signal derived by this logic is the EINTi signal in the following logic schematic

Figure 9.

For ex ample, if the EINT3 function is selected in the PINSEL0 and PINSEL1 registers for pins P0.9, P0.20 and P0.30, and EINT3 is configured to be low level sensitive, the inputs from all three pins will be logically ANDed. When more than one EINT pin is logically ORed, the interrupt service routine can read the states of the pins from the GPIO port using the IO0PIN and IO1PIN registers, to determine which pin(s) caused the interrupt.

User manual Rev. 01 — 24 June 2005 24

Philips Semiconductors

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UM10120

VPB Bus Data

EINTi

EXTPOLARi

EXTMODEi

Fig 9. External interrupt logic

GLITCH FILTER

Write 1 to EXTINTi

Wakeup enable

(one bit of EXTWAKE)

D Q

PCLK

Reset

VPB Read of EXTWAKE

EINTi to

Wakeup Time

(Figure 11)

Interrupt Flag

(one bit of EXTINT)

PCLK

3.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 to have control of the interrupts.

3.6.1 Memory Mapping control register (MEMMAP - 0xE01F C040)

Whenever an exception handling is necessary, the microcontroller will f etch an instruction residing on the exception cor res ponding a ddress a s de scribed in

vector locations” on page 12. The MEMMAP register determines the source of data that

will fill this table.

0000. This allows code running in diffe rent memory spaces

Table 2 “ARM exception

User manual Rev. 01 — 24 June 2005 25

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Volume 1 Chapter 3: System Control Block

Table 12: Memory Mapping control register (MEMMAP - address 0xE01F C040) bit

Bit Symbol Value Description Reset

1:0 MAP 00 Boot Loader Mode. Interrupt vectors are re-mapped to Boot

7:2 - - Reserved, user software should not write ones to reserved

3.6.2 Memory mapping control usage notes

The Memory Mapping Control simply selects one out of three available sources of data (sets of 64 bytes each) necessary for handling ARM exceptions (interrupts).

UM10120

description

value

Block.

01 User Flash Mode. Interrupt vectors are not re-mapped and

reside in Flash.

10 User RAM Mode. Interrupt vectors are re-mapped to Static

RAM. 11 Reserved. Do not use this option. Warning: Improper setting of this value may result in incorrect

operation of the device.

bits. The value read from a reserved bit is not defined.

For example, whenever a Software Interrupt request is generated, the ARM core will always fetch 32-bit data "residing" on 0x0000

locations” on page 12. This means that when MEMMAP[1:0]=10 (User RAM Mode), a

read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of MEMMAP[1:0]=00 (Boot Loader Mode), a read/fetch from 0x0000 available also at 0x7FFF

3.7 Phase Locked Loop (PLL)

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up into the CCLK with the range of 10 a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on the LPC2131/2/4/6/8 due to the upper frequency limit of the CPU). The CCO operates in the range of 156 320

MHz, so there is an additional divider in the loop to k eep the CCO wit hin its freq uency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to p roduce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle. A block diagram of the PLL is shown in

PLL activation is controlled via the PLLCON register . The PLL multiplier and divider values are controlled by the PLLCFG register. These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all chip operations, including the Watchdog Timer, are dependent on the PLL when it is providing the chip clock, accidental changes to the PLL setup could re sult in une xpected beha vior of the microcontroller. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLLFEED register.

0008 see Table 2 “ARM exception vector

0008 will provide data

E008 (Boot Block remapped from on-chip Bootloader).

MHz to 60 MHz using

MHz to

Figure 10.

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Philips Semiconductors

Volume 1 Chapter 3: System Control Block

The PLL is turned off and bypassed following a chip Reset and when by entering Pow er-down mode. The PLL is en abled b y softw are only. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.

3.7.1 Register description

The PLL is controlled by the registers shown in Table 13. More detailed descriptions follow.

Warning: Impr oper setting of t he PLL value s may result in incorrect operation of the device!

Table 13: PLL registers

Name Description Access Reset

PLLCON PLL Control Register. Holding register for

PLLCFG PLL Configuration Register. Holding register for

PLLSTAT PLL Status Register. Read-back register for

PLLFEED PLL Feed Register. This register enables

updating PLL control bits. Values written to this register do not take effect until a valid PLL feed sequence has taken place.

updating PLL configuration values. Values written to this register do not take effect until a valid PLL feed sequence has taken place.

PLL control and configuration information. If PLLCON or PLLCFG have been written to, but a PLL feed sequence has not yet occurred, they will not reflect the current PLL state. Reading this register provides the actual values controlling the PLL, as well as the status of the PLL.

loading of the PLL control and configuration information from the PLLCON and PLLCFG registers into the shadow registers that actually affect PLL operation.

UM10120

Address

[1]

value

R/W 0 0xE01F C080

R/W 0 0xE01F C084

RO 0 0xE01F C088

WO NA 0xE01F C08C

[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.

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UM10120

PLLC

PLLE

OSC

PSEL[1:0]

PLOCK

MSEL[4:0]

CLOCK

SYNCHRONIZATION

Direct

Bypass

PHASE-

FREQUENCY

DETECTOR

OUT

DIV-BY-M

MSEL<4:0>

CCO

/2P

CCLK

Fig 10. PLL block diagram

3.7.2 PLL Control register (PLLCON - 0xE01F C080)

The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting the PLL causes the processor and all chip functions to run from the PLL output clock. Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given (see

0xE01F C08C)” and Section 3.7.3 “PLL Configuration register (PLLCFG - 0xE01F C084)” on page 29).

User manual Rev. 01 — 24 June 2005 28

Section 3.7.7 “PLL Feed register (PLLFEED -

Philips Semiconductors

Volume 1 Chapter 3: System Control Block

Table 14: PLL Control register (PLLCON - address 0xE01F C080) bit description

Bit Symbol Description Reset

0 PLLE PLL Enable. When one, and after a valid PLL feed, this bit will

1 PLLC PLL Connect. When PLLC and PLLE are both set to one, and after a

7:2 - Reserved, user software should not write ones to reserved bits. The

The PLL must be set up, enabled, and Lock established before it may be used as a clock source. When switching from the oscillator clock to the PLL output or vice versa, internal circuitry synchronizes the operation in order to ensure that glitches are not generated. Hardware does not insure that the PLL is loc ked before it is connected or automatically disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is likely that the oscillator clock has become unstable and disconnecting the PLL will not remedy the situation.

UM10120

activate the PLL and allow it to lock to the requested frequency. See PLLSTAT register,

valid PLL feed, connects the PLL as the clock source for the microcontroller. Otherwise, the oscillator clock is used directly by the microcontroller. See PLLSTAT register,

value read from a reserved bit is not defined.

Table 16.

value

3.7.3 PLL Configuration register (PLLCFG - 0xE01F C084)

The PLLCFG register contains the PLL multiplier and divider values. Changes to the PLLCFG register do not take effect until a correct PLL feed sequence has been given (see

Section 3.7.7 “PLL Feed register (PLLFEED - 0xE01F C08C)” on page 30). Calculations

for the PLL frequency, and multiplier and divider values are found in the PLL Frequency Calculation section on

Table 15: PLL Configuration register (PLLCFG - address 0xE01F C084) bit description

Bit Symbol Description Reset

4:0 MSEL PLL Multipl ier value. Supplies the value "M" in the PLL frequency

6:5 PSEL PLL Divider value. Supplies the value "P" in the PLL frequency

7 - Reserved, user software should not write ones to reserved bits. The

page 31.

calculations. Note: For details on selecting the right value for MSEL see Section

3.7.9 “PLL frequency calculation” on page 31.

calculations. Note: For details on selecting the right value for PSEL see Section

3.7.9 “PLL frequency calculation” on page 31.

value read from a reserved bit is not defined.

3.7.4 PLL Status register (PLLSTA T - 0xE01F C088)

value

The read-only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred (see

0xE01F C08C)”).

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Section 3.7.7 “PLL Feed register (PLLFEED -

Philips Semiconductors

Volume 1 Chapter 3: System Control Block

Table 16: PLL Status register (PLLSTAT - address 0xE01F C088) bit description

Bit Symbol Description Reset

4:0 MSEL Read-back for the PLL Multiplier value. This is the value currently

6:5 PSEL Read-back for the PLL Divider value. This is the value currently

7 - Reserved, user software should not write ones to reserved bits.

8 PLLE Read-back for the PLL Enable bit. When one, the PLL is currently

9 PLLC Read-back for the PLL Connect bit. When PLLC and PLLE are both

10 PLOCK Reflects the PLL Lock status. When zero, the PLL is not locked.

15:11 - Reserved, user software should not write ones to reserved bits.

UM10120

value

used by the PLL.

The value read from a reserved bit is not defined.

0 activated. When zero, the PLL is turned off. This bit is automatically cleared when Power-down mode is activated.

0 one, the PLL is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, the PLL is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated.

0 When one, the PLL is locked onto the requested frequency.

NA The value read from a reserved bit is not defined.

3.7.5 PLL Interrupt

The PLOCK bit in the PLLSTA T register is connected t o the interrupt controller . This allo ws for software to turn on the PLL and continue wit h other function s without ha ving t o wait f or the PLL to achieve lock. When the interrupt occurs (PLOCK connected, and the interrupt disabled.

3.7.6 PLL Modes

The combinations of PLLE and PLLC are shown in Table 17.

Table 17: PLL Control bit combinations

PLLC PLLE PLL Function

0 0 PLL is turned off and disconnected. The system runs from the unmodified clock

input.

0 1 The PLL is active, but not yet connected. The PLL can be connected after

PLOCK is asserted.

1 0 Same as 00 combination. This prevents the possibility of the PLL being

connected without also being enabled.

1 1 The PLL is active and has been connected as the system clock source.

3.7.7 PLL Feed register (PLLFEED - 0xE01F C08C)

A correct feed sequence must be written to the PLLFEED register in order for changes to the PLLCON and PLLCFG registers to take effect. The feed sequence is:

= 1), the PLL may be

1. Write the value 0xAA to PLLFEED.

2. Write the value 0x55 to PLLFEED.

User manual Rev. 01 — 24 June 2005 30

+ 240 hidden pages