Philips LPC2114, LPC2124, LPC2212, LPC2214 DATA SHEET

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LPC2114/2124/2212/2214 USER MANUAL

Preliminary Supersedes data of 2004 Feb 03

 

2004 May 03

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

2 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table of Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ARM7TDMI-S Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

On-Chip Flash Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

On-Chip Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

LPC2114/2124/2212/2214 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

LPC2114/2124/2212/2214 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

LPC2114/2124/2212/2214 Memory Re-mapping and Boot Block . . . . . . . . . . . . . . . . . . . . . . . . . 37

Prefetch Abort and Data Abort Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

External Memory Controller (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Typical Bus Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

External Memory Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

System Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Summary of System Control Block Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

External Interrupt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Memory Mapping Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

PLL (Phase Locked Loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Power Control Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

VPB Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Memory Accelerator Module (MAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Memory Accelerator Module Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

MAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

MAM Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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LPC2114/2124/2212/2214ARM-based Microc ontroller

Vectored Interrupt Controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

VIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Spurious Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

VIC Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

LPC2114/2124 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Pin Description for LPC2114/2124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

LPC2212/2214 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Pin Description for LPC2212/2214 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Pin Connect Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Boot Control on 144-pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

GPIO Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

UART0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

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Timer0 and Timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Example Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Pulse Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Pin DescriptionS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Miscellaneous Register Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Consolidated Time Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Time Counter Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Alarm Register Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

RTC Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Reference Clock Divider (Prescaler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Usage Notes on Watchdog Reset and External Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Flash Memory System and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Flash Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Flash boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Boot process FlowChart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Sector Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Code Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

JTAG FLASH Programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

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EmbeddedICE Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Reset State of Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Reset State of Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

How to Enable RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

RealMonitor build options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

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LPC2114/2124/2212/2214ARM-based Microc ontroller

List of Figures

Figure 1: LPC2114/2124/2212/2214 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2: System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 3: Peripheral Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 4: AHB Peripheral Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5: VPB Peripheral Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 6: Map of lower memory is showing re-mapped and re-mappable areas (128 kB Flash).. . . . . . . 39

Figure 7: 32 Bit Bank External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 8: 16 Bit Bank External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 9: 8 Bit Bank External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 10: External memory read access (WST1=0 and WST1=1 examples) . . . . . . . . . . . . . . . . . . . . . . 46

Figure 11: External memory write access (WST2=0 and WST2=1 examples) . . . . . . . . . . . . . . . . . . . . . . 46

Figure 12: Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation,

c) external crystal model used for CX1/X2 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 13: FOSC selection algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 14: External Interrupt Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 15: PLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 16: Reset Block Diagram including Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 17: VPB Divider Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 18: Simplified Block Diagram of the Memory Accelerator Module . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 19: Block Diagram of the Vectored Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 20: LPC2114/2124 64-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 21: LPC2212/2214 144-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 22: UART0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 23: UART1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 24: I2C Bus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 25: Slave Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 26: Format in the master transmitter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 27: Format of master receiver mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 28: A master receiver switch to master transmitter after sending repeated START. . . . . . . . . . . . 150

Figure 29: Slave Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 30: Format of slave receiver mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 31: Format of slave transmitter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 32: I2C Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 33: SPI Data Transfer Format (CPHA = 0 and CPHA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 34: SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 35: A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.. . . 176

Figure 36: A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled. . . . 176

Figure 37: Timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 38: PWM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 39: Sample PWM waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 40: RTC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 41: RTC Prescaler block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 42: Watchdog Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 43: Map of lower memory after any reset (128 kB Flash part).. . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 44: Boot Process flowchart (Bootloader revisions before 1.61) . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 45: Boot Process flowchart (Bootloader revisions 1.61 and later) . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 46: IAP Parameter passing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 47: EmbeddedICE Debug Environment Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 48: ETM Debug Environment Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 49: RealMonitor components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 50: RealMonitor as a state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 51: Exception Handlers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

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8 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

List of Tables

Table 1: LPC2114/2124/2212/2214 device information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2: LPC2114/2124/2212/2214 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 3: ARM Exception Vector Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 4: LPC2114/2124/2212/2214 Memory Mapping Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 5: Address Ranges of External Memory Banks (LPC2212/2214 only) . . . . . . . . . . . . . . . . . . . . . . 41

Table 6: External Memory Controller Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 7: External Memory Controller Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 8: Bank Configuration Registers 0-3 (BCFG0-3 - 0xFFE00000-0C). . . . . . . . . . . . . . . . . . . . . . . . 43

Table 9: Default memory widths at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 10: External memory and system requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 11: Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 12: Summary of System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 13: Recommended values for CX1/X2 in oscillation mode

(crystal and external components parameters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 14: External Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 15: External Interrupt Flag Register (EXTINT - 0xE01FC140). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 16: External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144) . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 17: External Interrupt Mode Register (EXTMODE - 0xE01FC148) . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 18: External Interrupt Polarity Register (EXTPOLAR - 0xE01FC14C). . . . . . . . . . . . . . . . . . . . . . . . 57

Table 19: MEMMAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 20: Memory Mapping Control Register (MEMMAP - 0xE01FC040). . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 21: PLL Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 22: PLL Control Register (PLLCON - 0xE01FC080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 23: PLL Configuration Register (PLLCFG - 0xE01FC084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 24: PLL Status Register (PLLSTAT - 0xE01FC088) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 25: PLL Control Bit Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 26: PLL Feed Register (PLLFEED - 0xE01FC08C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 27: PLL Divider Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 28: PLL Multiplier Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 29: Power Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 30: Power Control Register (PCON - 0xE01FC0C0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 31: Power Control for Peripherals Register for LPC2114/2124 (PCONP - 0xE01FC0C4) . . . . . . . . 67

Table 32: Power Control for Peripherals Register for LPC2212/2214 (PCONP - 0xE01FC0C4) . . . . . . . . 67

Table 33: VPBDIV Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 34: VPB Divider Register (VPBDIV - 0xE01FC100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 35: MAM Responses to Program Accesses of Various Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 36: MAM Responses to Data and DMA Accesses of Various Types. . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 37: Summary of System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 38: MAM Control Register (MAMCR - 0xE01FC000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 39: MAM Timing Register (MAMTIM - 0xE01FC004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 40: VIC Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 41: Software Interrupt Register (VICSoftInt - 0xFFFFF018, Read/Write) . . . . . . . . . . . . . . . . . . . . . 82

Table 42: Software Interrupt Clear Register (VICSoftIntClear - 0xFFFFF01C, Write Only). . . . . . . . . . . . . 82

Table 43: Raw Interrupt Status Register (VICRawIntr - 0xFFFFF008, Read-Only). . . . . . . . . . . . . . . . . . . 82

Table 44: Interrupt Enable Register (VICINtEnable - 0xFFFFF010, Read/Write) . . . . . . . . . . . . . . . . . . . . 83

Table 45: Software Interrupt Clear Register (VICIntEnClear - 0xFFFFF014, Write Only) . . . . . . . . . . . . . . 83

Table 46: Interrupt Select Register (VICIntSelect - 0xFFFFF00C, Read/Write) . . . . . . . . . . . . . . . . . . . . . 83

Table 47: IRQ Status Register (VICIRQStatus - 0xFFFFF000, Read-Only) . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 48: IRQ Status Register (VICFIQStatus - 0xFFFFF004, Read-Only) . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 49: Vector Control Registers (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write) . . . . . . . . . . . . . . 84

Table 50: Vector Address Registers (VICVectAddr0-15 - 0xFFFFF100-13C, Read/Write). . . . . . . . . . . . . 84

Table 51: Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write) . . . . . . . . . . . . 84

Table 52: Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write). . . . . . . . . . . . . . . . . . . . . 85

Table 53: Protection Enable Register (VICProtection - 0xFFFFF020, Read/Write). . . . . . . . . . . . . . . . . . . 85

Table 54: Connection of Interrupt Sources to the Vectored Interrupt Controller . . . . . . . . . . . . . . . . . . . . . 86

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LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 55: Pin description for LPC2114/2124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 56: Pin description for LPC2212/2214 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 57: Pin Connect Block Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 58: Pin Function Select Register 0 for LPC2114/2124/2212/2214 (PINSEL0 - 0xE002C000). . . . 110

Table 59: Pin Function Select Register 1 for LPC2114/2124/2212/2214 (PINSEL1 - 0xE002C004) . . . . 110

Table 60: Pin Function Select Register 2 for LPC2114/2124 (PINSEL2 - 0xE002C014) . . . . . . . . . . . . . 111

Table 61: Pin Function Select Register 2 for LPC2212/2214 (PINSEL2 - 0xE002C014) . . . . . . . . . . . . . 112

Table 62: Pin Function Select Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 63: Boot Control on BOOT1:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 64: GPIO Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 65: GPIO Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 66: GPIO Pin Value Register (IO0PIN - 0xE0028000, IO1PIN - 0xE0028010,

IO2PIN - 0xE0028020, IO3PIN - 0xE0028030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 67: GPIO Output Set Register (IO0SET - 0xE0028004, IO1SET - 0xE0028014,

IO2SET - 0xE0028024, IO3SET - 0xE0028034) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 68: GPIO Output Clear Register (IO0CLR - 0xE002800C, IO1CLR - 0xE002801C,

IO2CLR - 0xE002802C, IO3CLR - 0xE002803C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 69: GPIO Direction Register (IO0DIR - 0xE0028008, IO1DIR - 0xE0028018,

IO2DIR - 0xE0028028, IO3DIR - 0xE0028038). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 70: UART0 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 71: UART0 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 72: UART0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only). . . . . . 123

Table 73: UART0 Transmit Holding Register (U0THR - 0xE000C000 when DLAB = 0, Write Only). . . . . 123

Table 74: UART0 Divisor Latch LSB Register (U0DLL - 0xE000C000 when DLAB = 1). . . . . . . . . . . . . . 123

Table 75: UART0 Divisor Latch MSB Register (U0DLM - 0xE000C004 when DLAB = 1). . . . . . . . . . . . . 123

Table 76: UART0 Interrupt Enable Register Bit Descriptions (U0IER - 0xE000C004 when DLAB = 0) . . 124 Table 77: UART0 Interrupt Identification Register Bit Descriptions (U0IIR - 0xE000C008, Read Only) . . 124

Table 78: UART0 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 79: UART0 FIFO Control Register Bit Descriptions (U0FCR - 0xE000C008) . . . . . . . . . . . . . . . . . 126

Table 80: UART0 Line Control Register Bit Descriptions (U0LCR - 0xE000C00C). . . . . . . . . . . . . . . . . . 127

Table 81: UART0 Line Status Register Bit Descriptions (U0LSR - 0xE000C014, Read Only) . . . . . . . . . 128

Table 82: UART0 Scratchpad Register (U0SCR - 0xE000C01C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 83: UART1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 84: UART1 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 85: UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only). . . . . . 135

Table 86: UART1 Transmit Holding Register (U1THR - 0xE0010000 when DLAB = 0, Write Only). . . . . 135

Table 87: UART1 Divisor Latch LSB Register (U1DLL - 0xE0010000 when DLAB = 1). . . . . . . . . . . . . . 135

Table 88: UART1 Divisor Latch MSB Register (U1DLM - 0xE0010004 when DLAB = 1). . . . . . . . . . . . . 136

Table 89: UART1 Interrupt Enable Register Bi t Descriptions (U1IER - 0xE0010004 when DLAB = 0). . . 136

Table 90: UART1 Interrupt Identification Register Bit Descriptions (IIR - 0xE0010008, Read Only). . . . . 137

Table 91: UART1 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 92: UART1 FCR Bit Descriptions (U1FCR - 0xE0010008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 93: UART1 Line Control Register Bit Descriptions (U1LCR - 0xE001000C). . . . . . . . . . . . . . . . . . 140

Table 94: UART1 Modem Control Register Bit Descriptions (U1MCR - 0xE0010010) . . . . . . . . . . . . . . . 141

Table 95: UART1 Line Status Register Bit Descriptions (U1LSR - 0xE0010014, Read Only). . . . . . . . . . 142

Table 96: UART1 Modem Status Register Bit Descriptions (U1MSR - 0x0xE0010018) . . . . . . . . . . . . . . 143

Table 97: UART1 Scratchpad Register (U1SCR - 0xE001001C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 98: I2C Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 99: I2C Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 100: I2C Control Set Register (I2CONSET - 0xE001C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 101: I2C Control Clear Register (I2CONCLR - 0xE001C018). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 102: I2C Status Register (I2STAT - 0xE001C004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 103: I2C Data Register (I2DAT - 0xE001C008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 104: I2C Slave Address Register (I2ADR - 0xE001C00C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 105: I2C SCL High Duty Cycle Register (I2SCLH - 0xE001C010) . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 106: I2C SCL Low Duty Cycle Register (I2SCLL - 0xE001C014). . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 107: I2C Clock Rate Selections for VPB Clock Divider = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

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Table 108: I2C Clock Rate Selections for VPB Clock Divider = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 109: I2C Clock Rate Selections for VPB Clock Divider = 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 110: SPI Data To Clock Phase Relationship. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 111: SPI Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 112: SPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 113: SPI Control Register (S0SPCR - 0xE0020000, S1SPCR - 0xE0030000). . . . . . . . . . . . . . . . . 164

Table 114: SPI Status Register (S0SPSR - 0xE0020004, S1SPSR - 0xE0030004). . . . . . . . . . . . . . . . . . 165

Table 115: SPI Data Register (S0SPDR - 0xE0020008, S1SPDR - 0xE0030008). . . . . . . . . . . . . . . . . . . 165

Table 116: SPI Clock Counter Register (S0SPCCR - 0xE002000C, S1SPCCR - 0xE003000C). . . . . . . . 165

Table 117: SPI Interrupt Register (S0SPINT - 0xE002001C, S1SPINT - 0xE003001C). . . . . . . . . . . . . . . 166

Table 118: Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 119: TIMER0 and TIMER1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 120: Interrupt Register (IR: TIMER0 - T0IR: 0xE0004000; TIMER1 - T1IR: 0xE0008000). . . . . . . . 172

Table 121: Timer Control Register

(TCR: TIMER0 - T0TCR: 0xE0004004; TIMER1 - T1TCR: 0xE0008004). . . . . . . . . . . . . . . . . 172

Table 122: Match Control Register

(MCR: TIMER0 - T0MCR: 0xE0004014; TIMER1 - T1MCR: 0xE0008014). . . . . . . . . . . . . . . . 173

Table 123: Capture Control Register

(CCR: TIMER0 - T0CCR: 0xE0004028; TIMER1 - T1CCR: 0xE0008028) . . . . . . . . . . . . . . . . 174

Table 124: External Match Register

(EMR: TIMER0 - T0EMR: 0xE000403C; TIMER1 - T1EMR: 0xE000803C) . . . . . . . . . . . . . . . 175

Table 125: External Match Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 126: Set and Reset inputs for PWM Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 127: Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 128: Pulse Width Modulator Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 129: PWM Interrupt Register (PWMIR - 0xE0014000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 130: PWM Timer Control Register (PWMTCR - 0xE0014004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 131: PWM Match Control Register (PWMMCR - 0xE0014014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 132: PWM Control Register (PWMPCR - 0xE001404C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 133: PWM Latch Enable Register (PWMLER - 0xE0014050). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 134: A/D Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 135: A/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 136: A/D Control Register (ADCR - 0xE0034000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 137: A/D Data Register (ADDR - 0xE0034004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 138: Real Time Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 139: Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 140: Interrupt Location Register Bits (ILR - 0xE0024000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 141: Clock Tick Counter Bits (CTC - 0xE0024004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 142: Clock Control Register Bits (CCR - 0xE0024008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 143: Counter Increment Interrupt Register Bits (CIIR - 0xE002400C) . . . . . . . . . . . . . . . . . . . . . . . 202

Table 144: Alarm Mask Register Bits (AMR - 0xE0024010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 145: Consolidated Time Register 0 Bits (CTIME0 - 0xE0024014) . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 146: Consolidated Time Register 1 Bits (CTIME1 - 0xE0024018) . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 147: Consolidated Time Register 2 Bits (CTIME2 - 0xE002401C) . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 148: Time Counter Relationships and Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 149: Time Counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 150: Alarm Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 151: Reference Clock Divider registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 152: Prescaler Integer Register (PREINT - 0xE0024080). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 153: Prescaler Fraction Register (PREFRAC - 0xE0024084). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 154: Prescaler cases where the Integer Counter reload value is incremented. . . . . . . . . . . . . . . . . 210

Table 155: Watchdog Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 156: Watchdog Mode Register (WDMOD - 0xE0000000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 157: Watchdog Feed Register (WDFEED - 0xE0000008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 158: Watchdog Timer Value Register (WDTV - 0xE000000C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 159: Sectors in a device with 128K bytes of Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 160: ISP Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

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Table 161: ISP Unlock command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 162: ISP Set Baud Rate command description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 163: Correlation between possible ISP baudrates and external crystal frequency (in MHz). . . . . . . 226

Table 164: ISP Echo command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 165: ISP Write to RAM command description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 166: ISP Read Memory command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 167: ISP Prepare sector(s) for write operation command description. . . . . . . . . . . . . . . . . . . . . . . . 229

Table 168: ISP Copy RAM to Flash command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 169: ISP Go command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 170: ISP Erase sector command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 171: ISP Blank check sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 172: ISP Read Part ID command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 173: ISP Read Boot Code version command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 174: ISP Compare command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 175: ISP Return Codes Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 176: IAP Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 177: IAP Prepare sector(s) for write operation command description. . . . . . . . . . . . . . . . . . . . . . . . 236

Table 178: IAP Copy RAM to Flash command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 179: IAP Erase Sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 180: IAP Blank check sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 181: IAP Read Part ID command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 182: IAP Read Boot Code version command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 183: IAP Compare command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 184: IAP Status Codes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 185: EmbeddedICE Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Table 186: EmbeddedICE Logic Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 187: ETM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 188: ETM Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 189: ETM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 190: RealMonitor stack requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

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DOCUMENT REVISION HISTORY

2003 Dec 03:

• Prototype LPC2114/2124/2212/2214 User Manual created from the design specification. 2003 Dec 09:

• External Memory Controller and Pin Connect Block chapters updated. 2003 Dec 15/16:

• System Control Block chapter updated. 2003 Dec 18:

• A/D Converter Block chapter updated. 2004 Jan 07:

• PLL related material updated. 2004 Jan 26:

• System Control Block (Crystal Oscillator section - new frequencies added) updated. 2004 Feb 03:

• Introduction chapter (register list) updated. 2004 May 03:

• P0.16 description in "Pin Connect Block" chapter corrected from "Reserved" to "Capture 0.2 (TIMER0)".

• LPC2212 Flash size corrected in "Introduction" chapter corrected from 256 to 128 kB.

• Interrupt source #17 in "Vectored Interrupt Controller (VIC)" corrected from "EINT2" to "EINT3".

• Parallel ports 2 and 3 related registers added to "Introduction" and "GPIO" chapters

• Trigger levels deter mined by bits 7 and 6 in U0 FCR and U1FCR ("UART0" and "UART1" chapters) now showed in both decim al and hexadecimal notations

• References to DBGSEL pin removed from entire document (pin does not exist in this family of microcontrollers)

• Pin 20 in figure showing 64-pin package ("Pin Configuration" chapter) corrected from "1.3" to "1.31"

•V

replaced with V3A in "A/D Converter" chapter and V3A description updated in "Pin Configuration" chapter

ddA

• Warning on analog input levels added to "A/D Converter" chapter

• On-chip upper RAM boundary corrected from 0x4000 1FFF to 0x4000 3FFF in "LPC2114/2124/2212/2214 Memory Addressing" chapter

• Port pin tolerance, pull-up presence and voltage considerations added in "Pin Configuration" and "A/D Converter" chapter

• Baudrates in "Flash Memory System and Programming" corrected: 115200 and 230400 instead of 115000 and 230000

• Number of the on-ch ip Fla sh era se and wr it e c ycles a dde d i nto "In t rod uct ion " a nd "Fl as h Mem ory Sy ste m and Prog ram ming" chapters

• Pins capable of providing an External Interrupt functionality are acounted and listed in "System Control Block" chapter

• Access to ports with respect to GPIO configured pins clarified in "GPIO" and "Pin Connect Block" chapters

• Description of Code Read Protection feature added in "Flash Memory System and Programming" chapter

• IOPIN0 and IOPIN1 tyopografic errors corrected in "System Control Block" chapter

• PINSEL2 added to to "Introduction" chapter

13 May 03, 2004

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• T0IR, T0CCR, T0TCR, T1TCR, T0EMR and PCONP updated in "Introduction" chapter

• EXTMODE and EXTPOLAR registers added in "Introduction" chapter and updated in "System Control Block" chapter

• Power Control Usage Notes for reducing the total power added to "System Control Block" chapter

• PINSEL2 register as well as booting procedure updated in "Pin Connect Block" and "Watchdog" chapters

• references to the pclk in "External Memory Controller (EMC)" chapter corrected to the cclk

• LPC2212/2214 PINSEL2 table in "Pin Connect Block" chapter corrected

• A/D pin description in "A/D Converter" chapter rephrased

• Information on Spurious Interrupts added into "Vectored Interrupt Controller (VIC)" chapter

• Details on the checksum generation in case of Read Memory and Write to RAM ISP commands added in "Flash Memory System and Programming" chapter

14 May 03, 2004

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LPC2114/2124/2212/2214ARM-based Microc ontroller

1. INTRODUCTION

GENERAL DESCRIPTION

The LPC2114/2124/2212/2214 are based on a 16/32 bit ARM7TDMI-STM CPU with real-time emulation and embedded trace support, together with 128/256 kilobytes (kB) of embedded high speed flash memory. A 128-bit wide internal memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal performance penalty.

With their comapct 64 and 144 pin packages, low power con sumption, various 32 -bit timers, combination of 4-channel 10-bit ADC or 8-channel 10-bit ADC (64 and 144 pin packages respectively), and up to 9 external interrupt pins these microcontrollers are particularly suitable for industrial control, medical systems, access control and point-of-sale.

Number of availabl e GPIOs goes up to 46 in 64 pin package. In 144 pin packages number of available GPIOs tops 76 (with external memory i n us e) th rou gh 1 12 (s in gle - ch ip a ppl ic ati on). Being equipped wide ran ge o f se rial co mm unications interfaces , they are also very well suited for communication gateways, protocol converters and embedded soft modems as well as many other general-purpose applications.

FEATURES

• 16/32-bit ARM7TDMI-S microcontroller in a 64 or 144 pin package.

• 16 kB on-chip Static RAM

• 128/256 kB on-chip Flash Progra m Memory (at least 10,000 erat e/write cycles over the whole temperature range). 128-bit wi de interface/accelerator enables high speed 60 MHz operation.

• External 8, 16 or 32-bit bus (144 pin package only)

• In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot-loader software. Flash programming takes 1 ms per 512 byte line. Single sector or full chip erase takes 400 ms.

• EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service routines can continue to execute whilst the foreground task is debugged with the on-chip RealMonitor software.

• Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of instruction execution.

• Four/eight channel (64/144 pin package) 10-bit A/D converter with conversion time as low as 2.44 ms.

• Two 32-bit timers (with 4 capture and 4 compare channels), PWM unit (6 outputs), Real Time Clock and Watchdog.

• Multiple serial interfaces including two UARTs (16C550), Fast I

• 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked Loop.

• Vectored Interrupt Controller with configurable priorities and vector addresses.

• Up to forty-six (64 pin) and hundred-twelve (144 pin package) 5 V tolerant general purpose I/O pins. Up to 12 independent external interrupt pins available (EIN and CAP functions).

• On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.

• Two low power modes, Idle and Power-down.

• Processor wake-up from Power-down mode via external interrupt.

• Individual enable/disable of peripheral functions for power optimization.

• Dual power supply.

- CPU operating voltage range of 1.65V to 1.95V (1.8V +/- 8.3%).

C (400 kbits/s) and two SPIs™.

- I/O power supply range of 3.0V to 3.6V (3.3V +/- 10%).

Introduction 15 May 03, 2004

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APPLICATIONS

• Industrial control

• Medical systems

• Access control

• Point-of-sale

• Communication gateway

• Embedded soft modem

• general purpose applicatio ns

DEVICE INFORMATION

Table 1: LPC2114/2124/2212/2214 device information

Device No. of pins On-chip RAM

LPC2114 64 16 kB 128 kB 4 LPC2124 64 16 kB 256 kB 4 LPC2212 144 16 kB 128 kB 8 with external memory interface LPC2214 144 16 kB 256 kB 8 with external memory interface

On-chip

FLASH

No. of 10-bit

AD Channels

Note

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ARCHITECTURAL OVERVIEW

The LPC2114/2124/2212/2214 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a comp atible superset of ARM’s AMBA Advanced Peripheral Bu s) for connection to on-c hip peripheral functions. The LPC2114/2124/2212/2214 configures the ARM7TDMI-S processor in little-endian byte order.

AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kilobyte address space within the AHB address space. LPC2114/2124/2212/2214 peripheral functions (other than the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2 megaby te range o f addresses , beginni ng at the 3 .5 gigabyte a ddress po int. Each VPB peripheral is allocated a 16 kilobyte address space within the VPB address space.

The connection of on-chip pe ripherals to d evice pins i s controlled by a Pin Conne ction Block. This must be configured by software to fit specific application requirements for the use of peripheral functions and pins.

ARM7TDMI-S PROCESSOR

The ARM7TDMI-S is a general purpose 32-bit microproce ssor, which offers high perfo rmance and very low pow er consumption . The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are em plo ye d so tha t all parts of the processing and memory sy stems can operate continuou sly. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM instruction set.

• A 16-bit THUMB instruction se t.

The THUMB set’s 16-bit ins truc tio n l eng th al lo ws it to ap proa ch tw ic e th e de ns ity of s tan dard AR M c ode while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.

The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website.

ON-CHIP FLASH MEMORY SYSTEM

The LPC2114/2212 incorporate a 128 kB Flash memory system, while LPC2124/2214 incorporate a 256 kB Flash memory system. This mem ory ma y be u sed fo r both c ode an d data storage . Program ming of the Flash memo ry may be ac comp lishe d in several ways: over the serial built-in JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application Programmi ng (IAP) capabilities. Th e application pro gram, using the In Appli cation Programmin g (IAP) functions, may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware up grades, etc.

Introduction 17 May 03, 2004

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LPC2114/2124/2212/2214ARM-based Microc ontroller

ON-CHIP STATIC RAM

The LPC2114/2124/2 212/2214 provide a 16 kB static RAM m em ory th at ma y be used for code and/or data storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses.

The SRAM controller inc orpo rate s a wri te-b ac k bu ffer i n ord er to p rev ent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset.

Introduction 18 May 03, 2004

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BLOCK DIAGRAM

Internal SRAM

Controller

16 kB

SRAM

EINT3:0

8 x CAP0

8 x MAT

Ain3:0

Ain7:4

P0.30:0

P1.31:16, 1:0

P2.31:0 P3.31:0

2 2

ARM7 Local Bus

External

Interrupts

Capture / Compare

TIMER 0 & 1

Converter

General

Purpose I/O

Internal Flash

Controller

128/256 kB

FLASH

A/D

TMS

TRST

Test/Debug Interface

TDI

TCK

TDO

ARM7TDMI-S

AHB Bridge

AHB to VPB

Bridge

VPB (VLSI Peripheral Bus)

PLL

System

Module

Emulation Trace

(Advanced High-performance Bus)

VPB

Divider

Clock

AMBA AHB

External Memory

Controller

I2C Serial

Interface

SPI Serial

Interfaces 0 & 1

UART 0 & 1

Xtal1

System

Functions

Vectored Interrupt

Controller

AHB

Decoder

DSR1,CTS1,D

Xtal2

RESET

CS3:0* A23:0*

BLS3:0*

OE, WE*

D31:0*

SCL SDA

SCK0,1 MOSI0,1 MISO0,1 SSEL0,1

TxD0,1

RxD0,1 CD1, RI1

PWM6:1

PWM0

Real Time

Clock

* Shared with GPIO

When Test/Debug Interface is used, GPIO/other functions sharing these pins are not available

LPC2212/2214 only.

Watchdog

Timer

System Control

Figure 1: LPC2114/2124/2212/2214 Block Diagram

Introduction 19 May 03, 2004

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LPC2114/2124/2212/2214 REGISTERS

Accesses to registers in LPC21 14/2 12 4/22 12/2214 is restricted in the followi ng ways :

1) user must NOT attempt to access any register locations not defined.

2) Access to any defined register locations must be strictly for the functions for the registers.

3) Register bits labeled ’-’, ’0’ or ’1’ can ONLY be written and read as follows:

- ’-’ MUST be written with ’0’, but can return any value when read (even if i t was written with ’0’). It is a reserved bit and may be used in future derivatives.

- ’0’ MUST be written with ’0’, and will return a ’0’ when read.

- ’1’ MUST be written with ’1’, and will return a ’1’ when read.

The following table shows all registers available in LPC2114/2124/2212/2214 microcontroller sorted according to the address. Access to the specific one can be categorized as either read/write, read only or write only (R/W, RO and WO respectively). "Reset Value" field refe rs to the data stored in us ed/accessible bit s only. It does not inc lude reserved bits cont ent. Some registers

may contain undeterm ined data up on reset. In thi s case, reset value is ca tegorized as "un defined". Classificati on as "NA" is u sed in case reset value is not applicable. Some registers in RTC are not affected by the chip reset. Their reset value is marked as * and these registers must be initialized by software if the RTC is enabled.

Registers in LPC2114/2124/2212/2214 are 8, 16 or 32 bits wide. For 8 bit registers shown in Table 2, bit residing in the MSB (The Most Significant Bi t) colu mn co rrespon ds to th e bit 7 o f that reg ister, wh ile bit in the LS B (The Least Si gnific ant Bit) c olumn corresponds to the bit 0 of the same register.

If a register is 16/3 2 bit wide, the b it res iding in t he top left corne r of i ts d escrip tion, is th e bit corre spond ing to the bit 1 5/31 o f the register, while the bit in the bottom right corner corresponds to bit 0 of this register.

Examples: bit "EN A6" in PWMPCR register (add res s 0 xE001404C) represents the bit at position 14 in thi s reg ister; bits 15, 8, 7 and 0 in the same register are reserved. Bit "Stop on MR6" in PWMMCR register (0xE001 4014) corresponds to the bit at positi on 20; bits 31 to 21 of the same register are reserved.

Unused (reserved) bits are marked with "-" and represented as gray fields. Access to them is restricted as already described.

Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

0xE0000000

0xE0000004 WDTC

Name Description MSB LSB Access

MOD

Watchdog mode register

Watchdog timer constant register

- - - -

WD INTWDTOF

32 bit data R/W 0xFF

WDRE

SET

WDEN R/W 0

Reset Value

Watchdog

0xE0000008

FEED

feed sequence register

8 bit data (0xAA fallowed by 0x55) WO NA

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Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

0xE000000C WDTV

TIMER0

0xE0004000 T0IR

0xE0004004 T0TCR

0xE0004008 T0TC T0 Counter 32 bit data RW 0

0xE000400C T0PR

0xE0004010 T0PC

0xE0004014 T0MCR

Name Description MSB LSB Access

Watchdog timer value register

T0 Interrupt Register

T0 Control Register

T0 Prescale Register

T0 Prescale Counter

T0 Match Control Register

CR3

Int.

Reset

MR2

CR2

Int.

- - - - - -

4 reserved (-) bits

Int. on

MR2

CR1

Int.

Stop

MR1

32 bit data RO 0xFF

CR0

Int.

Reset

MR1

MR3

Int.

32 bit data R/W 0

Stop

MR3

Int. on

MR1

MR2

Int.

Reset

MR3 Stop

MR0

MR1

Int.

CTR

Reset

Int. on

MR3

Reset

MR0

Int.

CTR

Enable

Stop

MR2

Int. on

MR0

R/W 0

Reset Value

0xE0004018 T0MR0

0xE000401C T0MR1

0xE0004020 T0MR2

0xE0004024 T0MR3

0xE0004028 T0CCR

0xE000402C T0CR0

0xE0004030 T0CR1

0xE0004034 T0CR2

T0 Match Register 0

T0 Match Register 1

T0 Match Register 2

T0 Match Register 3

T0 Capture Control Register

T0 Capture Register 0

T0 Capture Register 1

T0 Capture Register 2

4 reserved (-) bits

Int. on

Cpt.2

falling

Int. on

Cpt.2 rising

Int. on

Cpt.1

32 bit data R/W 0

Int. on

Cpt.3

Int. on

Cpt.1

falling

Int. on

Cpt.1 rising

32 bit data RO 0

Int. on

Cpt.3

falling

Int. on

Cpt.0

Int. on

Cpt.3 rising

Int. on

Cpt.0

falling

Int. on

Cpt.2

R/W 0

Int. on

Cpt.0 rising

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Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

0xE000403C T0EMR

TIMER1

0xE0008000 T1IR

0xE0008004 T1TCR

0xE0008008 T1TC T1 Counter 32 bit data RW 0

0xE000800C T1PR

0xE0008010 T1PC

0xE0008014 T1MCR

Name Description MSB LSB Access

T0 External Match Register

T1 Interrupt Register

T1 Control Register

T1 Prescale Register

T1 Prescale Counter

T1 Match Control Register

4 reserved (-) bits

External Match

Control 1

CR3

Int.

Reset

MR2

CR2

- - - - - -

4 reserved (-) bits

Int. on

MR2

Int.

External Match

Control 0

CR1

Int.

Stop MR1

CR0

Reset

MR1

External Match

Control 3

Ext.

Mtch3.

MR3

Int.

32 bit data R/W 0

Int.

Stop

MR3

Int. on

MR1

Mtch2.

MR2

Reset

MR3 Stop

MR0

Ext.

Int.

External Match

Control 2

Ext.

Mtch.1

MR1

Int.

CTR

Reset

Int. on

MR3

Reset

MR0

Ext.

Mtch.0

MR0

Int.

CTR

Enable

Stop

MR2

Int. on

MR0

R/W 0

Reset Value

0xE0008018 T1MR0

0xE000801C T1MR1

0xE0008020 T1MR2

0xE0008024 T1MR3

0xE0008028 T1CCR

0xE000802C T1CR0

0xE0008030 T1CR1

0xE0008034 T1CR2

T1 Match Register 0

T1 Match Register 1

T1 Match Register 2

T1 Match Register 3

T1 Capture Control Register

T1 Capture Register 0

T1 Capture Register 1

T1 Capture Register 2

4 reserved (-) bits

Int. on

Cpt.2

falling

Int. on

Cpt.2 rising

Int. on

Cpt.1

32 bit data R/W 0

Int. on

Cpt.3

Int. on

Cpt.1

falling

Int. on

Cpt.1 rising

32 bit data RO 0

Int. on

Cpt.3

falling

Int. on

Cpt.0

Int. on

Cpt.3 rising

Int. on

Cpt.0

falling

Int. on

Cpt.2

R/W 0

Int. on

Cpt.0 rising

Introduction 22 May 03, 2004

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Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

Name Description MSB LSB Access

0xE0008038 T1CR3

0xE000803C T1EMR

UART0

U0RBR

(DLAB=0)

0xE000C000

U0THR

(DLAB=0)

U0DLL

(DLAB=1)

U0IER

0xE000C004

(DLAB=0)

T1 Capture Register 3

T1 External Match Register

U0 Receiver Buffer Register

U0 Transmit Holding Register

U0 Divisor Latch LSB

U0 Interrupt Enable Register

32 bit data RO 0

4 reserved (-) bits

External Match

Control 1

External Match

Control 0

External Match

Control 3

Ext.

Mtch.3

8 bit data RO

8 bit data WO NA

8 bit data R/W 0x01

00000

Ext.

Mtch2.

En. Rx

Line

Status

Int.

External Match

Control 2

Ext.

Mtch.1

Enable

THRE

Int.

Ext.

Mtch.0

En. Rx

Data

Av.Int.

Reset Value

R/W 0

un-

defined

R/W 0

U0DLM

(DLAB=1)

U0IIR

0xE000C008

U0FCR

0xE000C00C U0LCR

0xE000C014 U0LSR

0xE000C01C U0SCR

UART1

U0 Divisor Latch MSB

U0 Interrupt ID Register

U0 FIFO Control Register

U0 Line Control Register

U0 Line Status Register

U0 Scratch Pad Register

8 bit data R/W 0

FIFOs Enabled 0 0 IIR3 IIR2 IIR1 IIR0 RO 0x01

Rx Trigger

DLAB

Set

Break

- - -

Stick

Parity

Even

Parity

Select

Parity

Enable

U0 Tx

FIFO

Reset Nm. of

Stop

Bits

U0 Rx

FIFO

Reset

FIFO

Enable

Word Length

Select

WO 0

R/W 0

FIFO

TEMT THRE BI FE PE OE DR RO 0x60

Error

8 bit data R/W 0

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Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

Name Description MSB LSB Access

U1RBR

(DLAB=0)

0xE0010000

U1THR

(DLAB=0)

U1DLL

(DLAB=1)

U1IER

0xE0010004

(DLAB=0)

U1DLM

(DLAB=1)

U1IIR

0xE0010008

U1FCR

0xE001000C U1LCR

0xE0010010

MCR

0xE0010014 U1LSR

U1 Receiver Buffer Register

U1 Transmit Holding Register

U1 Divisor Latch LSB

U1 Interrupt Enable Register

U1 Divisor Latch MSB

U1 Interrupt ID Register

U1 FIFO Control Register

U1 Line Control Register

U1 Modem Control Register

U1 Line Status Register

Reset Value

8 bit data RO

un-

defined

8 bit data WO NA

8 bit data R/W 0x01

En.

0000

Mdem

Satus

En. Rx

Status

Int.

Line

Int.

Enable

THRE

Int.

En. Rx

Data

Av.Int.

R/W 0

8 bit data R/W 0

FIFOs Enabled 0 0 IIR3 IIR2 IIR1 IIR0 RO 0x01

Rx Trigger

DLAB

Set

Break

- - -

Stick

Parity

000

Even

Parity

Select

Loop Back

U0 Tx

FIFO

Reset

Parity

Enable

Nm. of

Stop

0 0 RTS DTR R/W 0

Bits

U0 Rx

FIFO

Reset

FIFO

Enable

Word Length

Select

WO 0

R/W 0

FIFO

TEMT THRE BI FE PE OE DR RO 0x60

Error

U1 Scratch Pad Register

U1 Modem Status Register

8 bit data R/W 0

DCD RI DSR CTS

Delta

DCD

Trailing

Edge

Delta

DSR

Delta

CTS

RO 0

0xE001001C U1SCR

0xE0010018

MSR

PWM

0xE0014000

0xE0014004

0xE0014008

PWM Interrupt Register

PWM Timer Control Register

PWM

TCR

PWMTCPWM Timer

Counter

- - - - -

- - - -

MR3

PWM

Enable

32 bit data RW 0

Int.

MR6

Int.

MR2

Int.

MR5

Int.

MR4

Int.

R/W 0

MR1

Int.

CTR

Reset

MR0

Int.

CTR

Enable

R/W 0

Introduction 24 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

0xE001400C

0xE0014010

0xE0014014

0xE0014018

0xE001401C

0xE0014020

Name Description MSB LSB Access

PWM Prescale Register

PWM Prescale Counter

PWM Match Control Register

PWM Match Register 0

PWM Match Register 1

PWM Match Register 2

11 reserved (-) bits

Int. on

MR5

Reset

MR2

Stop

MR4

Int. on

MR2

Reset

MR4 Stop

MR1

32 bit data R/W 0

Stop MR6

Int. on

MR4

Reset

MR1

Reset

MR6 Stop

MR3

Int. on

MR1

Int. on

MR6

Reset

MR3 Stop

MR0

Stop

MR5

Int. on

MR3

Reset

MR0

Reset

MR5 Stop

MR2

Int. on

MR0

R/W 0

32 bit data R/W 0

PWM

MCR

PWM

MR0

PWM

MR1

PWM

MR2

Reset Value

0xE0014024

0xE0014040

0xE0014044

0xE0014048

0xE001404C

0xE0014050

0xE001C000

PWM

MR3

PWM

MR4

PWM

MR5

PWM

MR6

PWM

PCR

PWM

LER

I2CONSETI

0xE001C004 I2STAT

0xE001C008 I2DAT

PWM Match Register 3

PWM Match Register 4

PWM Match Register 5

PWM Match Register 6

PWM Control Register

PWM Latch Enable Register

C Control

Set Register

C Status

I Register

C Data

I Register

32 bit data R/W 0

- ENA6 ENA5 ENA4 ENA3 ENA2 ENA1 R/W 0

- SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 -

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

R/W 0

-I2ENSTASTOSIAA - -R/W0

5 bit Status 0 0 0 RO 0xF8

8 bit data R/W 0

Introduction 25 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

0xE001C00C

0xE001C010

0xE001C014

0xE001C018

SPI0

0xE0020000

0xE0020004

0xE0020008

0xE002000C

0xE002001C

Name Description MSB LSB Access

C Slave

ADR

Address Register

7 bit data GC R/W 0

SCL Duty

SCLH

Cycle Register High

16 bit data R/W 0x04 Half Word SCL Duty

SCLL

Cycle Register Low

16 bit data R/W 0x04 Half Word

C Control

I Clear Register

SPI0 Control Register

SPI0 Status Register

SPI0 Data Register

SPI0 Clock Counter Register

SPI0 Interrupt Flag

- I2ENC STAC - SIC AAC - -WONA

SPIE LSBF MSTR CPOL CPHA

SPIF WCOL ROVR MODF ABRT

- - -R/W0

- - -RO0

8 bit data R/W 0

- - - - - - -

SPI

Int.

R/W 0

I2CONC

SPCR

SPSR

SPDR

SPCCR

SPINT

Reset Value

SPI1

0xE0030000

0xE0030004

0xE0030008

0xE003000C

0xE003001C

SPCR

SPSR

SPDR

SPCCR

SPINT

SPI1 Control Register

SPI1 Status Register

SPI1 Data Register

SPI1 Clock Counter Register

SPI1 Interrupt Flag

SPIE LSBF MSTR CPOL CPHA

SPIF WCOL ROVR MODF ABRT

8 bit data R/W 0

- - - - - - -

- - -R/W0

- - -RO0

SPI

Int.

R/W 0

RTC

Introduction 26 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

Name Description MSB LSB Access

0xE0024000 ILR

0xE0024004 CTC

0xE0024008 CCR

0xE002400C CIIR

0xE0024010 AMR

0xE0024014

0xE0024018

CTIME0

CTIME1

Interrupt Location Register

Clock Tick Counter

Clock Control Register

Counter Increment Interrupt Register

Alarm Mask Register

Consolidated Time Register 0

Consolidated Time Register 1

- - - - - -

15 bit data

- - - - CTTEST

RTC

ALF

CTC RST

RTC

CIF

-RO*

CLK

YEARIMMONIMDOYIMDOWIMDOMIMHOURIMMINIMSEC

AMR

YEAR

AMR

MON

AMR DOY

AMR

DOW

AMR

DOM

AMR

HOUR

AMR

MIN

AMR SEC

- - - - - 3 bit Day of Week

- - - 5 bit Hours

- - 6 bit Minutes

- - 6 bit Seconds

- - - 12 bit Year

- - - - 4 bit Month

- - - 5 bit Day of Month

Reset Value

R/W *

RO *

Consolidated

0xE002401C

CTIME2

Time Register 2

0xE0024020 SEC

0xE0024024 MIN

0xE0024028 HOUR

0xE002402C DOM

0xE0024030 DOW

0xE0024034 DOY

0xE0024038

MONTH

Seconds Register

Minutes Register

Hours Register

Day of Month Register

Day of Week Register

Day of Year Register

Months Register

0xE002403C YEAR Year Register

reserved (-) 20 bits 12 bit Day of Year RO *

- - 6 bit data R/W *

- - - 5 bit data R/W *

- - - - - 3 bit data R/W *

reserved (-) 7 bits 9 bit data R/W *

- - - - 4 bit data R/W *

reserved (-) 4 bits 12 bit data R/W *

Introduction 27 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

0xE0024060

0xE0024064

0xE0024068

0xE002406C

0xE0024070

0xE0024074

0xE0024078

0xE002407C

0xE0024080

0xE0024084

Name Description MSB LSB Access

SEC

MIN

HOUR

DOM

DOW

DOY

MON

YEAR

PRE

INT

PRE

FRAC

Alarm value for Seconds

Alarm value for Minutes

Alarm value for Hours

Alarm value for Day of Month

Alarm value for Day of Week

Alarm value for Day of Year

Alarm value for Months

Alarm value for Year

Prescale value, integer portion

Prescale value, fractional portion

- - 6 bit data R/W *

- - - 5 bit data R/W *

- - - - - 3 bit data R/W *

reserved (-) 7 bits 9 bit data R/W *

- - - - 4 bit data R/W *

reserved

(-) 4 bits

reserved

(-) 3 bits

- 15 bit data R/W 0

12 bit data R/W *

13 bit data R/W 0

Reset Value

GPIO PORT0

0xE0028000 IO0PIN

0xE0028004 IO0SET

0xE0028008 IO0DIR

0xE002800C IO0CLR

GPIO PORT1

0xE0028010 IO1PIN

0xE0028014 IO1SET

GPIO 0 Pin Value reg.

GPIO 0 Out. Set register

GPIO 0 Dir. control reg.

GPIO 0 Out. Clear register

GPIO 1 Pin Value reg.

GPIO 1 Out. Set register

32 bit data RO NA

32 bit data R/W 0

32 bit data WO 0

32 bit data RO NA

32 bit data R/W 0

Introduction 28 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

0xE0028018 IO1DIR

0xE002801C IO1CLR

GPIO PORT2

0xE0028020 IO2PIN

0xE0028024 IO2SET

0xE0028028 IO2DIR

0xE002802C IO2CLR

GPIO PORT3

0xE0028030 IO3PIN

0xE0028034 IO3SET

Name Description MSB LSB Access

GPIO 1 Dir. control reg.

GPIO 1 Out. Clear register

GPIO 2 Pin Value reg.

GPIO 2 Out. Set register

GPIO 2 Dir. control reg.

GPIO 2 Out. Clear register

GPIO 3 Pin Value reg.

GPIO 3 Out. Set register

Reset Value

32 bit data R/W 0

32 bit data WO 0

32 bit data RO NA

32 bit data R/W 0

32 bit data WO 0

32 bit data RO NA

32 bit data R/W 0

0xE0028038 IO3DIR

0xE002803C IO3CLR

Pin Connet Block

0xE002C000

0xE002C004

0xE002C014

ADC

SEL0

SEL1

SEL2

GPIO 3 Dir. control reg.

GPIO 3 Out. Clear register

Pin function select register 0

Pin function select register 1

Pin function select register 2

32 bit data R/W 0

32 bit data WO 0

32 bit data R/W 0

24-bit pin configuration data (144 package case)

Reserved bits (64 package case)

configuration

data

R/W 0

Introduction 29 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

Name Description MSB LSB Access

0xE0034000 ADCR ADC Control

0xE0034004 ADDR ADC Data

System Control Block

0xE01FC000

0xE01FC004

0xE01FC040

MAMCRMAM control

MAM

TIM

MEM MAP

MAM timing control

Memory mapping control

Reset Value

- EDGE START

TEST1:0 PDN -CLKS

BURST

RW 01

8 bit data 8 bit data

DONE

OVER

RUN

- CHN

RW x

10 bit data

- - - - - - 2 bit data R/W 0

----- 3 bit data R/W0x07

------2 bit dataR/W0

0xE01FC080

0xE01FC084

0xE01FC088

0xE01FC08C

PLL

CON

PLL

CFG

PLL

STAT

PLL

FEED

0xE01FC0C0 PCON

0xE01FC0C4 PCONP

0xE01FC100

0xE01FC140

VPB

DIV

EXT

INT

PLL control register

PLL configuration register

PLL status register

PLL feed register

Power control register

Power control for peripherals

VPB divider control

External interrupt flag register

------PLLCPLLER/W0

- 2bit data PSEL 5 bit data MSEL R/W 0

-----

PLOCK

PLLC PLLE

RO 0

- 2bit data PSEL 5 bit data MSEL

8 bit data WO NA

- - - - - - PD IDL R/W 0

reserved (-) 19 bits PCAD -

SPI1PCRTCPCSPI0

R/W 0x3BE

I2C

PWM0PCURT1PCURT0PCTIM1PCTIM0

- - - - - - 2 bit data R/W 0

- - - - EINT3 EINT2 EINT1 EINT0 R/W 0

Introduction 30 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

Name Description MSB LSB Access

External

0xE01FC144

EXT

WAKE

interrupt wakeup register

External interrupt mode register

0xE01FC148

EXT

MODE

External

0xE01FC14C

EXT

POLAR

interrupt polarity register

External memory Controller - EMC

0xFFE00000 BCFG0

0xFFE00004 BCFG1

Conf. Reg. for mem bank 0

Conf. Reg. for mem bank 1

EXT

- - - -

WAKE

EXT

- - - -

MODE

EXT

POLAR

AT MW (BOOT1:0)BM WP

EXT

WAKE

EXT

MODE

EXT

POLAR

EXT

WAKE

EXT

MODE

EXT

POLAR

ERR

EXT

WAKE0R/W 0

EXT

MODE0R/W 0

EXT

POLAR

BUS ERR

-------WST2 RBLE WST1

WST1 - IDCY

AT MW (0x2) BM WP

ERR

BUS ERR

-------WST2 RBLE WST1

WST1 - IDCY

Reset Value

R/W 0

R/W

0x0000

FBEF

0x2000

FBEF

0xFFE00008 BCFG2

Conf. Reg. for mem bank 2

AT MW (0x1) BM WP

ERR

--------

BUS ERR

R/W

0x1000

FBEF

WST2 RBLE WST1

WST1 - IDCY

0xFFE0000C BCFG3

Conf. Reg. for mem bank 3

AT MW (0x0) BM WP

ERR

--------

BUS ERR

R/W

0x0000

FBEF

WST2 RBLE WST1

WST1 - IDCY

Vectored Interrupt Controller - VIC

0xFFFFF000

0xFFFFF004

VICIRQ

Status

VICFIQ

Status

IRQ Status Register

FIQ Status Register

32-bit data RO 0

Introduction 31 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 2: LPC2114/2124/2212/2214 Registers

Address

Offset

0xFFFFF008

0xFFFFF00C

0xFFFFF010

0xFFFFF014

0xFFFFF018

0xFFFFF01C

0xFFFFF020

0xFFFFF030

0xFFFFF034

0xFFFFF100

Name Description MSB LSB Access

VIC

RawIntr

VICInt Select

VICInt

Enable

VICInt

EnClear

VICSoft

VICSoftI

ntClear

Protection

VIC

Addr

VICDef

ectAddr

VIC

Addr0

Int

VIC

Vect

Raw Interrupt Status Reg.

Interrupt Select Reg.

Interrupt Enable Reg.

Int. Enable Clear Reg.

Software Interrupt Reg.

Software Int. Clear Reg.

Protection Enable Reg.

Vector Address Reg.

Default Vec. Addr.Reg.

Vector adr. 0 reg.

32-bit data RO 0

32-bit data R/W 0

32-bit data WO 0

32-bit data R/W 0

32-bit data W 0

32-bit data R/W 0

Reset Value

0xFFFFF104

0xFFFFF13C

0xFFFFF200

0xFFFFF204

0xFFFFF23C

Vect

VIC

Addr1

Vect

VIC

Addr15

Vect

VIC

Cntl0

Vect

VIC

Cntl1

Vect

VIC

Cntl15

Vector adr. 1 reg.

Vector adr. 15 reg.

Vect. Control 0 Reg.

Vect. Control 1 Reg.

Vect. Control 15 Reg.

- -

1-bit data

32-bit data R/W 0

...

32-bit data R/W 0

5-bit data R/W 0

...

5-bit data R/W 0

Introduction 32 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

2. LPC2114/2124/2212/2214 MEMORY ADDRESSING

MEMORY MAPS

The LPC2114/2124/ 2212/2214 incorpora tes se veral dist inct memory regions, shown i n the follo wing figures . Figur e 2 shows th e overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address re-mapping, which is described later in this section.

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

AHB Peripherals

VPB Peripherals

Reserved for

External Memory

Boot Block

(re-mapped from On-Chip Flash memory)

Reserved for

On-Chip Memory

0xFFFF FFFF 0xF000 0000

0xE000 0000

0xC000 0000

0x8000 0000

0x4000 3FFF 0x4000 0000

0x0004 0000 0x0003 FFFF

0x0002 0000 0x0001 FFFF

0x0000 0000

1.0 GB

0.0 GB

16 kB On-Chip Static RAM

256 kB On-Chip Non-Volatile Memory

(LPC2212/2214)

128 kB On-Chip Non-Volatile Memory

(LPC2114/2124)

Figure 2: System Memory Map

LPC2114/2124/2212/2214 Memory Addressing 33 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Notes:

- AHB section is 128 x 16 kB blocks (totaling 2 MB).

- VPB section is 128 x 16 kB blocks (totaling 2 MB).

4.0 GB

4.0 GB - 2 MB

3.75 GB

AHB Peripherals

0xFFFF FFFF 0xFFE0 0000

0xFFDF FFFF

Reserved

0xF000 0000 0xEFFF FFFF

Reserved

3.5 GB + 2 MB VPB Peripherals

3.5 GB

Figure 3: Peripheral Memory Map

Figures 3 through 5 show different views of the peripheral address space. Both the AHB and VPB peripheral areas are 2 megabyte spaces whic h are divided up into 128 periph erals. Each peripheral space is 16 kilobytes in size . This allows simplifyi ng the address decod ing for ea ch perip heral. All periphera l registe r addresses are wor d aligned (to 32-bit b oundar ies) regard less of their size. This eliminate s th e nee d for byte lane mapping hardwa re tha t woul d be requi red to all ow by te (8- bit) o r hal f-w ord (16bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.

0xE020 0000 0xE01F FFFF

0xE000 0000

LPC2114/2124/2212/2214 Memory Addressing 34 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Vectored Interrupt Controller

(AHB peripheral #126)

(AHB peripheral #125)

(AHB peripheral #124)

(AHB peripheral #3)

(AHB peripheral #2)

0xFFFF F000 (4G - 4K)

0xFFFF C000

0xFFFF 8000

0xFFFF 4000

0xFFFF 0000

0xFFE1 000 0

0xFFE0 C000

(AHB peripheral #1)

(AHB peripheral #0)

Figure 4: AHB Peripheral Map

0xFFE0 800 0

0xFFE0 400 0

0xFFE0 000 0

LPC2114/2124/2212/2214 Memory Addressing 35 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

System Control Block

(VPB peripheral #127)

(VPB peripherals #14-126)

not used

10 bit A/D

(VPB peripheral #13)

SPI1

(VPB peripheral #12)

Pin Connect Block

(VPB peripheral #11)

GPIO

(VPB peripheral #10)

RTC

(VPB peripheral #9)

SPI0

(VPB peripheral #8)

(VPB peripheral #7)

not used

(VPB peripheral #6)

PWM0

(VPB peripheral #5)

UART1

(VPB peripheral #4)

UART0

(VPB peripheral #3)

TIMER1

(VPB peripheral #2)

TIMER0

(VPB peripheral #1)

Watchdog Timer

(VPB peripheral #0)

0xE01F FFFF 0xE01F C000

0xE003 8000

0xE003 4000

0xE003 0000

0xE002 C000

0xE002 8000

0xE002 4000

0xE002 0000

0xE001 C000

0xE001 8000

0xE001 4000

0xE001 0000

0xE000 C000

0xE000 8000

0xE000 4000

0xE000 0000

Figure 5: VPB Peripheral Map

LPC2114/2124/2212/2214 Memory Addressing 36 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

LPC2114/2124/2212/2214 MEMORY RE-MAPPING AND BOOT BLOCK

Memory Map Concepts and Operating Modes

The basic concept on the LPC2114 /2124/221 2/2214 is that eac h memory are a has a "natura l" loca tion in the me mory map. Thi s is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.

Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000 through 0x0000 001C, as shown in Table 3 below), a sma ll portion of the Boot Blo ck and SRAM spa ces need to be re-ma pped in order to al low alternati ve uses of interrupts in the different operating modes described in Table 4. Re-mapping of the interrupts is accomplished via the Memory Mapping Control feature described in the System Control Block section.

Table 3: ARM Exception Vector Locations

Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort (instruction fetch memory fault) 0x0000 0010 Data Abort (data access memory fault) 0x0000 0014 Reserved * 0x0000 0018 IRQ 0x0000 001C FIQ

*: Identified as reserved in ARM do cumen tation , this loca tion is us ed by the Boot Loader as the Valid User Progra m key. Thi s is descibed in detail in Flash Memory System and Programming on page 217.

Table 4: LPC2114/2124/2212/2214 Memory Mapping Modes

Mode Activation Usage

Boot Loader

mode

User Flash

mode

User RAM

mode

User External

mode

Hardware activation

by any Reset

Software activation

by Boot code

Software activation

by User program

Activated by

BOOT1:0 pins not

11 at Reset

The Boot Loader always mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process.

Activated by Boot Loader whe n a valid User Program Si gnature is recogni zed in memory and Boot Loader operation is not forced. Interrupt vectors are not re-mapped and are found in the bottom of the Flash memory.

Activated by a User Program as de sir ed. In terru pt ve ctors are re-mapped to the bottom of the Static RAM.

Activated by the Boot Loader when either or both BOOT pins are low at the end of RESET low. Interrupt vectors are re-mapped from the bottom of the external memory map.

Note: This mode is available in LPC2212/2214 only!

executes after any reset. The Boot Block interrupt vectors are

LPC2114/2124/2212/2214 Memory Addressing 37 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Memory Re-Mapping

In order to allo w for com patibili ty with future der ivatives , the en tire Boot Block i s mapped to the top of t he on -chip mem ory space. In this manner, the use of larger or smaller flash modules will not require changing the location of the Boot Block (which would require changing the Boot Loader code itself ) or changing the mappin g of the Boot Block interru pt vectors. Memo ry spaces other than the interrupt vectors remain in fixed locations. Figure 6 shows the on-chip memory mapping in the modes defined above.

The portion of memory that is re-mapped to allow interrupt processing in different modes includes the interrupt vector area (32 bytes) and an additional 32 bytes, for a total of 64 bytes. The re-mapped code locations ove rlay addresses 0x0000 0000 throu gh 0x0000 003F. A typical u ser progra m in th e Flash memory c an place the entir e FIQ h andler at addre ss 0x0000 001C w ithout a ny need to consider memory boundaries. The vector contained in the SRAM, external memory, and Boot Block must contain branches to the actual interrupt handlers, or to other instructions that accomplish the branch to the interrupt handlers.

There are three reasons this configuration was chosen:

1. To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the remapping into account.

2. Minimize the need to for th e SRAM and Bo ot Blo ck vec to rs to deal with arbitrary boun dari es in th e mi ddl e of cod e sp ac e.

3. To provide space to store constants for jumping beyond the range of single word branch instructions.

Re-mapped memory are as, includin g the Boot Block and interr upt vectors, con tinue to appear in their original loc ation in additi on to the re-mapped address.

Details on re-mapping and examples can be found in System Control Block on page 49.

LPC2114/2124/2212/2214 Memory Addressing 38 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

0x8000 0000

2.0 GB

2.0 GB - 8K

8K byte Boot Block

(re-mapped from top of Flash memory)

(Boot Block interrupt vectors)

Reserved for

On-Chip Memory

0x7FFF FFFF

1.0 GB

16 kB On-Chip SRAM

(SRAM interrupt vectors)

Reserved for

On-Chip Memory

(8k byte Boot Block re-Mapped to higher address range)

128K byte Flash Memory

0x4000 4000 0x4000 3FFF

0x4000 0000 0x3FFF FFFF

0x0002 0000 0x0001 FFFF

0.0 GB

Note: memory regions are not drawn to scale.

Active interrupt vectors (from Flash, SRAM, or Boot Block)

0x0000 0000

Figure 6: Map of lower memory is showing re-mapped and re-mappable areas (128 kB Flash).

LPC2114/2124/2212/2214 Memory Addressing 39 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

PREFETCH ABORT AND DATA ABORT EXCEPTIONS

The LPC2114/2124/2212 /2214 generates the ap propriate bus cycl e abort exception if an ac cess is attempted for an address that is in a reserved or unassigned address region. The regions are:

• Areas of the memory map that are not implemented for a specific ARM derivative. For the LPC2114/2124/2212/2214, this is:

- Address space between On-Chip Non-Volatile Memory and On-Chip SRAM, labelled "Reserved for On-Chip Memory" in Figure 2 and Figure 6 . For 128 kB Fla sh devic e, this is me mory a ddress range from 0x 0002 0 000 to 0 x3FFF FFFF, while for 256 kB Flash device this range is from 0x0004 0000 to 0x3FFF FFFF.

- Address space between On-Chip Static RAM and External Memory. Labelled "Reserved for On-Chip Memory" in Figure 2. This is an address range from 0x4000 3FFF to 0x7FFF DFFF.

- External Memory other than that provided by the EMC in the 144-pin package.

- Reserved regions of the AHB and VPB spaces. See Figure 3.

• Unassigned AHB peripheral spaces. See Figure 4.

• Unassigned VPB peripheral spaces. See Figure 5. For these areas, both atte mpted data acc ess and instruc tion fetch gen erate an excep tion. In additi on, a Prefetch Abort exceptio n

is generated for any instruction fetch that maps to an AHB or VPB peripheral address. Within the addres s spa ce of an ex is tin g VPB peri phe ral, a data abort exce pti on is not generated in response to an access to an

undefined address. Address decoding within each peri pheral is limited to that neede d to distinguish defined reg ist ers within th e peripheral itself. Fo r example, an access to address 0xE0 00D000 (an un defined add ress wit hin the UART0 space) may result in an access to the register defined at address 0xE000C000. Details of such address aliasing within a peripheral space are not defined in the LPC2114/2124/2212/2214 documentation and are not a supported feature.

Note that the ARM core stores the Prefetch Abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This prevents acciden tal abort s that co uld be ca used by prefetc hes tha t occur w hen co de is exec uted ve ry ne ar a memo ry boun dary.

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3. EXTERNAL MEMORY CONTROLLER (EMC)

This module is available in LPC2212 and LPC2214 only.

FEATURES

• Supports static memory-mapped devices including RAM, ROM, flash, burst ROM, and some external I/O devices.

• Asynchronous page mode read operation in non-clocked memory subsystems

• Asynchronous burst mode read access to burst mode ROM devices

• Independent configuration for up to four banks, each up to 16M Bytes

• Programmable bus turnaround (idle) cycles (1 to 16)

• Programmable read and write WAIT states (up to 32), for static RAM devices

• Programmable initial and subsequent burst read WAIT state, for burst ROM devices

• Programmable write protection

• Programmable burst mode operation

• Programmable external data width, 8, 16, or 32 bits

• Programmable read byte lane enable control

DESCRIPTION

The external Static Memory Controller is an AMBA AHB slave module which provides an interface between an AMBA AHB system bus and externa l (off-chip) m emory devic es. It provide s support fo r up to four indep endently c onfigurabl e memory b anks simultaneously. Ea ch memory bank is capable of s upporting SRAM, R OM, Flash EPROM, Burst ROM memory, o r some external I/O devices

Each memory bank may be 8, 16, or 32 bits wide. This module is availa ble in LPC2212 and LPC221 4 only. Since this 144 pin package pins out address lines A[23:0 ], the decoding

among the four banks uses address bits A[25:24]. The native location of the four banks is at the start of the External Memory area identified in Figure 2 on page 33, but Bank 0 can b e used for ini tial booti ng under c ontrol of t he stat e of the BOOT [1:0] pi ns.

Bank Address Range Configuration Register

0 8000 0000 - 80FF FFFF BCFG0 1 8100 0000 - 81FF FFFF BCFG1 2 8200 0000 - 82FF FFFF BCFG2 3 8300 0000 - 83FF FFFF BCFG3

Table 5: Address Ranges of External Memory Banks (LPC2212/2214 only)

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PIN DESCRIPTION

Pin Name Type Pin Description

D[31:0]

A[23:0] Output External memory address lines.

OE Output Low-active Output Enable signal.

BLS[3:0] Output Low-active Byte Lane Select signals.

WE Output Low-active Write Enable signal.

CS[3:0] Output Low-active Chip Select signals.

Table 6: External Memory Controller Pin Description

Input/

Output

External memory data lines.

The external memory controller contains 4 registers as shown in Table 7.

Name Description Access

BCFG0 Configuration register for memory bank 0 Read/Write 0x0000 FBEF 0xFFE00000 BCFG1 Configuration register for memory bank 1 Read/Write 0x2000 FBEF 0xFFE00004 BCFG2 Configuration register for memory bank 2 Read/Write 0x1000 FBEF 0xFFE00008 BCFG3 Configuration register for memory bank 3 Read/Write 0x0000 FBEF 0xFFE0000C

Table 7: External Memory Controller Register Map

Each register selects the following options for its memory bank:

• The number of idle clock cycles inserted between between read and write accesses in this bank, and between an access in another bank and an access in this bank, to avoid bus contention between devices (1 to 17 clocks)

• the length of read accesses, except for subsequent reads from a burst ROM (3 to 35 clocks)

• the length of write accesses (3 to 19 clocks)

• whether the bank is write-protected

• whether the bank is 8, 16, or 32 bits wide

Reset Value

(see Table 9)

Address

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Bank Configuration Registers 0 - 3 (BCFG0-3 - 0xFFE00000-0C).

BCFG0-3 Name Function Reset Value

This field controls the minimum number of “idle” CCLK cycles that the EMC maintains

3:0 IDCY

between read and write accesse s in this bank, and betw een an access in anothe r bank and an access in this bank, to avoid bus contention between devices. The number of idle CCLK cycles between such accesses is the value in this field plus 1.

1111

4 Reserved

9:5 WST1

10 RBLE

15:11 WST2

16:23 Reserved

24 BUSERR

25 WPERR

26 WP A 1 in this bit write-protects the bank. 0

Reserved, user software should not wri te ones to res erved bits. The va lue read from a reserved bit is not defined.

This field controls the length of read accesses, except for subsequent reads from a burst ROM. The length of such rea d accesses , in CCLK cycles, is the value in this fiel d plus 3.

This bit should be 0 for banks composed of byte-wide or non-b yte -par titi one d de vices, so that the EMC d rives the BLS3:0 lin es Hig h during read access es. Thi s bit sh ould be 1 for banks compos ed of 16 -bi t and 32 -bit w ide de vices that i nclud e byte selec t inpu ts, so that the EMC drives the BLS3:0 lines Low during read accesses.

For SRAM banks, this field controls the length of write accesses, which consist of:

• one CCLK cycle of address setup with CS, BLS, and WE high,

• (this value plus 1) CCLK cycles with address valid and CS, BLS, and WE low, and

• one CCLK cycle with address valid, CS low, BLS and WE high. For burst ROM banks, thi s field co ntro ls the leng th of subs equent accesse s, whic h are

(this value plus 1) CCLK cycles long. Reserved, user software should not wri te ones to res erved bits. The va lue read from a

reserved bit is not defined. The only known case in which this bit is s et is if th e EM C detects an AMBA req ues t for

more than 32 bits of data. The ARM7TDMI-S will not make such a request. This bit is set if software attem pts to wr ite to a bank that ha s the W P bit 1. Write a 1 to

this bit to clear it.

11111

27 BM A 1 in this bit identifies a burst-ROM bank. 0

29:28 MW

31:30 AT Always write 00 to this field. 00

Table 8: Bank Configuration Registers 0-3 (BCFG0-3 - 0xFFE00000-0C)

The table below shows the state of BCFG0[29:28] after the Boot Loader has run. The hardware reset state of these bits is 10.

Bank BOOT[1:0] during Reset BCFG[29:28] Reset value Memory Width

0 LL 00 8 bits 0LH 01 16 bits 0HL 10 32 bits 1XX 10 32 bits 2XX 01 16 bits 3XX 00 8 bits

Table 9: Default memory widths at Reset

This field controls the width of the data bus for this bank: 00=8 bit, 01=16 bit, 10=32 bit, 11=reserved

see Table 9

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EXTERNAL MEMORY INTERFACE

External memory interface depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding BCFG register). Furthermore, choice of the memory chip(s) will require an adequate setup of RBLE bit in BCFG register, too. RBLE = 0 in case of 8-bit based external memories, while memory chips capable of accepting 16 or 32 bit wide data will work with RBLE = 1.

If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used as non-address lines. Memory bank configured to 16 bits wide will not require A0, while 8 bit wide memory bank will require address lines down to A0. Configuring A1 and/or A0 line(s) to provide address or non-address function is acomplished using bits 23 and 24 in Pin Function Select Register 2 (PINSEL2 register).

Symbol "a_b" in follo wing figures refers to the highest orde r address line in the d ata bus. Symbol " a_m" refers to the high est order address line of the memory chip used in the external memory interface

CS OE

BLS[3]

CE OE WE

BLS[2]

CE OE WE

BLS[1]

CE OE WE

BLS[0]

CE OE WE

D[31:24]

A[a_b:2]

CS OE

BLS[3] BLS[2]

D[31:16]

A[a_b:2]

b) 32 bit wide memory bank interfac ed t o 16 bit memory chips

IO[7:0] A[a_m:0]

CE OE WE UB LB

IO[15:0] A[a_m:0]

D[23:16]

a) 32 bit wide memory bank interfac ed to 8 bit memory chips

BLS[1] BLS[0]

D[15:0]

IO[7:0] A[a_m:0]

CE OE WE UB LB

IO[15:0] A[a_m:0]

D[15:8]

IO[7:0] A[a_m:0]

A[a_b:0]

c) 32 bit wide memory bank interf aced

D[7:0]

CS OE

BLS[3] BLS[2] BLS[1] BLS[0]

D[31:0]

to 32 bit memory chip

CE OE WE B3 B2 B1 B0

IO[31:0] A[a_m:0]

IO[7:0] A[a_m:0]

Figure 7: 32 Bit Bank External Memory Interfaces

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BLS[1]

CE OE WE

BLS[0]

CE OE WE

BLS[1] BLS[0]

CE OE WE UB LB

D[15:8]

IO[7:0] A[a_m:0]

A[a_b:1]

a) 16 bit wide memory bank interfaced

to 8 bit memory chips

Figure 8: 16 Bit Bank External Memory Interfaces

D[7:0]

IO[7:0] A[a_m:0]

A[a_b:1]

a) 16 bit wide memory bank interfac ed

to 16 bit memory chips

CS OE

CE OE

BLS[0]

D[7:0]

WE IO[7:0]

A[a_m:0]

A[a_b:0]

Figure 9: 8 Bit Bank External Memory Interface

D[15:0]

IO[15:0] A[a_m:0]

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TYPICAL BUS SEQUENCES

Following figures show typical external read and write access cycles. XCLK is the clock signal avalable on P3.23. While not necessary used by external memory, In these examples it is used to provide the time reference (XCLK and CCLK were set to have the same frequency).

1 wait state (WST1=0)

XCLK

CS OE

WE/BLS

Addr Data

XCLK

CS OE

WE/BLS

Addr Data

valid address

change valid data

2 wait states (WST1=1)

valid address

change valid data

Figure 10: External memory read access (WST1=0 and WST1=1 examples)

WST2=0

XCLK

CS OE

WE/BLS

Addr Data

XCLK

CS OE

WE/BLS

Addr Data

valid address

valid data

WST2=1

valid address

valid data

Figure 11: External memory write access (WST2=0 and WST2=1 examples)

Figure 10 and Figure 11 are showing typ ical read an d write acces ses to exte rnal memo ry. Howeve r, variation s can be noti ced in some particular cases.

For example, when the first read access to the memory bank that has just been selected is performed, CS and OE lines may become low one XCLK cycle earlier than it is shown in Figure 10.

Likewise, in a sequenc e of several consec utive write accesse s to SRAM, the last write acce ss will look like thos e shown in Figure

11. On the other ha nd, lea ding write cycles i n th at ca se w ill h ave data valid one cycle longer. Also, is lo ated write access will be

identical to the one in Figure 11.

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EXTERNAL MEMORY SELECTION

Based on the des cription of the EMC opera tion and ex ternal memo ry in genera l (appropriate read and write access tim es tAA and t

respecitely), the fo llowing table ca n be construc ted and u sed for ex ternal me mory sel ection. t

WRITE

XCLK cycle (see Fi gure 10 and Fi gure 11 ). f

is the maximum c cl k f r equ enc y ac hie va ble in the s ys tem w ith s ele cte d e xte rnal

max

memory.

Table 10: External memory and system requirements

is the period of a single

CYC

Access

cycle

Standard

Read

Standard

Write

Max. frequency

2 + WST1

<= ———————

max

RAM

+ 20ns

1 + WST2

<= ———————

max

RAM

+ 5ns

WST setting

(WST>=0; round up to integer)

WST1>=

WST2>=

—————————

+ 20ns

RAM

—————— - 2

CYC

- t

WRITE

CYC

+ 5ns

Required memory access time

RAM

WRITE

<= t

*(2+WST1) - 20ns

CYC

<= t

*(1+WST2) - 5ns

CYC

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4. SYSTEM CONTROL BLOCK

SUMMARY OF SYSTEM CONTROL BLOCK FUNCTIONS

The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include:

• Crystal Oscillator.

• External Interrupt Inputs.

• Memory Mapping Control.

• PLL.

• Power Control.

• Reset.

• VPB Divider.

• Wakeup Timer.

Each type of fu nction has it s own reg ister(s) if any are required and unnee ded bits a re defined as reserved i n order to allow future expansion. Unrelated f unctions never share the same register addresses.

PIN DESCRIPTION

Table 11 shows pins that are associated with System Control block functions.

Table 11: Pin summary

Pin name Pin direction Pin Description

X1 Input Crystal Oscillator Input- Input to the oscillator and internal clock generator circuits. X2 Output Crystal Oscillator Output- Output from the oscillator amplifier.

External Interrupt Input 0- An ac tive low general p urpose interru pt input. This pin may be used to wake up the processor from Idle or Po wer down modes.

EINT0 Input

EINT1 Input

EINT2 Input

Pins P0.1 and P0.16 can be selected to perform EINT0 function. LOW level on this pin immediately after reset is considered as an external hardware

request to start the ISP command ha ndler. More de tails on ISP and Flash memory can be found in "Flash Memory System and Programming" chapter.

External Interrupt Input 1- See the EINT0 description above. Pins P0.3 and P0.14 can be selected to perform EINT1 function.

External Interrupt Input 2- See the EINT0 description above. Pins P0.7 and P0.15 can be selected to perform EINT2 function.

External Interrupt Input 3- See the EINT0 description above.

EINT3 Input

Pins P0.9, P0.20 and P0.30 can be selected to perform EINT3 function.

ESET Input

External Reset input- A low on this pin resets the chi p, causing I/O ports and periphe rals to take on their default states, and the processor to begin execution at address 0.

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All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

Table 12: Summary of System Control Registers

Name Description Access

External Interrupts

EXTINT External Interrupt Flag Register. R/W 0 0xE01FC140 EXTWAKE External Interrupt Wakeup Register. R/W 0 0xE01FC144 EXTMODE External Interrupt Mode Register. R/W 0 0xE01FC148

EXTPOLAR External Interrupt Polarity Register. R/W 0 0xE01FC14C

Memory Mapping Control

MEMMAP Memory Mapping Control. R/W 0 0xE01FC040

Phase Locked Loop

PLLCON PLL Control Register. R/W 0 0xE01FC080

PLLCFG PLL Configuration Register. R/W 0 0xE01FC084 PLLSTAT PLL Status Register. RO 0 0xE01FC088 PLLFEED PLL Feed Register. WO NA 0xE01FC08C

Power Control

PCON P ower Control Register. R/W 0 0xE 01FC0C0

PCONP Power Control for Peripherals. R/W 0x3BE 0xE01FC0C4

VPB Divider

VPBDIV VPB Divider Control. R/W 0 0xE01FC100

Reset

Value*

Address

*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.

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CRYSTAL OSCILLATOR

While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz can be used by LPC2114/2124/2212/ 2214 if supplied to its input XTAL1 pin, this microcontroller’s onboard oscillator circuit supports external crystals in the range of 1 MHz to 30 MHz only. If on-chip PLL sy stem or boot-loader is used, input clock frequen cy is limited to exclusi ve range of 10 MHz to 25 MHz.

The oscillator output freq uen cy is ca lle d F equations, etc. else where in t his d ocum ent. F

and the ARM processor clock frequenc y is referred to as cclk for purposes of rate

osc

and cclk are the same val ue unless the PLL is running and con nected. Refer to

osc

the PLL description in this chapter for details and frequency limitations. Onboard oscillator in LPC2114/2124/2212/2214 can operate in one of two modes: slave mode and oscillation mode. In slave mode the input cloc k si gna l sho uld be cou pl ed by mean s of a ca pac itor of 100 pF (Cc in Figure 12, drawin g a), wi th an

amplitude of at leas t 200mVrms. X2 pin in this co nfig ura tion can be left not connected. If slave mode is se lec ted , F

signal of

osc

50-50 duty cycle can range from 1 MHz to 50 MHz. External components and models use d in oscilla tion mode are shown in Figure 12, drawings b and c, and in Table 13 . Since the

feedback resistance is integrated on chip, only a crystal and the capacitances C case of fundamental mod e oscillatio n (the fundamenta l frequency is repr esented by L, C drawing c, represents the par all el pa ck age cap aci tance and should not be larger than 7 pF. Para me ters F

and CX2 need to be connected externally in

and RS). Capacitance Cp in Figur e 12,

, CL, RS and CP are

supplied by the crystal manufa ctu rer. Choosing an oscillation mode as an on-board oscillator mode of operation limits F

LPC2114/2124 LPC2212/2214

X1 X2

Clock

LPC2114/2124 LPC2212/2214

X1 X2

Xtal

clock selection to 1 MHz to 30 MHz.

osc

<=>

C R

a) b) c)

Figure 12: Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation,

c) external crystal model used for C

Table 13: Recommended values for C

Fundamental Oscillation

Frequency F

Crystal Load

Capacitance C

in oscillation mode (crystal and external components parameters)

X1/X2

Max. Crystal Series

Resistence R

X1/X2

evaluation

External Load

Capacitors C

, C

10 pF n.a. n.a.

1 - 5 MHz

20 pF n.a. n.a. 30 pF < 300 : 58 pF, 58 pF

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Table 13: Recommended values for C

Fundamental Oscillation

Frequency F

Crystal Load

Capacitance C

5 - 10 MHz

10 - 15 MHz

15 - 20 MHz

20 - 25 MHz

25 - 30 MHz

in oscillation mode (crystal and external components parameters)

X1/X2

Max. Crystal Series

Resistence R

External Load

Capacitors C

, C

10 pF < 300 : 18 pF, 18 pF 20 pF < 300 : 38 pF, 38 pF 30 pF < 300 : 58 pF, 58 pF 10 pF < 300 : 18 pF, 18 pF 20 pF < 220 : 38 pF, 38 pF 30 pF < 140 : 58 pF, 58 pF 10 pF < 220 : 18 pF, 18 pF 20 pF < 140 : 38 pF, 38 pF 30 pF < 80 : 58 pF, 58 pF 10 pF < 160 : 18 pF, 18 pF 20 pF < 90 : 38 pF, 38 pF 30 pF < 50 : 58 pF, 58 pF 10 pF <130 : 18 pF, 18 pF 20 pF <50 : 38 pF, 38 pF 30 pF n.a. n.a.

selection

OSC

on-chip PLL used

in application?

False

ISP used for initial

code download?

False

external crystal

oscillator used?

False

min f

= 1 MHz

OSC

max f

= 50 MHz

OSC

True

min f

max f

= 1 MHz

OSC

= 30 MHz

OSC

min f

max f

= 10 MHz

OSC

= 25 MHz

OSC

True

(Figure 12, mode a and/or b) (Figure 12, mode a) (Figure 12, mode b)

Figure 13: F

selection algorithm

OSC

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EXTERNAL INTERRUPT INPUTS

The LPC2114/2124/2212/2214 includes four External Interrupt Inputs as selectable pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from the Power Down mode.

The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags, and the EXTWAKEUP register contains bits that enable individual external interrupts to wake up the LPC2114/2124/2212/2214 from Power Down mode. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.

Table 14: External Interrupt Registers

Address Name Description Access

0xE01FC140 EXTINT

0xE01FC144 EXTWAKE

0xE01FC148 EXTMODE

0xE01FC14C EXTPOLAR

The External Interrupt Flag Register contains interrupt flags for EINT0, EINT1, and EINT2. See Table 15.

The External Interrupt Wakeup Register contains three enable bits that control whether each external inte rrup t will ca use the proc es so r to w ake u p fro m Pow e r Down mode. See Table 16.

The External Interrupt Mode R egister co ntrols whethe r each pin is edge- or levelsensitive.

The External Interrupt Polarity Regi ster controls w hich leve l or edge on ea ch pin will cause an interrupt.

R/W

External Interrupt Flag Register (EXTINT - 0xE01FC140)

When a pin is selected for its external interrupt function, the level or edge on that pin se le cte d by its bi ts i n the EXT POL AR and EXTMODE registers will set its interrupt flag in this register. This asserts the corresponding interrupt request to the VIC, which will cause an intrerrupt if interrupts from the pin are enabled.

Writing ones to bits EINT0 thr ough EINT3 in EXTINT register cl ears the corre sponding bits. In level-se nsitive m ode this action is efficacious only when the pin is in its innactive state.

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Table 15: External Interrupt Flag Register (EXTINT - 0xE01FC140)

EXTINT Function Description

In level-sensitive mode, this bit is set i f the EINT0 func tion is selec ted for its p in, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin.

0EINT0

1EINT1

2EINT2

Up to two pins can be selected to perform EINT0 function (see P0.1 and P0.16 description in "Pin Configuration" chapter.)

This bit is cleared by writi ng a one to it, except in level sensit ive mode when the pi n is in its active state.

In level-sensitive mode, this bit is set i f the EINT1 func tion is selec ted for its p in, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin.

Up to two pins can be selected to perform EINT1 function (see P0.3 and P0.14 description in "Pin Configuration" chapter.)

This bit is cleared by writi ng a one to it, except in level sensit ive mode when the pi n is in its active state.

In level-sensitive mode, this bit is set i f the EINT2 func tion is selec ted for its p in, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin.

Up to two pins can be selected to perform EINT2 function (see P0.7 and P0.15 description in "Pin Configuration" chapter.)

Reset

Value

This bit is cleared by writi ng a one to it, except in level sensit ive mode when the pi n is in its active state.

In level-sensitive mode, this bit is set i f the EINT3 func tion is selec ted for its p in, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin.

3EINT3

7:4 Reserved

Up to three pins can be selected to perform EINT3 function (see P0.9, P0.20 and P0.30 description in "Pin Configuration" chapter.)

This bit is cleared by writi ng a one to it, except in level sensit ive mode when the pi n is in its active state.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144)

Enable bits in the EXTWAKE register allow the external interrupts to wake up the processor if it is in Power Down mode. The related EINTn function must be mapped to the pin in order for the wakeup process to take place. It is not necessary for the interrupt to be enabled in the Vectored Interrupt Controller for a wakeup to take place. This arrangement allows additional capabilities, such as having an external interrupt input wake up the processor from Power Down mode without causing an interrupt (simply resuming operation), or allowing an interrupt to be enabled during Power Down without waking the processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application).

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Table 16: External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144)

EXTWAKE Function Description

0 EXTWAKE0 When one, assertion of EINT0 1 EXTWAKE1 When one, assertion of EINT1 2 EXTWAKE2 When one, assertion of EINT2 3 EXTWAKE3 When one, assertion of EINT3 will wake up the processor from Power Down mode. 0

7:4 Reserved

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

will wake up the processor from Power Down mode. 0 will wake up the processor from Power Down mode. 0 will wake up the processor from Power Down mode. 0

Reset

Value

External Interrupt Mode Register (EXTMODE - 0xE01FC148)

The bits in thi s registe r select whether ea ch EINT pin is level- o r edge-se nsitive. Only pin s that are select ed for the EINT fu nction (chapter Pin Connec t Block on pa ge 109) and enabled via the VI CIntEnabl e registe r (chapter Ve ctored Inte rrupt Con troller (VIC) on page 79) can cause interrupts from the External Interrupt function (though of course pins selected for ) other functions may cause interrupts from those funct ion s).

Note: Software should only change a bit in this regis ter when its interrupt is disable d in VICIntEnable, and sh ould write the corresponding 1 to EXTINT before re-enabling the interrupt, to clear the EXTINT bit that could be set by changing the mode.

Table 17: External Interrupt Mode Register (EXTMODE - 0xE01FC148)

EXTMODE Function Description

0 EXTMODE0 When 0, level-sensitivity is selected for EINT0. When 1, EINT0 is edge-sensitive. 0 1 EXTMODE1 When 0, level-sensitivity is selected for EINT1. When 1, EINT1 is edge-sensitive. 0 2 EXTMODE2 When 0, level-sensitivity is selected for EINT2. When 1, EINT2 is edge-sensitive. 0 3 EXTMODE3 When 0, level-sensitivity is selected for EINT3. When 1, EINT3 is edge-sensitive. 0

7:4 Reserved

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Reset

Value

External Interrupt Polarity Register (EXTPOLAR - 0xE01FC14C)

In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function (chapter Pin Connect Block on page 109) a nd e nab led in the VICIntEnable register (ch apt er Vec tore d Int errup t C ont roll er (VIC) on page

79) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions ).

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Table 18: External Interrupt Polarity Register (EXTPOLAR - 0xE01FC14C)

EXTPOLAR Function Description

0 EXTPOLAR0

1 EXTPOLAR1

2 EXTPOLAR2

3 EXTPOLAR3

7:4 Reserved

When 0, EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0). When 1, EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0).

When 0, EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1). When 1, EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1).

When 0, EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2). When 1, EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2).

When 0, EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3). When 1, EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3).

Reserved, user softw are should n ot write o nes to reser ved bits . The valu e read from a reserved bit is not defined.

Reset Value

Multiple External Interrupt Pins

Software can select multiple pins for each of EINT3:0 in the Pin Select registers, which are described in chapter Pin Connect Block on page 109. The external inte rrupt logic for each of EINT3:0 recei ves the stat e of al l of it s as so ci ated pin s from the p ins’ receivers, alon g with signals th at indic ate wh ether each p in is selected for the EINT functi on. The e xternal interrupt l ogic ha ndles the case when more than one pin is so selected, differently according to the state of its Mode and Polarity bits:

• In Low-Active Level Sensitive m ode, the stat es of all pin s selected f or EINT functiona lity are d igitally comb ined using a positive logic AND gate.

• In High-Active Level Sensitive mode , the states of all p ins selected fo r EINT functionalit y are digitally c ombined using a po sitive logic OR gate.

• In Edge Sensitive mode, regardless of polarity, the pin with the lowest GPIO port number is used. (Selecting multiple EINT pins in edge-sensitive mode could be considered a programmi ng error.)

The signal derived by this logic is the EINTi signal in the following logic schematic (Figure 14). When more than one EINT pi n is logically ORed , the interrupt service ro utine can read the s tates of the pins from G PIO port using

IO0PIN0 and IO1PIN registers, to determine which pin(s) caused the interrupt.

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EINTi

EXTPOLARi

EXTMODEi

Write 1 to EXTINTi

VPB Bus Data

Glitch

Filter

Reset

Wakeup Enable

(one bit of EXTWAKE)

pclk

Figure 14: External Interrupt Logic

VPB Read of EXTWAKE

EINTi to

Wakeup Timer

(Figure 16)

Interrupt Flag

(one bit of EXTINT)

pclk pclk

to VIC

VPB Read of EXTINT

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MEMORY MAPPING CONTROL

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. This allows code running in different memory spaces to have control of the interrupts.

Memory Mapping Control Register (MEMMAP - 0xE01FC040)

Table 19: MEMMAP Register

Address Name Description Access

0xE01FC040 MEMMAP

Table 20: Memory Mapping Control Register (MEMMAP - 0xE01FC040)

MEMMAP Function Description

1:0 MAP1:0

7:2 Reserved

*: The hardware reset value of the MAP bits is 00 for LPC2114/2124/2 212/2214 parts. Th e apparent reset va lue that the user will see will be altered by the Boot Loader code, which always runs initially at reset. User documentation will reflect this difference.

Memory mapping control. Selects whether the ARM interrupt vectors are read from the Flash Boot Block, User Flash or RAM.

00: Boot Loader Mode. Interrupt vectors are re-mapped to Boot Block. 01: User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 10: User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 11: User External memory Mode. Interrupt vectors a re re-mapped to exte rnal memory.

This mode is available in LPC2212/2214 only and must not be specified when LPC2114/2124 are used.

Warning: Improper set tin g of t his v alue may result in inco rrect o perati on of the devi ce. Reserved, user software shou ld not write ones to reserved b its. The value rea d from a

reserved bit is not defined.

R/W

Reset

Value*

Memory Mapping Control Usage Notes

Memory Mapping Cont rol simply selects one out of three available sources of data (sets of 64 bytes each) nec essary for handling ARM exceptions (interrupts).

For example, whenever a Software Interrupt request is generated, ARM core will always fetch 32-bit data "residing" on 0x0000 0008 (see Table 3, “ARM Exception Ve ctor Locations,” o n page 37). This means that wh en MEMMAP[1:0]=10 (User R AM Mode), read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. If MEMMAP[1:0]=01 (User Flash Mode), read/fetch from 0x0000 0008 will provide da ta st ored in on-chi p Flash locatio n 0x000 0 0008. In c ase of MEMM AP[1:0]=00 (Boot Lo ader Mod e), read/fetch from 0x0000 00 08 will provide da ta availbl e also at 0x7FFF E00 8 (Boot Block re mapped from on-c hip Flash memory).

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PLL (PHASE LOCKED LOOP)

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up into the cclk with the range of 10 MHz to 60 MHz using a Current Controlled Osc illator (CCO). Th e multiplier c an be an integ er value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on the LPC2114/2124/2212/2214 due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to prod uce t he ou tput clock. Since the minimum outpu t d iv ide r v al ue is 2 , it is insured th at the PL L output has a 50% dut y cycle. A block diagram of the PLL is shown in Figure 15.

PLL activation is con trolled via the PLLC ON register. The PLL mu ltiplier and divider v alues are controlle d by the PLLCFG regist er. These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all chip operations, including the Watchdog Timer, are dependent on the PLL when it is providing the chip clock, accidental changes to the PLL setup could result in unexpected behavior of the microcontroller. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLLFEED register.

The PLL is turned off and bypassed fol lowing a chip Reset and when by entering pow er Down mode. PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.

The PLL is controlled by the registers shown in Table 21. More detailed descriptions follow.

Warning: Improper setting of PLL values may result in incorrect operation of the device.

Table 21: PLL Registers

Address Name Description Access

PLL Control Register. Holding register for updating PLL control bits. Values

0xE01FC080 PLLCON

0xE01FC084 PLLCFG

0xE01FC088 PLLSTAT

0xE01FC08C PLLFEED

written to this register do not take effect until a valid PLL feed sequ ence has taken place.

PLL Configuration Register. Holding register for updating PLL configuration values. Values written to this register do not take effect until a valid PLL feed sequence has taken place.

PLL Status Register. Read-back register for PLL control and configuration information. If PLLCON or PLLCFG have been written to, but a PLL feed sequence has not yet occurred, they will not reflect the current PLL state. Reading this registe r provides the actual val ues controlling the PL L, as well as the status of the PLL.

PLL Feed Register. This register enables loading of the PLL control and configuration information from the PLLCON and PLLCFG registers into the shadow registers that actually affect PLL operation.

R/W

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PLLC

PLLE

OSC

PSEL[1:0]

PLOCK

MSEL[4:0]

Clock

Synchronization

Direct

Bypass

Phase-

Frequency

Detector

CCO

/2P

cclk

fout

Div-by-M

msel<4:0>

Figure 15: PLL Block Diagram

PLL Control Register (PLLCON - 0xE01FC080)

The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of th e m ul tipl ie r and di vi der va lues. Connecting the PLL causes the process or a nd a ll ch ip functions to run from the PLL output clock. Changes to the PLLCO N register d o not take effect until a co rrect PLL fee d sequen ce has been given (se e PLL Feed Register (PLLFEED - 0xE01FC08C) description).

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Table 22: PLL Control Register (PLLCON - 0xE01FC080)

PLLCON Function Description

0 PLLE

1 PLLC

7:2 Reserved

The PLL must be set up, enabled, and Lock established before it may be used as a clock source. When switching from the oscillator clock to the PLL output or vice versa, internal circuitry synchronizes the operation in order to ensure that glitches are not generated. Hardw are does not insu re that the PLL is lo cked bef ore it is con nected or autom atically di sconnec t the PLL i f lock is lost during opera tion. In the event of l oss of PLL lock, it i s likely that the o scillator clock has become unst able and disconnecting the PLL will not remedy the situation.

PLL Enable. When one, and after a valid PLL feed, this bit will activate the PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 24.

PLL Connect. When PLLC and PLLE are both set to one, and after a valid PLL feed, connects the PLL as the clock source for the LPC2114/2124/2212/2214. Otherwise, the oscillator clock is used directly by the LPC2114/2124/2212/2214. See PLLSTAT register, Table 24.

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

Reset

Value

PLL Configuration Register (PLLCFG - 0xE01FC084)

The PLLCFG register contains the PLL multiplier and divider values. Changes to the PLLCFG register do not take effect until a correct PLL feed sequenc e has been giv en (see PLL Feed Re gister (PLLFEED - 0xE01FC08C) desc ription). Calcul ations for the PLL frequency, and multiplier and divider values are found in the PLL Frequency Calculation section.

Table 23: PLL Configuration Register (PLLCFG - 0xE01FC084)

PLLCFG Function Description

PLL Multiplier value. Supplies the value "M" in the PLL frequency calculations.

4:0 MSEL4:0

6:5 PSEL1:0

7 Reserved

Note: For details on sele cting the rig ht value for MSEL 4:0 see sec tion "PLL Frequ ency Calculation" on page 64.

PLL Divider value. Supplies the value "P" in the PLL frequency calculations. Note: For details on selecting the right val ue for PSEL1:0 see section "PL L Frequency

Calculation" on page 64. Reserved, user software shou ld not write ones to reserved b its. The value rea d from a

reserved bit is not defined.

Reset

Value

PLL Status Register (PLLSTAT - 0xE01FC088)

The read-only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read, as well as the PLL status. PLLSTAT may di sagree with values foun d in PLLCON and PLLCFG beca use changes to those re gisters do not take effe ct until a proper PLL feed has occurred (see PLL Feed Register (PLLFEED - 0xE01FC08C) description).

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Table 24: PLL Status Register (PLLSTAT - 0xE01FC088)

PLLSTAT Function Description

4:0 MSEL4:0 Read-back for the PLL Multiplier value. This is the value currently used by the PLL. 0 6:5 PSEL1:0 Read-back for the PLL Divider value. This is the value currently used by the PLL. 0

7 Reserved

8 PLLE

9 PLLC

10 PLOCK

15:11 Reserved

PLL Interrupt

The PLOCK bit in the PLLSTAT register is connected to the interrupt controller. This allows for software to turn on the PLL and continue with other fun ctions without having to wait for the PLL to ach ieve lock. Wh en the interru pt occurs (PLOCK = 1), the PLL may be connected, and the interrupt disabled.

Reserved, user software shou ld not write ones to reserved bits. The value rea d from a reserved bit is not defined.

Read-back for the PLL Enable bit. When one, the PLL is currently activated. When zero, the PLL is turne d off. This bit is aut omatically cleared w hen Power Do wn mode is activated.

Read-back for the PLL Conne ct bit. W hen PLLC and PLLE are both one, the PLL is connected as the clo ck source for the LPC2 114/2124/2 212/2214. Whe n either PLLC or PLLE is zero, the PLL is bypassed and the oscillator clock is used directly by the LPC2114/2124/2212/22 14. This bit is autom atically cleared w hen Power Down mode is activated.

Reflects the PLL Lock status . When zero , the PLL is no t locked. Wh en one, the PLL is locked onto the requested frequency.

Reserved, user software shou ld not write ones to reserved bits. The value rea d from a reserved bit is not defined.

Reset

Value

PLL Modes

The combinations of PLLE and PLLC are shown in Table 25.

Table 25: PLL Control Bit Combinations

PLLC PLLE PLL Function

0 0 PLL is turned off and disconnected. The system runs from the unmodified clock input. 0 1 The PLL is active, but not yet connected. The PLL can be connected after PLOCK is asserted.

1 1 The PLL is active and has been connected as the system clock source.

Same as 0 0 combination. This preven ts the possibility of the PLL bei ng connected without als o being enabled.

PLL Feed Register (PLLFEED - 0xE01FC08C)

A correct feed sequence mus t be written to the PLLFEED regi ster in or der for chang es to the PLLCO N and PLLCFG reg isters to take effect. The feed sequence is:

1. Write the value 0xAA to PLLFEED

2. Write the value 0x55 to PLLFEED.

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The two writes must be in the correct sequence, and must be consecutive VPB bus cycles. The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not become effective.

Table 26: PLL Feed Register (PLLFEED - 0xE01FC08C)

PLLFEED Function Description

7:0 PLLFEED

The PLL feed sequence must be written to this register in order for PLL configuration and control register changes to take effect.

Reset

Value

undefined

PLL and Power Down Mode

Power Down mode automatically turns off and disconnects the PLL. Wakeup from Power Down mode does not automatically restore the PLL settings, this must be done in software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL can be called at the begin ning of a ny inte rrupt service ro utine th at migh t be cal led due to the wake up. It is import ant not to attempt to restart the PLL by simply feeding it when execution resumes after a wakeup from Power Down mode. This would enable and connect the PLL at the same time, before PLL lock is established.

PLL Frequency Calculation

The PLL equations use the following parameters: F

OSC

CCO

cclk the PLL output frequency (also the processor clock frequency) M PLL Multiplier value from the MSEL bits in the PLLCFG register P PLL Divider value from the PSEL bits in the PLLCFG register

the frequency from the crystal oscillator the frequency of the PLL current controlled oscillator

The PLL output frequency (when the PLL is both active and connected) is given by: F

cclk = M * F

or cclk = ———

osc

cco

2 * P

The CCO frequency can be computed as: F

= cclk * 2 * P or F

cco

= F

* M * 2 * P

osc

The PLL inputs and settings must meet the following:

• F

is in the range of 10 MHz to 25 MHz.

osc

• cclk is in the range of 10 MHz to F

is in the range of 156 MHz to 320 MHz.

• F

cco

(the maximum allowed frequency for the LPC2114/2124/2212/2214).

max

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Procedure for Determining PLL Settings

If a particular application uses the PLL, its configuration may be determined as follows:

1. Choose the desired processor operating frequency (cclk). This may be based on processor throughput requirements, need to support a spec ific set o f UART baud rates, etc. Be ar in m ind that pe riph eral d evices may be run nin g from a lowe r clock than the processor (see the VPB Divider description in this chapter).

2. Choose an oscillator frequency (F

3. Calculate the value of M to c onfigure the MSEL bits. M = cclk / F to the MSEL bits in PLLCFG is M - 1 (see Table 28).

4. Find a value for P to con fig ure the PSEL b its, s uc h t hat F the equation given abov e. P must have on e of the valu es 1, 2, 4, or 8. Th e value writt en to the PSEL bits in PL LCFG is 00

). cclk must be the whole (non-fractional) multiple of F

osc

. M must be in the rang e of 1 to 32 . Th e va lue w ritte n

osc

is within its defined frequency lim its. F

cco

for P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see Table 27).

Table 27: PLL Divider Values

osc

is calculated using

cco

PSEL Bits

(PLLCFG bits 6:5)

00 1 01 2 10 4 11 8

Table 28: PLL Multiplier Values

MSEL Bits

(PLLCFG bits 4:0)

00000 1 00001 2 00010 3 00011 4

... ...

11110 31 11111 32

Value of P

Value of M

PLL Example

System design asks for F Based on th ese specific ations, M = cclk / F Value for P can be derived from P = F

the lowest allowed fre quency for F

= 10 MHz and requires cclk = 60 MHz.

osc

= 60 MHz / 10 MHz = 6. Consequenty, M-1 = 5 will be written as PLLCFG 4:0.

osc

/ (cclk * 2), using condition that F

cco

= 156 MHz, P = 156 MHz / (2*60 MHz) = 1.3. The highest F

cco

must be in range of 156 MHz to 320 M Hz. Assuming

cco

frequency criteria prod uces

cco

P = 2.67. The only solut ion for P tha t sa tis fies both of these requirements and is listed in Table 27 i s P = 2. Th ere fore, PLLCFG 6:5 = 1 will be used.

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POWER CONTROL

The LPC2114/2124/22 12/221 4 suppo rts two redu ced p ower mo des: Idle m ode a nd Powe r Down mode . In Id le m ode, e xecut ion of instructions is suspen ded until ei ther a Reset o r interrupt occurs. Peri pheral functi ons contin ue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.

In Power Down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power Down mode and the logic levels of chip pins remain static. The Power Down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power Down mode reduces chip power consumption to nearly zero.

Entry to Power Down and Idle mode s must be coord inated with program ex ecution. Wake up from Power Down or Id le modes via an interrupt resumes program execut ion in such a wa y that no instru ctions are los t, incomplete, or repeated. Wake u p from Power Down mode is discussed further in the description of the Wakeup Timer later in this chapter.

A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.

The Power Control function contains two registers, as shown in Table 29. More detailed descriptions follow.

Table 29: Power Control Registers

Address Name Description Access

0xE01FC0C0 PCON

0xE01FC0C4 PCONP

Power Control Register. This register contains control bits that enable the two reduced power operati ng modes of the L PC2114/2124 /2212/2214. See Ta ble 30.

Power Control for Peripheral s Register. This register contains control bits that enable and disable indiv idual pe riphera l functi ons, Allo wing elim inati on of pow er consumption by peripherals that are not needed.

R/W

Power Control Register (PCON - 0xE01FC0C0)

The PCON register contai ns two bits. Writin g a one to the corres ponding bit caus es entry to either the Power Down or Idle mode. If both bits are set, Power Down mode is entered.

Table 30: Power Control Register (PCON - 0xE01FC0C0)

PCON Function Description

Idle mode - when 1, this bit causes the processor clock to be stopped, while on-chip

0IDL

1PD

peripherals remain activ e. Any enabled interrupt from a peripheral or an ex ternal interrupt source will cause the processor to resume execution.

Power Down mode - when 1, this bit causes the oscillator and all on -chip clocks to be stopped. A wakeup condition from an external interrupt can cause the oscillator to restart, the PD bit to be cleared, and the processor to resume execution.

Reset

Value

7:2 Reserved

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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Power Control for Peripherals Register (PCONP - 0xE01FC0C4)

The PCONP register all ows turn ing off selec ted pe riphera l func tions for the p urpose of savin g pow er. A few p eriphe ral fun ctions cannot be turned off (i.e. the Watchdog timer, GPIO, the Pin Con ne ct blo ck , a nd the Sys te m Co ntro l b loc k ). Ea ch bi t in PC ON P controls one of the peripherals. The bit numbers correspond to the related peripheral number as shown in the VPB peripheral map in the LPC2114/2124/2212/2214 Memory Addressing section.

Table 31: Power Control for Peripherals Register for LPC2114/2124 (PCONP - 0xE01FC0C4)

PCONP Function Description

0 Reserved

1 PCTIM0 When 1, TIMER0 is enabled. When 0, TIMER0 is disabled to conserve power. 1 2 PCTIM1 When 1, TIMER1 is enabled. When 0, TIMER1 is disabled to conserve power. 1 3 PCURT0 When 1, UART0 is enabled. When 0, UART0 is disabled to conserve power. 1 4 PCURT1 When 1, UART1 is enabled. When 0, UART1 is disabled to conserve power. 1 5 PCPWM0 When 1, PWM0 is enabled. When 0, PWM0 is disabled to conserve power. 1

6 Reserved

7 PCI2C When 1, the I 8 PCSPI0 When 1, the SPI0 interface is enabled. When 0, the SPI0 is disabled to conserve power. 1

9 PCRTC When 1, the RTC is enabled. When 0, the RTC is disabled to conserve power. 1 10 PCSPI1 When 1, the SPI1 interface is enabled. When 0, the SPI1 is disabled to conserve power. 1 11 Reserved User software should write 0 here to reduce power consumption. 1 12 PCAD When 1, the A/D converter is enabled. When 0, the A/D is disabled to conserve power. 1

31:13 Reserved

Reserved, user software s hould not writ e ones to res erved bits. The value read fro m a reserve d bit is not defined.

User software should not write ones to reserved bits. The value read from a reserved bit is not defined.

C interface is enabled. When 0, the I2C interface is disabled to conserve power. 1

Reserved, user software s hould not writ e ones to res erved bits. The value read fro m a reserve d bit is not defined.

Reset Value

Table 32: Power Control for Peripherals Register for LPC2212/2214 (PCONP - 0xE01FC0C4)

PCONP Function Description

0 Reserved

1 PCTIM0 When 1, TIMER0 is enabled. When 0, TIMER0 is disabled to conserve power. 1

2 PCTIM1 When 1, TIMER1 is enabled. When 0, TIMER1 is disabled to conserve power. 1

3 PCURT0 When 1, UART0 is enabled. When 0, UART0 is disabled to conserve power. 1

4 PCURT1 When 1, UART1 is enabled. When 0, UART1 is disabled to conserve power. 1

5 PCPWM0 When 1, PWM0 is enabled. When 0, PWM0 is disabled to conserve power. 1

Reserved, user software s hould not writ e ones to res erved bits. The value read fro m a reserve d bit is not defined.

Reset Value

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Table 32: Power Control for Peripherals Register for LPC2212/2214 (PCONP - 0xE01FC0C4)

PCONP Function Description

6 Reserved

7 PCI2C When 1, the I

8 PCSPI0 When 1, the SPI0 interface is enabled. When 0, the SPI0 is disabled to conserve power. 1

9 PCRTC When 1, the RTC is enabled. When 0, the RTC is disabled to conserve power. 1 10 PCSPI1 When 1, the SPI1 interface is enabled. When 0, the SPI1 is disabled to conserve power. 1

11 PCEMC

12 PCAD When 1, the A/D converter is enabled. When 0, the A/D is disabled to conserve power. 1

31:13 Reserved

User software should not write ones to reserved bits. The value read from a reserved bit is not defined.

C interface is enabled. When 0, the I2C interface is disabled to conserve power. 1

When 1, the External Memory Controller is enabled. When 0, the EMC is disabled to conserve power.

Reserved, user software s hould not writ e ones to res erved bits. The value read fro m a reserve d bit is not defined.

Reset Value

POWER CONTROL USAGE NOTES

After every reset, PCONP reg ist er contai ns the valu e that en ables al l inte rfaces and periphe rals c ontrol led b y the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, user’s application has no need to access the PCONP in order to start using any of the on-board peripherals.

Power saving orien ted s ystems shoul d hav e 1s in the PCONP reg ister only in pos ition s that matc h peri pherals reall y us ed in the application. All other bits , declare d to be "Rese rved" or ded icate d to the perip herals not used in th e current appli catio n, must be cleared to 0.

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RESET

Reset has two sources on the LPC2114/2124/2212/2214: the RESET pin and Watchdog Reset. The RESET pin is a Schmitt trigger input pin with an additional glitch fi lter. Assertion of ch ip Reset by any so urce starts the Wakeup Timer (see Wakeup Timer description later i n this chapter), caus ing reset to remain as serted until the ex ternal Reset is de- asserted, the osc illator is runnin g, a fixed number of c loc ks h av e pas se d, and the Flash controller has com pl ete d i ts in iti ali zation. The relationship between Res et , the oscillator, and the Wakeup Timer are shown in Figure 16.

The Reset glitch fi lter al lows th e proce ssor t o igno re exte rnal reset p ulses that a re very short , and al so de termin es the minim um duration of R when crystal oscillator is fully running and an adequate signal is present on the X1 pin of the LPC2114/2124/2212/2214. Assuming that an external crystal is used in the crystal os cilla tor subs ystem , after power on, the R for 10 ms. For all subsequent resets when crystal osillator is already running and stable signal is on the X1 pin, the R needs to be asserted for 300 ns only.

ESET that must be asserted in order to guaran tee a chip reset. Once as serted, RESET pin can be deasserted only

ESET pin should be asserted

ESET pin

Speaking in general, there are no sequence requirements for powering up the supplies (V proper reset handli ng It is absolut ely necessary to have valid vol tage supply on V dedicated hardware are powe red by the m. V Consequently, not providing V

power supply will not affect the reset sequence itself, but will prevent microcontroller from

pins enable microcontroller’s interface to the environment via its digit al pins.

pins, since on-chi p Reset circuit and o scillator

, V3, V

and V3A). However, for

18A

communicating with external world. When the internal Reset is rem oved, the p rocessor be gins executin g at address 0, which is initially the Reset vector mappe d from

the Boot Block. At that po int, all of the processor and peripheral registers have been initialized to predetermined values. External and internal Resets have some small differences. An external Reset causes the value of certain pins to be latched to

configure the part. External circuitry cannot determine when an internal Reset occurs in order to allow setting up those special pins, so those latches are not reloaded during an internal Reset. Pins that are examined during an external Reset for various purposes are: P1.20/TRACESYN C, P1.26/RTCK, BOOT1 and BOOT0 (se e chapters Pin Configuration on page 93, Pin Connect Block on page 109 and External Mem ory Controller (EMC) on page 41). Pin P0.14 (see Fl ash Memory System an d Programming on page 217) is exemined by on-chip bootloader when this code is executed after reset.

It is possible for a chip Reset to occur during a Flash programming or erase operation. The Flash memory will interrupt the ongoing operation and hold off the completion of Reset to the CPU until internal Flash high voltages have settled.

External

Reset

Watchdog

Reset

Reset to

kFlash shell

Reset to

PCON.PD

Power Down

EINT0 Wakeup EINT1 Wakeup EINT2 Wakeup EINT3 Wakeup

Oscillator

Output (F

OSC

)

Wakeup Timer

Start Count 2

Write "1"

from VPB

Reset

VPB Read

of PDbit

in PCON

OSC

PLL

Figure 16: Reset Block Diagram including Wakeup Timer

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VPB DIVIDER

The VPB Divider determines the relationshi p between the processor cl ock (cclk) and the clock used by peripheral devices (pcl k). The VPB Divider serves t wo purpose s. The fi rst is to p rovides peripheral s with desi red pclk v ia VPB bus so that th ey can operate at the speed c hosen for the ARM p roces sor. In order to ac hieve this, the VP B bu s ma y be slowed dow n to one ha lf or one fo urth of the processor clock ra te. Beca use the VPB bu s mus t work prope rly at po wer up (an d its ti ming can not be a ltered i f it doe s not work since the VPB divider control registers reside on the VPB bus), the default condition at reset is for the VPB bus to run at one quarter speed. The se co nd p urpo se of the VPB Div ide r is to all ow p ower sav in gs when an app lic at ion do es not requ ire any peripherals to run at the full processor rate.

The connection of the VPB Divider relative to the oscillator and the processor clock is shown in Figure 17. Because the VPB Divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.

VPBDIV Register (VPBDIV - 0xE01FC100)

The VPB Divider register contains two bits, allowing three divider values, as shown in Table 34.

Table 33: VPBDIV Register Map

Address Name Description Access

0xE01FC100 VPBDIV Controls the rate of the VPB clock in relation to the processor clock. R/W

Table 34: VPB Divider Register (VPBDIV - 0xE01FC100)

VPBDIV Function Description

The rate of the VPB clock is as follows: 0 0: VPB bus clock is one fourth of the processor clock. 0 1: VPB bus clock is the same as the processor clock.

1:0 VPBDIV

3:2 Reserved

5:4 XCLKDIV

7:6 Reserved

1 0: VPB bus clock is one half of the processor clock. 1 1: Reserved. If this value is written to the VPBDIV register, it has no effect (the previous setting is retained).

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

In the LPC2212/2214 (part s in 144 packages) o nly, these bits c ontrol the clock that can be driven onto the A23/XCLK pin. They have the same encoding as the VPBDIV bits above. A bit in the PINSEL2 register (Pin Conn ect Block on page 109) controls whether the pin carries A23 or the clock selected by this field.

Note: If this field and VPBDIV ha ve the same value, the same clock is used o n the VPB and XCLK. (This might be useful for external logic dealing with the VPB

peripherals). Reserved, user software shou ld not write ones to reserved b its. The value rea d from a

reserved bit is not defined.

Reset

Value

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Crystal Oscillator

External Clock Source

)

osc

PLL

Processor Clock

(cclk)

VPB Divider

Figure 17: VPB Divider Connections

VPB Clock

(pclk)

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WAKEUP TIMER

The purpose of the wakeup timer is to ensure that the oscillator and other analog functions required for chip operation are fully functional before the pr ocessor is allowed to e xecute instructi ons. This is important at power on, all types of R eset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power Down mode, any wakeup of the processor from Power Down mode makes use of the Wakeup Timer.

The Wakeup Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chi p, or som e event ca used th e chip to exit Powe r down mode, som e time is req uired fo r the osc illato r to produce a signal of su fficie nt amplitud e to dr ive the c lock logi c. The am ount of tim e depe nds on m any fact ors, inclu ding the rate of Vdd ramp (in the cas e o f po w er on ), th e ty pe of c ry sta l a nd i ts ele ctri ca l cha r act eris ti cs (if a quartz crystal is used), as well as any other external circuit ry (e.g. cap acitor s), and the c haracteris tics of th e oscil lator its elf unde r the exis ting ambien t con ditions.

Once a clock is detected, the Wakeup Timer counts 4096 clocks, then enables the Flash memory to initialize. When the Flash memory initialization is complete, the processor is released to execute instructions if the external Reset has been de-asserted. In the case where an external clock source is used in the system (as opposed to a crystal connected to the oscillator pins), the possibility that there could be l ittle or no d elay for oscilla tor start-up m ust be consi dered. The Wake up Timer desi gn then ens ures that any other required chip functions will be operational prior to the beginning of program execution.

The LPC2114/2124/2212/2214 does not contain any analog function such as comparators that operate without clocks or any independent clo ck source such as a dedica ted Watchdog o scillator. The on ly remaining functions that can operate i n the absence of a clock source ar e the external interru pts (EINT0, EINT1, EINT2 and EINT3). When an external interrupt is enabled for wakr up, and its selected event occurs, an oscillator wakeup cycle is started. The actual interrupt (if any) occurs after the wakeup time expires, and is handled by the Vectored Interrupt Controller (VIC).

However, the pin multiplexing on the LPC2114/2124/2212/2214 (see Pin Configuration on page 93 and Pin Connect Block on page 109) was designed to allow other peripherals to, in effect, bring the device out of power down mode. The following pinfunction pairings a llow i nterrupts from event s rela ting to UART0 or 1, SPI 0 or 1, or th e I / EINT2, RxD1 / EINT3, DCD1 / EINT1, RI1 / EINT2, SSEL1 / EINT3.

To put the device in power down mode and allow activity on one or more of these buses or lines to power it back up, software should reprogram the pi n function to Extern al Interrupt, sel ect the appropr iate mode and p olarity for the I nterrupt, and then select power down mode. Upon wakeup software should restore the pin mulitplexing to the peripheral function.

All of the bus- or line-activity indications in the list above happen to be low-active. If software wants the device to come out of power -down mode in response to actity on more than one pin that share the same EINTi channel, it should program low-level sensitivity for that channel, because only in level mode will the channel logically OR the signals to wake the device.

The only flaw in this scheme is that the time to restart the oscillator prevents the LPC2114/2124/2212/2214 from capturing the bus or line activity that wakes it up. Idle mode is more appropriate than power-down mode for devices that must capture and respond to external activity in a timely manner.

To summarize: on the LPC2114/2124/2212/2214, the Wakeup Timer enforces a minimum reset duration based on the crystal oscillator, and is activated whenever there is a wakeup from Power Down mode or any type of Reset.

C: RxD0 / EINT0, SDA / EINT1, SSEL0

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5. MEMORY ACCELERATOR MODULE (MAM)

INTRODUCTION

Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM instruction that will be needed in its latches in time to prevent CPU fetch stal ls. The me tho d use d is to spli t the Fl as h memory into two bank s, each cap abl e of ind ep end ent accesses. Each of the two F lash bank s has i ts ow n Prefetc h Buffe r and Bra nch Tra il Buffe r. The Bra nch Trail Buffers for the t wo banks capture two 128-b it l ine s of Fl as h da ta whe n an In stru ction Fetch is not satisfied b y ei ther the Prefetch buffer nor Branch Trail buffer for its bank, and for which a prefetch has not been initiated. Each prefetch buffer captures one 128-bit line of instructions from its Flash bank, at the conclusion of a prefetch cycle initiated speculatively by the MAM.

Each 128 bit value includes four 32-bit ARM instructions or eight 16-bit Thumb instructions. During sequential code execution, typically one Flash bank contains or is fetching the current instruction and the entire Flash line that contains it. The other bank contains or is prefetching the next sequential code line. After a code line delivers its last instruction, the bank that contained it begins to fetch the ne xt line in that bank.

Timing of Flash read operations is programmable and is described later in this section as well as in the System Control Block section.

Branches and othe r pro gram f low c ha nge s cause a break in the sequential flow of instruction fetches described abo ve. Wh en a backward branch occurs, there is a distinct possibility that a loop is being executed. In this case the Branch Trail Buffers may already contain the target instruction. If so, execution continues without the need for a Flash read cycle. For a forward branch, there is also a chance that the new addres s is already contai ned in on e of the Prefetc h Buffers . If it is, the bra nch is again taken with no delay.

When a branch outsi de the con ten ts of the Branch Trail an d Prefetc h buffe rs is ta ken, on e Flas h Acces s cy cle is ne ede d to loa d the Branch Trail buffers . Subseq uently , there wil l typic ally b e no furthe r fetch de lays unti l anothe r such “Instr uct ion Mi ss” occurs.

The Flash memory controller detects data accesses to the Flash memory and uses a separate buffer to store the results in a manner similar to that us ed during code fetches . This allows faster acces s to data if it is accessed sequ entially. A single lin e buffer is provided for data accesses, as opposed to the two buffers per Flash bank that are provided for code accesses. There is no prefetch function for data accesses.

Memory Accelerator Module Blocks

The Memory Accelerator Module is divided into several functional blocks:

• A Flash Address Latch for each bank. An Incrementer function is associated with the Bank 0 Flash Address latch.

• Two Flash Memory Banks.

• Instruction Latches, Data Latches, Address Comparison latches.

• Wait logic Figure 18 shows a simplified block diagram of the Memory Accelerator Module data paths.

In the following de scriptions, the term “fetch” applies to an ex plicit Flas h read requ est from t he ARM. “prefetch” is used to denote a Flash read of instructions beyond th e current processor fetch address.

Flash Memory Banks

There are two banks of Flash memory in order to allow two parallel accesses and eliminate delays for sequential accesses.

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Flash programming oper ations are not con trolled by the Me mory Ac celera tor Modu le, but are handle d as a separat e fun ction. A “boot block” sector contains Flash programming algorithms that may be called as part of the application prog ram, and a loader that may be run to allow serial programming of the Flash memory.

The Flash memories are wired so that each sector exists in both banks, such that a sector erase operation acts on part of both banks simultaneously. In effect, the existence of two banks is transparent to the programming functions.

Memory Address

Flash Memory

ARM Local Bus

Figure 18: Simplified Block Diagram of the Memory Accelerator Module

Bus

Interface

Bank 0

Selection

Memory Data

Flash Memory

Bank 1

Bank

Instruction Latches and Data Latches

Code and Data accesses are treated separately by the Memory Accelerator Module. There are two sets of 128-bit Instruction Latches and 12 -bit Com parison Address L atches associated with each Flash Bank . One of the two se ts, called the Branch Trail Buffer, holds the data and comparison address for that bank from the last Instruction miss. The other set, called the Prefetch Buffer, holds the data and comparison address from prefetches undertaken speculatively by the MAM. Each Instruction Latch holds 4 words of code (4 ARM instructions, or 8 Thumb instructions).

Similarly there i s a 1 28-bit Data La tch an d 1 3-bit Data Addr ess l atch, that ar e u sed d uring Da ta cy cles . This sing le se t of la tches is shared by bot h Flas h bank s. Eac h Data a cces s that is not in the Data latch caus es a F lash f etch o f 4 words of data, wh ich ar e captured in the Data latch. This speeds up sequential Data operations, but has little or no effect on random accesses.

Flash Programming Issues

Since the Flash memory does not al low accesses durin g programming and erase op erations, it is necessar y for the MAM to force the CPU to wait if a memory access to a Flash address is requested while the Flash module is busy. (This is accomplished by asserting the ARM7 TDMI-S local bus signal CLKEN.) Under some conditi ons, this dela y could result in a Watchdog ti me-out. The user will need to be aw are of this pos sibilit y and take s teps to insu re that an unw anted Watc hdog reset d oes not cau se a system failure while programming or erasing the Fl ash memory.

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In order to preclude the possibility of stale data being read from the Flash memory, the MAM holding latches are automatically invalidated at the be ginning of any Fl ash programming o r erase operation . Any subsequen t read from a Flash ad dress will cause a new fetch to be initiated after the Flash operation has completed.

MEMORY ACCELERATOR MODULE OPERATING MODES

Three modes of operation are defined for the MAM, trading off performance for ease of predictability:

0) MAM off. All memory requests result in a Flash read operation (see note 2 below). There are no instruction prefetches.

1) MAM partially ena bl ed. Sequential instruction accesses ar e fu lfi lle d from the holding la tches if the data is present. Instruction prefetch is enabled. Non-sequential instruction accesses initiate Flash read operations (see note 2 below). This means that all branches cause mem ory fe tches . All dat a opera tions c ause a Flash rea d beca use bu ffered d ata ac cess timin g is ha rd to pre dict and is very situation dependent.

2) MAM fully enabled . Any memory request (code or data) for a value that is contai ned in one of the correspondi ng holding latches is fulfilled from the latch. Instruction prefetch is enabled. Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches.

Table 35: MAM Responses to Program Accesses of Various Types

Program Memory Request Type

MAM Mode

012

Sequential access, data in MAM latches Initiate Fetch

Use Latched Data Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch Non-Sequential access, data in MAM latches Initiate Fetch

Initiate Fetch

Non-Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch

1, 2

Use Latched Data

Initiate Fetch

Use Latched Data

Initiate Fetch

Table 36: MAM Responses to Data and DMA Accesses of Various Types

MAM Mode

Data Memory Request Type

012

Sequential access, data in MAM latches Initiate Fetch

Initiate Fetch

Use Latched Data Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Non-Sequential access, data in MAM latches Initiate Fetch

Initiate Fetch

Use Latched Data Non-Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch

1. Instruction prefetch is enabled in modes 1 and 2.

2. The MAM actually uses latch ed data if it i s availa ble, but mi mics the t iming of a F lash read o peration. Th is saves power whil e resulting in the same execution timing. The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock.

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MAM CONFIGURATION

After reset the MAM defaults to the disabled state. Software can turn memory access acceleration on or off at any time. This allows most of an application to be run at the highest possible performance, while certain functions can be run at a somewhat slower but more predictable rate if more precise timi ng is required.

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

Table 37: Summary of System Control Registers

Name Description Access

MAM

Memory Accelerator Module Control Register. Determines the MAM

MAMCR

MAMTIM

*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.

functional mode, that is, to what extent the MAM performance enhancements are enabled. See Table 38.

Memory Accelerator Module Timing control. Determines the number of clocks used for Flash memory fetches (1 to 7 processor clocks).

R/W 0 0xE01FC000

R/W 0x07 0xE01FC004

Reset

Value*

Address

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MAM Control Register (MAMCR - 0xE01FC000)

Two configuration bi ts select the three MAM operating modes, as shown in Table 38. Following Reset, MAM functions are disabled. Changing the MAM operating mode causes the MAM to invalidate all of the holding latches, resulting in new reads of Flash information as required.

Table 38: MAM Control Register (MAMCR - 0xE01FC000)

MAMCR Function Description

These bits determine the operating mode of the MAM as follows:

1:0

7:2 Reserved

MAM mode

control

0 0 - MAM functions disabled. 0 1 - MAM functions partially enabled. 1 0 - MAM functions fully enabled. 1 1 - reserved

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

Reset

Value

MAM Timing Register (MAMTIM - 0xE01FC004)

The MAM Timing regis ter determines how many cclk cycles are used to acces s the Flash memory. This al lows tuning MAM timing to match the processor operating frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash accesses would esse nti a ll y re mo ve th e M A M fro m ti mi ng c alc ul atio ns . In th is cas e the MAM mo de m ay be se le cted to optimize power usage.

Table 39: MAM Timing Register (MAMTIM - 0xE01FC004)

MAMTIM Function Description

These bits set the duration of MAM Flash fetch operations as follows: 0 0 0 = 0 - Reserved. 0 0 1 = 1 - MAM fetch cycles are 1 processor clock (cclk) in duration. 0 1 0 = 2 - MAM fetch cycles are 2 processor clocks (cclks) in duration. 0 1 1 = 3 - MAM fetch cycles are 3 processor clocks (cclks) in duration. 1 0 0 = 4 - MAM fetch cycles are 4 processor clocks (cclks) in duration. 1 0 1 = 5 - MAM fetch cycles are 5 processor clocks (cclks) in duration. 1 1 0 = 6 - MAM fetch cycles are 6 processor clocks (cclks) in duration. 1 1 1 = 7 - MAM fetch cycles are 7 processor clocks (cclks) in duration.

2:0

MAM Fetch

Cycle timing

Reset

Value

0x07

Warning: Improper set tin g of t his v alue may result in inco rrect o perati on of the devi ce.

7:3 Reserved

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

MAM USAGE NOTES

When changing M AM timing, the MAM mu st f irs t be turn ed off by writing a zero to MAMCR. A new va lue ma y then be written to MAMTIM. Finally, the MAM may be turned on again by writing a value (1 or 2) corresponding to the desired operating mode to MAMCR.

For system cloc k sl ower than 2 0 MHz , MAM TIM c an be 001. Fo r sys tem clock betwe en 20 MH z and 40 M Hz, Fl ash acces s ti me is suggested to be 2 CCLKs, while in systems with system clock faster than 40 MHz, 3 CCLKs are proposed.

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6. VECTORED INTERRUPT CONTROLLER (VIC)

FEATURES

• ARM PrimeCell™ Vectored Interrupt Controller

• 32 interrupt request inputs

• 16 vectored IRQ interrupts

• 16 priority levels dynamically assigned to interrupt requests

• Software interrupt generation

DESCRIPTION

The Vectored Interrupt Con troller (VIC) takes 32 interrupt reque st inputs and p rogrammably assig ns them into 3 cate gories, FIQ, vectored IRQ, and non-vectored IR Q. The pro grammable ass ignment sche me means that priorities of interrupts from the v arious peripherals can be dynamically assigned and adjusted.

Fast Interrupt reQuest (FIQ) requests have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, be caus e then the FIQ s ervice routin e can simp ly sta rt de aling with tha t de vice . But if m ore th an one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority, but ony 16 of the 32 requests can be assig ne d to this categ ory . Any of the 32 reques ts can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority. The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The

IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highe st-priority requesting IR Qs service routine, otherwis e it provides the address of a default routine that is shared by al l the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are act ive.

All registers in the VIC are word registers. Byte and halfword reads and write are not supported. Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell™ Vectored Interrupt Controller

(PL190) documentation.

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The VIC implements the registers shown in Table 40. More detailed descriptions follow.

Table 40: VIC Register Map

Name Description Access

VICIRQStatus

VICFIQStatus

VICRawIntr

VICIntSelect

VICIntEnable

VICIntEnClr

VICSoftInt

VICSoftIntClear

VICProtection

IRQ Status Register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ.

FIQ Status Requests. Th is reg ister read s out the st ate of thos e inte rrupt requests that are enabled and classified as FIQ.

Raw Interrupt Status Register. This register reads out the sta te of the 32 interrupt requests / software interrupts, regardless of enabling or classification.

Interrupt Select Registe r. This regis ter classifies e ach of the 32 interrupt requests as contributing to FIQ or IRQ.

Interrupt Enable Register. This register controls which of the 32 interrupt requests and software interrupts are enabled to contribute to FIQ or IRQ.

Interrupt Enable Clear Register. This register allows software to clear one or more bits in the Interrupt Enable register.

Software Interrupt Regis ter. The co ntents of th is register are ORed with the 32 interrupt requests from various peripheral functions.

Software Interrupt Clear Re giste r. This regis ter all ows sof tware to clear one or more bits in the Software Interrupt register.

Protection enable register. This regi ster allows limiti ng access to the VIC registers by software running in privileged mode.

Reset

Value*

RO 0 0xFFFF F000

RO 0 0xFFFF F004

RO 0 0xFFFF F008

R/W 0 0xFFFF F00C

R/W 0 0xFFFF F010

W 0 0xFFFF F014

R/W 0 0xFFFF F018

W 0 0xFFFF F01C

R/W 0 0xFFFF F020

Address

VICVectAddr

VICDefVectAddr

VICVectAddr0

VICVectAddr1 Vector address 1 register R/W 0 0xFFFF F104 VICVectAddr2 Vector address 2 register R/W 0 0xFFFF F108 VICVectAddr3 Vector address 3 register R/W 0 0xFFFF F10C VICVectAddr4 Vector address 4 register R/W 0 0xFFFF F110 VICVectAddr5 Vector address 5 register R/W 0 0xFFFF F114 VICVectAddr6 Vector address 6 register R/W 0 0xFFFF F118 VICVectAddr7 Vector address 7 register R/W 0 0xFFFF F11C VICVectAddr8 Vector address 8 register R/W 0 0xFFFF F120 VICVectAddr9 Vector address 9 register R/W 0 0xFFFF F124

Vector Address Register. When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read.

Default Vector Addres s Register. This regi ster holds the address of the Interrupt Service routine (ISR) for non-vectored IRQs.

Vector address 0 register. Vector Address Registers 0-15 hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

R/W 0 0xFFFF F030

R/W 0 0xFFFF F034

R/W 0 0xFFFF F100

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Table 40: VIC Register Map

Name Description Access

VICVectAddr10 Vector address 10 register R/W 0 0xFFFF F128 VICVectAddr11 Vector address 11 register R/W 0 0xFFFF F12C VICVectAddr12 Vector address 12 register R/W 0 0xFFFF F130 VICVectAddr13 Vector address 13 register R/W 0 0xFFFF F134 VICVectAddr14 Vector address 14 register R/W 0 0xFFFF F138 VICVectAddr15 Vector address 15 register R/W 0 0xFFFF F13C

Vector control 0 re gister. Vector Control Registers 0-15 eac h control one

VICVectCntl0

VICVectCntl1 Vector control 1 register R/W 0 0xFFFF F204 VICVectCntl2 Vector control 2 register R/W 0 0xFFFF F208 VICVectCntl3 Vector control 3 register R/W 0 0xFFFF F20C VICVectCntl4 Vector control 4 register R/W 0 0xFFFF F210 VICVectCntl5 Vector control 5 register R/W 0 0xFFFF F214 VICVectCntl6 Vector control 6 register R/W 0 0xFFFF F218 VICVectCntl7 Vector control 7 register R/W 0 0xFFFF F21C VICVectCntl8 Vector control 8 register R/W 0 0xFFFF F220

of the 16 vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest.

R/W 0 0xFFFF F200

Reset

Value*

Address

VICVectCntl9 Vector control 9 register R/W 0 0xFFFF F224 VICVectCntl10 Vector control 10 register R/W 0 0xFFFF F228 VICVectCntl11 Vector control 11 register R/W 0 0xFFFF F22C VICVectCntl12 Vector control 12 register R/W 0 0xFFFF F230 VICVectCntl13 Vector control 13 register R/W 0 0xFFFF F234 VICVectCntl14 Vector control 14 register R/W 0 0xFFFF F238 VICVectCntl15 Vector control 15 register R/W 0 0xFFFF F23C

*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.

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VIC REGISTERS

This section describes the VIC registers in the order in which they are used in the VIC logic, from those closest to the interrupt request inputs to tho se most abstracted for us e by software. For most p eople, this is also th e best order to read about the registers when learning the VIC.

Software Interrupt Register (VICSoftInt - 0xFFFFF018, Read/Write)

The contents of this register are ORed with the 32 interrupt requests from the various peripherals, before any other logic is applied.

Table 41: Software Interrupt Register (VICSoftInt - 0xFFFFF018, Read/Write)

VICSoftInt Function Reset Value

1:force the interrupt request with this bit number.

31:0

0: do not force the inte rrupt request w ith this bit nu mber. Writin g zeroes to bits in VICSof tInt has no effect, see VICSoftIntClear.

Software Interrupt Clear Register (VICSoftIntClear - 0xFFFFF01C, Write Only)

This register allows software to clear one or more bits in the Software Interrupt register, without having to first read it.

Table 42: Software Interrupt Clear Register (VICSoftIntClear - 0xFFFFF01C, Write Only)

VICSoftIntClear Function Reset Value

1: writing a 1 clears the corresponding bit in the Software Interrupt register, thus releasing

31:0

the forcing of this request. 0: writing a 0 leaves the corresponding bit in VICSoftInt unchanged.

Raw Interrupt Status Register (VICRawIntr - 0xFFFFF008, Read Only)

This register reads out the state of the 32 interrupt requests and software interrupts, regardless of enabling or classification.

Table 43: Raw Interrupt Status Register (VICRawIntr - 0xFFFFF008, Read-Only)

VICRawIntr Function Reset Value

31:0

1: the interrupt request or software interrupt with this bit number is asserted. 0: the interrupt request or software interrupt with this bit number is negated.

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Interrupt Enable Register (VICIntEnable - 0xFFFFF010, Read/Write)

This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ.

Table 44: Interrupt Enable Register (VICINtEnable - 0xFFFFF010, Read/Write)

VICIntEnable Function Reset Value

When this register is r ead, 1s indic ate in terrupt re quest s or so ftwar e interru pts th at are en abled to contribute to FIQ or IRQ.

31:0

Interrupt Enable Clear Register (VICIntEnClear - 0xFFFFF014, Write Only)

This register allows software to clear one or more bits in the Interrupt Enable register, without having to first read it.

Table 45: Software Interrupt Clear Register (VICIntEnClear - 0xFFFFF014, Write Only)

When this register is written, on es enab le interru pt reque sts or sof tware inter rupts to co ntribu te to FIQ or IRQ, zeroes have no effe ct. See the VICInt EnCle ar regis ter (Tab le 45 b elow) , for ho w to disable interrupts.

VICIntEnClear Function Reset Value

1: writing a 1 clears the corresponding bit in the Interrupt Enable register, thus disabling

31:0

interrupts for this request. 0: writing a 0 leaves the corresponding bit in VICIntEnable unchanged.

Interrupt Select Register (VICIntSelect - 0xFFFFF00C, Read/Write)

This register classifies each of the 32 interrupt requests as contributing to FIQ or IRQ.

Table 46: Interrupt Select Register (VICIntSelect - 0xFFFFF00C, Read/Write)

VICIntSelect Function Reset Value

31:0

1: the interrupt request with this bit number is assigned to the FIQ category. 0: the interrupt request with this bit number is assigned to the IRQ category.

IRQ Status Register (VICIRQStatus - 0xFFFFF000, Read Only)

This register reads out the state of those interrupt requests that are enabled and classified as IRQ. It does not differentiate between vectored and non-vectored IRQs.

Table 47: IRQ Status Register (VICIRQStatus - 0xFFFFF000, Read-Only)

VICIRQStatus Function Reset Value

31:0 1: the interrupt request with this bit number is enabled, class ifi ed as IRQ, and asserte d. 0

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FIQ Status Register (VICFIQStatus - 0xFFFFF004, Read Only)

This register reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.

Table 48: IRQ Status Register (VICFIQStatus - 0xFFFFF004, Read-Only)

VICFIQStatus Function Reset Value

31:0 1: the interrupt request with this bit number is enabled, class ifi ed as FIQ, and assert ed. 0

Vector Control Registers 0-15 (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write)

Each of these registers con trols one of the 16 vectored IRQ slots . Slot 0 has the hi ghest priori ty and slot 1 5 the lowest. N ote that disabling a vectored IRQ slot in one of the VICVectCntl registers does not disable the interrupt itself, the interrupt is simply changed to the non-vectored form.

Table 49: Vector Control Registers (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write)

VICVectCntl0-15 Function Reset Value

4:0

1: this vectored IRQ slot is enabled, and can produce a unique ISR address when its assigned interrupt request or software interrupt is enabled, classified as IRQ, and asserted.

The number of the interrupt request or software interrupt assigned to this vectored IRQ slot. As a matter of good programming practice, software should not assign the same interrupt number to more than one enabled vectored IRQ slot. But if this does occur, the lowernumbered slot will be used when the interrupt request or software interrupt is enabled, classified as IRQ, and asserted.

Vector Address Registers 0-15 (VICVectAddr0-15 - 0xFFFFF100-13C, Read/Write)

These registers hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

Table 50: Vector Address Registers (VICVectAddr0-15 - 0xFFFFF100-13C, Read/Write)

VICVectAddr0-15 Function Reset Value

When one or more in terrupt req uest or s oftware int errupt is (are) enab led, class ified as IRQ ,

31:0

asserted, and assign ed to a n e nab le d v ec tore d IR Q s lot , the value from this register for the highest-priority such slot will be provided when the IRQ service routine reads the Vector Address register (VICVectAddr).

Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write)

This register holds the address of the Interrupt Service routine (ISR) for non-vectored IRQs.

Table 51: Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write)

VICDefVectAddr Function Reset Value

31:0

When an IRQ service routin e reads the Vec tor Address register (VIC VectAddr), and no IR Q slot responds as described above, this address is returned.

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Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write )

When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read.

Table 52: Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write)

VICVectAddr Function Reset Value

If any of the inter rupt requests or software in terrupts that a re assigned to a vector ed IRQ slot is (are) enabled, classified as IRQ, and asserted, reading from this register returns the address in the Vector Addres s Regis ter for the highes t-priori ty such sl ot (lowes t-numb ered)

31:0

Protection Enable Register (VICProtection - 0xFFFFF020, Read/Write)

This one-bit register controls access to the VIC registers by software running in User mode.

such slot. Otherwise it returns the address in the Default Vector Address Register. Writing to this register does not set the value for future reads from it. Rather, this register

should be written near the end of an ISR, to update the priority hardware.

Table 53: Protection Enable Register (VICProtection - 0xFFFFF020, Read/Write)

VICProtection Function Reset Value

1: the VIC registers can only be accessed in privileged mode. 0: VIC registers can be accessed in User or privileged mode.

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INTERRUPT SOURCES

Table 54 lists the interrupt sources for each peripheral function. Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Table 54: Connection of Interrupt Sources to the Vectored Interrupt Controller

Block Flag(s) VIC Channel #

WDT Watchdog Interrupt (WDINT) 0

- Reserved for software interrupts only 1 ARM Core Embedded ICE, DbgCommRx 2 ARM Core Embedded ICE, DbgCommTx 3

TIMER0

TIMER1

Match 0 - 3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3)

Rx Line Status (RLS)

UART0

Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI)

Rx Line Status (RLS) Transmit Holding Register Empty (THRE)

UART1

Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI)

PWM0 Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8

C SI (state c h ange) 9

SPI0

SPI1

SPI Interrupt Flag (SPIF) Mode Fault (MODF)

PLL PLL Lock (PLOCK) 12

RTC

Counter Increment (RTCCIF) Alarm (RTCALF)

System Control External Interrupt 0 (EINT0) 14

System Control External Interrupt 1 (EINT1) 15 System Control External Interrupt 2 (EINT2) 16 System Control External Interrupt 3 (EINT3) 17

A/D A/D Converter 18

Reserved Reserved 19 - 31

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nVICFIQIN

VICINT

SOURCE

[31:0]

Interrupt Request, Masking, and Selection

SoftIntClear

[31:0]

SoftInt

[31:0]

RawInterrupt

[31:0]

Vector Interrupt 0

Source Enable

VectorCntl[5:0]

Vector Interrupt 1 Priority 1

IntEnableClear

[31:0]

IntEnable

[31:0]

IntSelect

[31:0]

Priority 0

VectorAddr

Priority 2

[31:0]

FIQStatus

[31:0]

IRQStatus

[31:0]

VectIRQ0

VectAddr0[31:0]

VectIRQ1 VectAddr1[31:0]

Non-vectored FIQ Interrupt Logic

FIQStatus

[31:0]

Non-vectored IRQ Interrupt Logic

Priority

Logic

IRQ

Address Select for Highest Priority Interrupt

IRQStatus

[31:0]

Interrupt Priority Logic

Hardware

NonVectIRQ

VectorAddr

[31:0]

nVICFIQ

nVICIRQ

VICVECT

ADDROUT

[31:0]

Vector Interrupt 15 Priority 14

Priority 15

VectIRQ15 VectAddr15[31:0]

VICVECTADDRIN[31:0]nVICIRQIN

Default

VectorAddr

[31:0]

Figure 19: Block Diagram of the Vectored Interrupt Controller

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SPURIOUS INTERRUPTS

Spurious interrupt s are poss ible to o ccur in th e ARM7 TDMI base d mi croco ntrolle r such as t he LPC2114 /2124/ 2212/22 14 d ue to the asynchronous interrupt handling. The asynchronous character of the interrupt processing has its roots in the interaction of the core and the VIC. If the VIC s tate i s cha nged b etween the mome nts whe n the core d etects an in terrupt and the core actual ly processes an interrupt, problems may be generated.

Real-life applicati on may experience following scenario:

1) VIC decides there is an IRQ interrupt and sends the IRQ signal to the core.

2) Core latches the IRQ st ate.

3) Processing continues for a few cycles due to pipelining.

4) Core loads IRQ address from VIC. Furthermore, It is pos sible that the VI C state ha s changed during the st ep 3. For examp le, VIC was modified so th at the interru pt

that triggered the sequence starting with step 1) is no longer pending -interrupt got disabled in the executed code. In this case, the VIC will not be able to clearly ident ify the interru pt that genera ted the int errupt re quest, and as a res ult the VIC will r eturn the default interrupt VicDefVectAddr (0x FFFF F03 4).

This potentialy disastrous chain of events can be prevented in two ways:

1. Application code sh oul d be se t up in a way t o prevent the spurious interrupt s to ev er hap pe n. Sim ple guard ing of cha nges to the VIC may not not be enough, since for example glitches on level sensitive interrupts can also cause spurious interrupts.

2. VIC default handler should be set up and tested properly.

Details and Case Studies on Spurious Interrupts

This chapter contains details that can be obtained from the official ARM website (http://www.arm.com), FAQ section under the "Technical Support" link: http://www.arm.com/support/faqip/3677.html.

What happens if an interrupt occurs as it is being disabled? Applies to: ARM7TDMI If an interrupt is received by the core durin g execution of an instructi on that disa bles interru pts, the ARM7 fam ily will still take t he

interrupt. This occurs for both IRQ and FIQ interrupts. For example, consider the follow instruction sequence:

MRS r0, cpsr ORR r0, r0, #I_Bit:OR:F_Bit ;disable IRQ and FIQ interrupts MSR cpsr_c, r0

If an IRQ interrupt is received during execution of the MSR instruction, then the behavior will be as follows:

• The IRQ interrupt is latched

• The MSR cpsr, r0 executes to completion setting both the I bit and the F bit in the CPSR

• The IRQ interrupt is taken because the core was committed to taking the interrupt exception before the I bit was set in the CPSR.

• The CPSR (with the I bit and F bit set) is moved to the SPSR_irq

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This means that, on entry to the IRQ interrupt se rvice routin e, one can see the un usual effec t that an IRQ interr upt has just b een taken while the I bi t in th e SPSR is set. In the exam ple ab ove, the F b it will also be set i n both the CPSR and SPSR. This mea ns that FIQs are disabled upon entry to the IRQ service routine, and will remain so until explicitly re-enabled. FIQs will not be reenabled automatically by the IRQ return sequence.

Although the example shows both IRQ and FIQ interrupts being disabled, similar behavior occurs when only one of the two interrupt types is being disab led. The fact that the c ore processe s the IRQ after completion of the MSR in struction whi ch disables IRQs does not norma lly ca use a pro blem, since an inter rupt arriv ing jus t one c ycle e arlier wou ld be ex pecte d to be tak en. Whe n the interrupt routine returns with an instruction like:

SUBS pc, lr, #4

the SPSR_IRQ is restored to the CPSR. The CPSR will now have the I bit and F bit set, and therefore execution will continue with all interrupts disabled.

However, this can cause problems in the following cases: Problem 1: A particular routine maybe called as an IRQ handler, or as a regular subroutine. In the latter case, the system

guarantees that IRQ s would have been disab led prior to t he routine be ing called . The routine exploits this restriction to determine how it was called (by examining th e I bit of the SPSR), and returns us ing the appropr iate instructi on. If the routine is entered due to an IRQ being receiv ed during execution of the M SR instruction which di sables IRQs, t hen the I bit in the SPSR will be set. T he routine would therefore assume that it could not have been entered via an IRQ.

Problem 2: FIQs and IR Qs are b oth disa bled by the sam e write to the CPSR. In this cas e, if a n IRQ is receiv ed during the CPSR write, FIQs will b e disabled for the ex ec uti on tim e of the IR Q handler. This may not be acceptable i n a system where FIQs m ust not be disabled for more than a few cycles.

Workaround: There are 3 suggested workarounds. Which of these is most applicable will depend upon the requirements of the particular

system.

Solution 1: Add code similar to the following at the start of the interrupt routine.

SUB lr, lr, #4 ; Adjust LR to point to return STMFD sp!, {..., lr} ; Get some free regs MRS lr, SPSR ; See if we got an interrupt while TST lr, #I_Bit ; interrupts were disabled. LDMNEFD sp!, {..., pc}^ ; If so, just return immediately.

; The interrupt will remain pending since we haven’t ; acknowledged it and will be reissued when interrupts are ; next enabled. ; Rest of interrupt routine

This code will test for the situation where the IRQ was received during a write to dis able IRQs. If this is the case, the code returns immediately - resulting in the IRQ not being acknowledged (cleared), and further IRQs being disabled.

Similar code may also be applied to the FIQ handler, in order to resolve the first issue. This is the recommended workaround, as it overcomes both problems mentioned above. However, in the case of problem two,

it does add several cycles to the maximum length of time FIQs will be disabled.

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Solution 2: Disable IRQs and FIQs using separate writes to the CPSR, eg:

MRS r0, cpsr ORR r0, r0, #I_Bit ;disable IRQs MSR cpsr_c, r0 ORR r0, r0, #F_Bit ;disable FIQs MSR cpsr_c, r0

This is the best workaround wher e the maximum time for which FIQ s are disabled is cri tical (it does no t increase this time at all). However, it does not solve problem one, and requires extra instructions at every point where IRQs and FIQs are disabled together.

Solution 3: Re-enable FIQs at the beginning of the IRQ handler. As the required state of all bits in the c field of the CPSR are known, this can be most efficiently be achieved by writing an immediate value to CPSR_c, for example:

MSR cpsr_c, #I_Bit:OR:irq_MODE ;IRQ should be disabled

;FIQ enabled ;ARM state, IRQ mode

This requires only the IRQ handler to be modified, and FIQs may be re-enabled more quickly than by using workaround 1. However, this should on ly be used if the system can guarant ee that FIQs a re never disa bled while IR Qs are enable d. It does not address problem one.

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VIC USAGE NOTES

If user’s code is runing from the on-chip RAM and an aplication uses interrupts, interrupt vectors must be re-mapped to flash address 0x0. This is nece ssary because all the except ion vectors are located at addre sses 0x0 and above. This is eas ily achieved by configuring MEMM AP registe r (locat ed in Sys tem Con trol Bloc k) to User R AM mod e. App licat ion co de shou ld be li nked s uch that at 0x4000 0000 the Interrupt Vector Tabe (IVT) will reside.

Although multiple sources can be selected (VICIntSelect) to generate FIQ request, only one interrupt service routine should be dedicated to service al l avail able/p resent FIQ reque st(s). Th erefore, i f more than one inte rrupt sour ces are cla ssifi ed as FIQ the FIQ interrupt service rout ine must read VICFIQSta tus to decide based on thi s content what to do and how to process the interrup t request. However, it is recommended that only one interrupt source should be classified as FIQ. Classifying more than on e interrupt sources as FIQ will increase the interrupt latency.

Following the completi on of the desired interrupt service routine, clea ring of the interrupt flag on the peripheral level will propagate to corresponding bits in VIC registers (VICRawIntr, VICFIQStatus and VICIRQStatus). Also, before the next interrupt can be serviced, it is necessary that write is performed into the VICVectAddr register before the return from interrupt is executed. This write will clear the respective interrupt flag in the internal interrupt priority hardware.

In order to disable the interrupt at the VIC you need to clear corresponding bit in the VICIntEnClr register, which in turn clears the related bit in the VICIntEnable registe r. T his a lso app lie s to the VICSoftInt and VICSoftIntClear in which VI CS oftIn tCle ar will clear the respective bits in VICSoftInt. For example, if VICSoftInt=0x0000 0005 and bit 0 has to be cleared, VICSoftIntClear=0x0000 0001 will acom plish this. Be fore the new cl ear operatio n on the sam e bit in VICSoftInt u sing writin g into VICSoftIntClear is performed in the future, VICSoftIntClear= 0x0000 0000 must be assi gned. Therefore writing 1 to any bit in Clear register will have one-time-effect in the destination register.

If the watchdog is enable d for interru pt on unde rflow or in vali d feed sequen ce only then there is no way of clea ring the in terr upt. The only way you could perform return from interrupt is by disabling the interrupt at the VIC(using VICIntEnClr).

Example: Assuming that UART0 and SPI0 are generating interrupt requests that are classified as vectored IRQs (UART0 being on the

higher level than SPI0), while UART1 and I setup:

VICIntSelect = 0x0000 0000(SPI0, I2C, UART1 and UART0 are IRQ => bit10, bit9, bit7 and bit6=0) VICIntEnable = 0x0000 06C0(SPI0, I2C, UART1 and UART0 are enabled interrupts => bit10, bit9, bit 7 and bit6=1) VICDefVectAddr = 0x… (holds address at what routine for servicing non-vectored IRQs (i.e. UART1 and I2C) starts) VICVectAddr0 = 0x… (holds address where UART0 IRQ service routine starts) VICVectAddr1 = 0x… (holds address where SPI0 IRQ service routine starts) VICVectCntl0 = 0x0000 0026(interrupt source with index 6 (UART0) is enabled as the one with priority 0 (the highest)) VICVectCntl1 = 0x0000 002A(interrupt source with index 10 (SPI0) is enabled as the one with priority 1)

After any of IRQ requests (SPI0, I2C, UART0 or UART1) is made, microcontroller will redirect code execution to the address specified at location 0x000 000 18. For vectored and non-vectored IRQ ’s the following instruction coul d be placed at 0x18:

LDR pc,[pc,#-0xFF0]

This instruction loads PC with the address that is present in VICVectAddr register. In case UART0 request has been made, VICVectAddr will be identical to VICVectAddr0, while in case SPI0 request has been

made value from VICVectAddr1 will be found here. If neither UART0 nor SPI0 have generated IRQ request but UART1 and/or

C were the reason, content of VICVectAddr will be identical to VICDefVectAddr.

C are generating non-vectored IRQs, the following could be one possibility for VIC

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7. PIN CONFIGURATION

LPC2114/2124 PINOUT

P0.21/PWM5/CAP1.3

P0.22/CAP0.0/MAT0.0

P0.23

P1.19/TRACEPKT3

P0.24

P1.18/TRACEPKT2

P0.25

P0.27/AIN0/CAP0.1/MAT0.1

P1.17/TRACEPKT1 P0.28/AIN1/CAP0.2/MAT0.2 P0.29/AIN2/CAP0.3/MAT0.3

P0.30/AIN3/EINT3/CAP0.0

P1.16/TRACEPKT0

18A

P1.27 / TD0

XTAL1

XTAL2

1 2 3 4 5 6 7

9 10 11 12 13 14 15 16

SSA

P1.28 / TDI 60

SSA_PLL

RESET

P1.29 / TCK

P0.20 / MAT1.3 / SSEL1 / EINT3

P0.19 / MAT1.2 / MOSI1 / CAP1.2

P0.18 / CAP1.3 / MISO1 / MAT1.3

P1.30 / TMS

V 51

P1.20/TRACESYNC P0.17/CAP1.2 /SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/RI1/EINT2

P1.21/PIPESTAT0

42 41 40 39 38 37 36 35 34 33

P0.14/DCD1/EINT1 P1.22/PIPESTAT1 P0.13/DTR1/MAT1.1 P0.12/DSR1/MAT1.0 P0.11/CTS1/CAP1.1 P1.23/PIPESTAT2 P0.10/RTS1/CAP1.0 P0.9/RxD1/PWM6/EINT3 P0.8/TxD1/PWM4

P1.31 / TRST

P0.0 / TxD0 / PWM1

P0.1 / RxD0 / PWM3 / EINT0

P0.2 / SCL / CAP0.0

P1.26 / RTCK

P1.25 / EXTIN0

P0.4 / SCK0 / CAP0.1

P0.3 / SDA / MAT0.0 / EINT1

P0.6 / MOSI0 / CAP0.2

P0.5 / MISO0 / MAT0.1

P1.24 / TRACECLK

P0.7 / SSEL0 / PWM2/ EINT2

Figure 20: LPC2114/2124 64-pin package

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PIN DESCRIPTION FOR LPC2114/2124

Pin description for LPC2114/2124 and a brief of corresponding functions are shown in the following table.

Table 55: Pin description for LPC2114/2124

Name

P0.0

P0.31

LQFP64

Pin #

Type Description

Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The

operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. Pins 26 and 31 of port 0 are not available.

I/O

Note: All Port 0 pins excluding those that can be used as A/D inputs (P0.27, P0.28, P0.29 and P0.30) are functionally 5V toleran t. If the A/D con ve rter is not used at al l, pins associated with A/ D inputs can be us ed as 5V tolerant d igital IO pi ns. See "A /D Convert er" chapt er for A/D inp ut pin voltage consideratio ns .

I/O

P0.0 TxD0 Transmitter output for UART0.

PWM1 Pulse Width Modulator output 1.

P0.1 RxD0 Receiver input for UART0.

PWM3 Pulse Width Modulator output 3.

P0.2 SCL I

P0.3 SDA I

P0.4 SCK0 Serial Clock for SPI0. SPI clock output from master or input to slave.

EINT0 External interrupt 0 input.

C clock input/output. Open drain output (for I2C compliance).

CAP0.0 Capture input for TIMER0, channel 0.

C data input/output. Open drain output (for I2C compliance).

MAT0.0 Match output for TIMER0, channel 0. EINT1 External interrupt 1 input.

CAP0.1 Capture input for TIMER0, channel 1.

I/O

P0.5 MISO0 Master In Slave Out for SPI0. Data input to SPI master or data output

from SPI slave.

MAT0.1 Match output for TIMER0, channel 1.

P0.6 MOSI0 Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave.

P0.7 SSEL0 Slave Select for SPI0. Selects the SPI interface as a slave.

P0.8 TxD1 Transmitter output for UART1.

P0.9 RxD1 Receiver input for UART1.

CAP0.2 Capture input for TIMER0, channel 2.

PWM2 Pulse Width Modulator output 2. EINT2 External interrupt 2 input.

PWM4 Pulse Width Modulator output 4.

PWM6 Pulse Width Modulator output 6. EINT3 External interrupt 3 input.

Pin Configuration 94 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 55: Pin description for LPC2114/2124

Name

LQFP64

Pin #

Type Description

P0.10 RTS1 Request to Send output for UART1.

P0.11 CTS1 Clear to Send input for UART1.

P0.12 DSR1 Data Set Ready input for UART1.

P0.13 DTR1 Data Terminal Ready output for UART1.

P0.14 DCD1 Data Carrier Detect input for UART1.

P0.15 RI1 Ring Indicator input for UART1.

P0.16 EINT0 External interrupt 0 input.

CAP1.0 Capture input for TIMER1, channel 0.

CAP1.1 Capture input for TIMER1, channel 1.

MAT1.0 Match output for TIMER1, channel 0.

MAT1.1 Match output for TIMER1, channel 1.

EINT1 External interrupt 1 input. LOW on this pine while RESET

forces on-chip boot-loader to take over control of the part after reset.

Important: LOW on pin P0.14 while RESET

take over control of the part after reset.

EINT2 External interrupt 2 input.

MAT0.2 Match output for TIMER0, channel 2. CAP0.2 Capture input for TIMER0, channel 2.

is LOW

is LOW forces on-chip boot-loader to

I/O

P0.17 CAP1.2 Capture input for TIMER1, channel 2.

SCK1 Serial Clock for SPI1. SPI clock output from master or input to slave. MAT1.2 Match output for TIMER1, channel 2.

P0.18 CAP1.3 Capture input for TIMER1, channel 3.

MISO1 Master In Slave Out for SPI1. Data input to SPI master or data output

from SPI slave.

MAT1.3 Match output for TIMER1, channel 3.

P0.19 MAT1.2 Match output for TIMER1, channel 2.

MOSI1 Master Out Slave In for SPI1. Data output from SPI master or data

input to SPI slave.

CAP1.2 Capture input for TIMER1, channel 2.

P0.20 MAT1.3 Match output for TIMER1, channel 3.

I I

P0.21 PWM5 Pulse Width Modulator output 5.

P0.22 CAP0.0 Capture input for TIMER0, channel 0.

SSEL1 Slave Select for SPI1. Selects the SPI interface as a slave. EINT3 External interrupt 3 input.

CAP1.3 Capture input for TIMER1, channel 3.

MAT0.0 Match output for TIMER0, channel 0.

Pin Configuration 95 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 55: Pin description for LPC2114/2124

Name

P1.16

P1.31

LQFP64

Pin #

3 I/O

5 I/O

9 I/O

Type Description

P0.23 General purpose bidirectional digital port only.

P0.24 General purpose bidirectional digital port only.

P0.25 General purpose bidirectional digital port only.

P0.27 AIN0 A/D converter, input 0. This analog input is always connected to its pin.

P0.28 AIN1 A/D converter, input 1. This analog input is always connected to its pin.

P0.29 AIN2 A/D converter, input 2. This analog input is always connected to its pin.

P0.30 AIN3 A/D converter, input 3. This analog input is always connected to its pin. I I

Port 1: Port 1 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the Pin Connect Block. Only pins 16 through 31 of port 1 are available.

I/O

Note: All Port 1 pins are 5V tolerant with bu ilt-in pull-u p resistor tha t sets input level to high w hen corresponding pin is used as input.

CAP0.1 Capture input for TIMER0, channel 1. MAT0.1 Match output for TIMER0, channel 1.

CAP0.2 Capture input for TIMER0, channel 2. MAT0.2 Match output for TIMER0, channel 2.

CAP0.3 Capture input for TIMER0, channel 3. MAT0.3 Match output for TIMER0, channel 3.

EINT3 External interrupt 3 input. CAP0.0 Capture input for TIMER0, channel 0.

16 O

12 O

O P1.20 TRACESYNCTrace Synchronization. S ta ndard I/O port w ith internal pul l-up. LOW on

44 O

40 O

P1.16 TRACEPKT0Trace Packet, bit 0. Standard I/O port with internal pull-up.

P1.17 TRACEPKT1Trace Packet, bit 1. Standard I/O port with internal pull-up.

P1.18 TRACEPKT2Trace Packet, bit 2. Standard I/O port with internal pull-up.

P1.19 TRACEPKT3Trace Packet, bit 3. Standard I/O port with internal pull-up.

this pin while RESET Trace port after reset.

Important: LOW on pin P1.20 while RESET

operate as a Trace port after reset.

P1.21 PIPESTAT0 Pipeline Statu s, bit 0. Standard I/O port with internal pull-up.

P1.22 PIPESTAT1 Pipeline Statu s, bit 1. Standard I/O port with internal pull-up.

is LOW enables pins P1.25:16 to operate as a

is LOW enables pins P1.25:16 to

Pin Configuration 96 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 55: Pin description for LPC2114/2124

Name

LQFP64

Pin #

36 O

32 O

28 I

64 O

60 I

56 I

52 I

Type Description

P1.23 PIPESTAT2 Pipeline Statu s, bit 2. Standard I/O port with internal pull-up.

P1.24 TRACECLK Trace Clock. Standard I/O port with internal pull-up.

P1.25 EXTIN0 External Trigger Input. Standard I/O with internal pull-up.

I/O P1.26 RTCK Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies. Bi-directional pin with inte rnal pullup. LOW on this pin while RESET LOW enables pins P1.31:26 to operate as a Debug port after reset.

Important: LOW on pin P1.26 while RESET

is LOW enables pins P1.31:26 to

operate as a Debug port after reset.

P1.27 TDO Test Data out for JTAG interface.

P1.28 TDI Test Data in for JTAG interface.

P1.29 TCK Test Clock for JTAG interface.

P1.30 TMS Test Mode Select for JTAG interface.

20 I

NC 10

P1.31 TRST

Pin not connected.

Test Reset for JTAG interface.

External Reset input: A LOW on t his pi n resets the devic e, cau sing I/ O ports and per ipheral s to

RESET

57 I

take on their default sta tes , and proc es so r exe cu tio n to be gi n at ad dres s 0. TTL wi th hy st eres is ,

5V tolerant. XTAL1 62 I Input to the oscillator circuit and internal clock generator circuits. XTAL2 61 O Output from the oscillator amplifier.

SSA

SSA_PLL

18A

6, 18, 25,

42, 50

59 I

58 I

17, 49 I 1.8V Core Power Supply: This is the power supply voltage for internal circuitry.

63 I

23, 43,

I Ground: 0V reference.

Analog Ground: 0V reference. Thi s should nomina lly be the sam e voltage as V

isolated to minimize noise and error.

PLL Analog Ground: 0V reference. This should nominally be the same voltage as V

should be isolated to minimize noise and error.

Analog 1.8V Core Power Supply: This is the power supply voltage for internal circuitry. This

should be nominall y the sa me vol tage as V18 but sh ould be isola ted to mi nimiz e nois e and error .

I 3.3V Pad Power Supply: This is the power supply voltage for the I/O ports.

Analog 3.3V Pad Power Supply: This should be nominally the same voltage as V3 but should

be isolated to mini mize nois e and error. Le ve l on th is pin i s us ed as a refe rence for AD convertor .

but should be

SS,

but

SS,

Pin Configuration 97 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

LPC2212/2214 PINOUT

P1.27/TDO

V18A

XTAL1

XTAL2

P1.28/TDI

VSSA

VSSA_PLL

P2.21/D21

P2.20/D20

RESET

P2.19/D19

P2.18/D18

P2.17/D17

P2.16/D16

P2.15/D15

P2.14/D14

VSS

P2.13/D13

P1.29/TCK

P2.12/D12

P2.11/D11

P0.20/MAT1.3/SSEL1/EINT3 P0.19/MAT1.2/MOSI1/CAP1.2

P0.18/CAP1.3/MISO1/MAT1.3

P2.10/D10

P2.9/D9

P2.8/D8

P2.7/D7

P2.6/D6

P2.5/D5

P1.30/TMS

VSS

V18

P2.4/D4

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

P2.3/D3

P2.22/D22

P0.21/PWM5/CAP1.3

P0.22/CAP0.0/MAT0.0

P1.19/TRACEPKT3

P2.26/D26/BOOT0

P1.18/TRACEPKT2

P2.27/D27/BOOT1

P0.27/AIN0/CAP0.1/MAT0.1

P1.17/TRACEPKT1

P0.28/AIN1/CAP0.2/MAT0.2

P0.29/AIN2/CAP0.3/MAT0.3

P0.30/AIN3/EINT3/CAP0.0

P1.16/TRACEPKT0

VSS

P0.23

P0.24

VSS P2.23/D23 P2.24/D24 P2.25/D25

V3A

P2.28/D28 P2.29/D29

P2.30/D30/AIN4 P2.31/D31/AIN5

P0.25

VSS

P3.29/BLS2/AIN6 P3.28/BLS3/AIN7

P3.27/WE

P3.26/CS1

P3.25/CS2 P3.24/CS3

1 2

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

23 24 25 26 27 28 29 30 31

32 33 34 35 36

V18

VSS

P3.22/A22

P3.21/A21

P3.20/A20

P3.19/A19

P1.31 / TRST

P3.23/A23/XCLK

P0.0 / TxD0 / PWM1

P3.18/A18

P3.17/A17

P0.1 / RxD0 / PWM3 / EINT0

P3.16/A16

P1.26 / RTCK

P0.2 / SCL / CAP0.0

VSS

P3.13/A13

P3.15/A15

P3.14/A14

P0.4 / SCK0 / CAP0.1

P0.3 / SDA / MAT0.0 / EINT1

P3.12/A12

P1.25 / EXTIN0

P0.5 / MISO0 / MAT0.1

Vss

P3.9/A9

P3.11/A11

P3.10/A10

P3.8/A8

P1.24 / TRACECLK

P0.6 / MOSI0 / CAP0.2

P0.7 / SSEL0 / PWM2/ EINT2

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

P3.7/A7

VSS P2.2/D2 P2.1/D1 V3 VSS P1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/RI1/EINT2 P2.0/D0 P3.30/BLS1 P3.31/BLS0 P1.21/PIPESTAT0 V3 VSS P0.14/DCD1/EINT1 P1.0/CS0 P1.1/OE P3.0/A0 P3.1/A1 P3.2/A2 P1.22/PIPESTAT1 P0.13/DTR1/MAT1.1 P0.12/DSR1/MAT1.0 P0.11/CTS1/CAP1.1 P1.23/PIPESTAT2 P3.3/A3 P3.4/A4 VSS P0.10/RTS1/CAP1.0 V3 P0.9/RxD1/PWM6/EINT3 P0.8/TxD1/PWM4 P3.5/A5 P3.6/A6

Figure 21: LPC2212/2214 144-pin package

Pin Configuration 98 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

PIN DESCRIPTION FOR LPC2212/2214

Pin description for LPC2212/2214 and a brief of corresponding functions are shown in the following table.Pin Description

Table 56: Pin description for LPC2212/2214

Name

P0.0

P0.31

LQFP144

Pin #

42,49,50,58,59

,61,68,69,75,7

6,78,83-

85,92,99,100,1

01,121-123,4-

6,8,21,23,25,3

2,33

42 O

50 I/O

Type Description

Port 0: Port 0 is a 32-bit bi-direction al I/O port with indiv idual direction con trols for each bit.

The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. Pins 26 and 31 of Port 0 are not available.

I/O

Note: All Port 0 pins excluding thos e that can be used as A/D inputs (P0.27 , P0.28, P0.29 and P0.30) are functionally 5V tolerant. If the A/D converter is not used at all, pins associated with A/D inputs can be used as 5V toleran t digital IO pins. See "A/D Conv erter" chapter for A/D input pin voltage considerations.

P0.0 TxD0 Transmitter output for UA RT0.

I/O

P0.1 RxD0 Receiver input for UART0.

P0.2 SCL I

P0.3 SDA I

PWM1 Pulse Width Modulator output 1.

PWM3 Pulse Width Modulator output 3. EINT0 External interrupt 0 input.

C clock input/output. Open drain output (for I2C compliance).

CAP0.0 Capture input for TIMER0, channel 0.

C data input/output. Open drain output (for I2C compliance).

MAT0.0 Match output for TIMER0, channel 0. EINT1 External interrupt 1 input.

I/O

O O

P0.4 SCK0 Serial Clock for SPI0. SPI clock output from master or input to

slave.

P0.5 MISO0 Master In Slave Out for SPI0. Data input to SPI master or data

P0.6 MOSI0 Master Out Slave In for SPI0. Data output from SPI master or

P0.7 SSEL0 Slave Select for SPI0. Selects the SPI inte rface as a slave.

P0.8 TxD1 Transmitter output for UA RT1.

P0.9 RxD1 Receiver input for UART1.

CAP0.1 Capture input for TIMER0, channel 1.

output from SPI slave.

MAT0.1 Match output for TIMER0, channel 1.

data input to SPI slave.

CAP0.2 Capture input for TIMER0, channel 2.

PWM2 Pulse Width Modulator output 2. EINT2 External interrupt 2 input.

PWM4 Pulse Width Modulator output 4.

PWM6 Pulse Width Modulator output 6. EINT3 External interrupt 3 input.

Pin Configuration 99 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2114/2124/2212/2214ARM-based Microc ontroller

Table 56: Pin description for LPC2212/2214

Name

LQFP144

Pin #

85 O

99 I

100

Type Description

P0.10 RTS1 Request to Send output for UART1.

P0.11 CTS1 Clear to Send input for UART1.

P0.12 DSR1 Data Set Ready input for UART1.

P0.13 DTR1 Data Terminal Ready output for UART1.

P0.14 DCD1 Data Carrier Detect input for UART1.

P0.15 RI1 Ring Indicator input for UART1.

P0.16 EINT0 External interrupt 0 input.

CAP1.0 Capture input for TIMER1, channel 0.

CAP1.1 Capture input for TIMER1, channel 1.

MAT1.0 Match output for TIMER1, channel 0.

MAT1.1 Match output for TIMER1, channel 1.

EINT1 External interrupt 1 input. LOW on this pin while RESET

forces on-chip boot-loader to take over control of the part after reset.

Important: LOW on pin P0.14 while RESET

loader to take over control of the part after reset.

EINT2 External interrupt 2 input.

MAT0.2 Match output for TIMER0, channel 2. CAP0.2 Capture input for TIMER0, channel 2.

is LOW

is LOW forces on-chip boot-

101

121

122

123

I/O

P0.17 CAP1.2 Capture input for TIMER1, channel 2.

SCK1 Serial Clock for SPI1. SPI clock output from master or input to

slave.

MAT1.2 Match output for TIMER1, channel 2.

P0.18 CAP1.3 Capture input for TIMER1, channel 3.

MISO1 Master In Slave Out for SPI1. Data input to SPI master or data

output from SPI slave.

MAT1.3 Match output for TIMER1, channel 3.

P0.19 MAT1.2 Match output for TIMER1, channel 2.

MOSI1 Master Out Slave In for SPI1. Data output from SPI master or

data input to SPI slave.

CAP1.2 Capture input for TIMER1, channel 2.

P0.20 MAT1.3 Match output for TIMER1, channel 3.

I I

P0.21 PWM5 Pulse Width Modulator output 5.

SSEL1 Slave Select for SPI1. Selects the SPI interface as a slave. EINT3 External interrupt 3 input.

CAP1.3 Capture input for TIMER1, channel 3.

Pin Configuration 100 May 03, 2004

Philips LPC2114, LPC2124, LPC2212, LPC2214 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual