Philips LPC2101, LPC2103, LPC2102 User Manual

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UM10161

Volume 1: LPC2101/02/03 User Manual

Rev. 01 — 12 January 2006 User manual

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Keywords LPC2101, LPC2102, LPC2103, ARM, ARM7, embedded, 32-bit,

microcontroller

Abstract An initial LPC2101/02/03 user manual revision

Philips Semiconductors

Volume 1 Preliminary UM

Revision history

Rev Date Description

01 20060112 Initial version

Preliminary UM

Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

User manual Rev. 01 — 12 January 2006 2

1.1 Introduction

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Chapter 1: General information

Rev. 01 — 12 January 2006 User manual

The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB, or 32 kB of embedded high speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over the Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, LPC2101/02/03 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. A blend of serial communications interfaces, ranging from multiple UARTS, SPI, and SSP to two I well suited for communication gateways and protocol converters. The superior performance also makes these devices suitable as math coprocessors. Various 32-bit and 16-bit timers, an improved 10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with up to 13 edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.

Cs, and on-chip SRAM of 2 kB/4 kB/8 kB make these devices very

1.2 Features

• 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package.

• 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program

memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.

• In-System/In-Application Programming (ISP/IAP) via on-chip boot loader software.

Single flash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms.

• EmbeddedICE RT offers real-time debugging with the on-chip RealMonitor software.

• The 10-bit A/D converter provides eight analog inputs, with conversion times as low

as 2.44 µs per channel, and dedicated result registers to minimize interrupt overhead.

• Two 32-bit timers/external event counters with combined seven capture and seven

compare channels.

• Two 16-bit timers/external event counters with combined three capture and seven

compare channels.

• Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz

clock input.

• Multiple serial interfaces including two UARTs (16C550), two Fast I

(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

• Vectored interrupt controller with configurable priorities and vector addresses.

• Up to thirty-two 5 V tolerant fast general purpose I/O pins.

• Up to 13 edge or level sensitive external interrupt pins available.

C-buses

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Volume 1 Chapter 1: Introductory information

• 70 MHz maximum CPU clock available from programmable on-chip PLL with a

possible input frequency of 10 MHz to 25 MHz and a settling time of 100 µs.

• On-chip integrated oscillator operates with an external crystal in the range from

1 MHz to 25 MHz.

• Power saving modes include Idle mode, Power-down mode, and Power-down mode

with RTC active.

• Individual enable/disable of peripheral functions as well as peripheral clock scaling for

additional power optimization.

• Processor wake-up from Power-down mode via external interrupt or RTC.

1.3 Applications

• Industrial control

• Medical systems

• Access control

• Point-of-sale

• Communication gateway

• Embedded soft modem

• General purpose applications

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1.4 Device information

Table 1: LPC2101/02/03 device information

Device Number

of pins

LPC2101 48 2 kB 8 kB 8 inputs -

LPC2102 48 4 kB 16 kB 8 inputs -

LPC2103 48 8 kB 32 kB 8 inputs UART1 with full modem

1.5 Architectural overview

The LPC2101/02/03 consist of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the ARM Peripheral Bus (APB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The LPC2101/02/03 configures the ARM7TDMI-S processor in little-endian byte order.

AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. LPC2101/02/03 peripheral functions (other than the interrupt controller) are connected to the APB bus. The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each APB peripheral is allocated a 16 kB address space within the APB address space.

On-chip SRAM

On-chip FLASH

ADC channels

Note

interface

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Volume 1 Chapter 1: Introductory information

The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block (see Section 7.4 on page 66 application requirements for the use of peripheral functions and pins.

1.6 ARM7TDMI-S processor

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

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). This must be configured by software to fit specific

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM instruction set.

• A 16-bit THUMB instruction set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.

The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S data sheet that can be found on official ARM website.

1.7 On-chip flash memory system

The LPC2101/02/03 incorporate a 8 kB, 16 kB, and 32 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways:

• using the serial built-in JTAG interface

• using In System Programming (ISP) and UART

• using In Application Programming (IAP) capabilities

The application program, using the IAP functions, may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. The entire flash memory is available for user code because the boot loader resides in a separate memory location.

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Volume 1 Chapter 1: Introductory information

The LPC2101/02/03 flash memory provides minimum of 100,000 erase/write cycles and 20 years of data-retention.

1.8 On-chip Static RAM (SRAM)

On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/02/03 provide 2/4/8 kB of static RAM respectively.

The LPC2101/02/03 SRAM is designed to be accessed as a byte-addressed memory. Word and halfword accesses to the memory ignore the alignment of the address and access the naturally-aligned value that is addressed (so a memory access ignores address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses). Therefore valid reads and writes require data accessed as halfwords to originate from addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in hexadecimal notation) and data accessed as words to originate from addresses with address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal notation). This rule applies to both off and on-chip memory usage.

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The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset.

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Volume 1 Chapter 1: Introductory information

1.9 Block diagram

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P0[31:0]

EINT2 to EINT0

3 × CAP0 4 × CAP1 3 × CAP2

3 × MAT0 4 × MAT1 3 × MAT2

4 × MAT3

AD0[7:0]

TMS

TRST

LPC2101/2102/2103

HIGH SPEED

GENERAL

PURPOSE I/O

ARM7 local bus

INTERNAL

SRAM

CONTROLLER

2 kB/4 kB/

8 kB SRAM

(1)

(1) (1)

(1)

(1) (1)

CAPTURE/COMPARE

EXTERNAL COUNTER

8 kB

BOOT ROM

MEMORY

ACCELERATOR

8 kB/16 kB/

32 kB FLASH

EXTERNAL

INTERRUPTS

TIMER 0/TIMER 1/ TIMER 2/TIMER 3

ADC

TEST/DEBUG

INTERFACE

ARM7TDMI-S

AHB BRIDGE

AHB TO APB

TDI

TCK

BRIDGE

TDO

system

clock

AMBA AHB

(Advanced High-performance Bus)

APB (ARM

peripheral bus)

XTAL2 V

XTAL1

PLL

C-BUS SERIAL

INTERFACES 0 AND 1

SPI AND SSP

SERIAL INTERFACES

UART0/UART1

RST V

SYSTEM

FUNCTIONS

VECTORED INTERRUPT

CONTROLLER

DD(3V3)

DD(1V8)

SCL0, SCL1

SDA0, SDA1

SCK0, SCK1

MOSI0, MOSI1

MISO0, MISO1

SSEL0, SSEL1

TXD0, TXD1

RXD0, RXD1

DSR1, CTS1, RTS1, DTR1 DCD1, RI1

(1)

P0[31:0]

GENERAL

PURPOSE I/O

WATCHDOG

TIMER

REAL-TIME CLOCK

SYSTEM CONTROL

002aab814

RTXC1 RTXC2 VBAT

(1) Pins shared with GPIO.

Fig 1. LPC2101/02/03 block diagram

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2.1 Memory maps

The LPC2101/02/03 incorporates several distinct memory regions, shown in the following figures. Figure 2 viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.

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Chapter 2: LPC2101/02/03 Memory addressing

Rev. 01 — 12 January 2006 User manual

shows the overall map of the entire address space from the user program

4.0 GB

3.75 GB

3.5 GB

3.0 GB 0xC000 0000

2.0 GB

8 kB ON-CHIP STATIC RAM (LPC2103)

4 kB ON-CHIP STATIC RAM (LPC2102)

1.0 GB

2 kB ON-CHIP STATIC RAM (LPC2101)

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK

RESERVED ADDRESS SPACE

0xFFFF FFFF

0xF000 0000

0xE000 0000

0x8000 0000

0x7FFF E000 0x7FFF DFFF

0x4000 2000 0x4000 1FFF

0x4000 1000 0x4000 0FFF

0x4000 0800 0x4000 07FF

0x4000 0000

RESERVED ADDRESS SPACE

0x0000 8000

32 kB ON-CHIP NON-VOLATILE MEMORY

16 kB ON-CHIP NON-VOLATILE MEMORY

8 kB ON-CHIP NON-VOLATILE MEMORY

0.0 GB

Fig 2. System memory map

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0x0000 7FFF

0x0000 4000 0x0000 3FFF 0x0000 2000 0x0000 1FFF

0x0000 0000

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Volume 1 Chapter 2: Memory map

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4.0 GB

4.0 GB - 2 MB

3.75 GB

0xFFFF FFFF

AHB PERIPHERALS

0xFFE0 0000 0xFFDF FFFF

RESERVED

0xF000 0000 0xEFFF FFFF

RESERVED

3.5 GB + 2 MB

APB PERIPHERALS

3.5 GB

AHB section is 128 x 16 kB blocks (totaling 2 MB).

APB section is 128 x 16 kB blocks (totaling 2MB).

Fig 3. Peripheral memory map

0xE020 0000 0xE01F FFFF

0xE000 0000

Figure 3, Figure 4, and Ta bl e 2 show different views of the peripheral address space. Both the AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are word aligned

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Volume 1 Chapter 2: Memory map

(to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.

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VECTORED INTERRUPT CONTROLLER

(AHB PERIPHERAL #126)

(AHB PERIPHERAL #125)

(AHB PERIPHERAL #124)

0xFFFF F000 (4G - 4K)

0xFFFF C000

0xFFFF 8000

0xFFFF 4000

0xFFFF 0000

0xFFE1 0000

(AHB PERIPHERAL #3)

0xFFE0 C000

(AHB PERIPHERAL #2)

0xFFE0 8000

(AHB PERIPHERAL #1)

0xFFE0 4000

(AHB PERIPHERAL #0)

0xFFE0 0000

Fig 4. AHB peripheral map

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Volume 1 Chapter 2: Memory map

Table 2: APB peripheries and base addresses

APB peripheral Base address Peripheral name

0 0xE000 0000 Watchdog timer

1 0xE000 4000 Timer 0

2 0xE000 8000 Timer 1

3 0xE000 C000 UART0

4 0xE001 0000 UART1

5 0xE001 4000 Not used

6 0xE001 8000 Not used

7 0xE001 C000 I

8 0xE002 0000 SPI0

9 0xE002 4000 RTC

10 0xE002 8000 GPIO

11 0xE002 C000 Pin connect block

12 0xE003 0000 Not used

13 0xE003 4000 ADC

14 - 22 0xE003 8000

23 0xE005 C000 I

24 0xE006 0000 Not used

25 0xE006 4000 Not used

26 0xE006 8000 SSP

27 0xE006 C000

28 0xE007 0000 Timer 3

29 0xE007 4000 Timer 4

30 - 126 0xE007 8000

127 0xE01F C000 System Control Block

0xE005 8000

0xE01F 8000

Not used

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2.2 LPC2101/02/03 memory re-mapping and boot block

2.2.1 Memory map concepts and operating modes

The basic concept on the LPC2101/02/03 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.

Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000 through 0x0000 001C, as shown in Ta bl e 3 Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of interrupts in the different operating modes described in Ta bl e 4 interrupts is accomplished via the Memory Mapping Control feature (Section 3.7 “

mapping control” on page 23).

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below), a small portion of the

. Re-mapping of the

Memory

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Volume 1 Chapter 2: Memory map

Table 3: ARM exception vector locations

Address Exception

0x0000 0000 Reset

0x0000 0004 Undefined Instruction

0x0000 0008 Software Interrupt

0x0000 000C Prefetch Abort (instruction fetch memory fault)

0x0000 0010 Data Abort (data access memory fault)

0x0000 0014 Reserved

0x0000 0018 IRQ

0x0000 001C FIQ

Table 4: LPC2101/02/03 memory mapping modes

Mode Activation Usage

Boot Loader mode

User Flash mode

User RAM mode

Hardware activation by any Reset

Software activation by Boot code

Software activation by User program

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Note: Identified as reserved in ARM documentation, this location is used

by the Boot Loader as the Valid User Program key. This is described in detail in Section 19.4.2 “

The Boot Loader always executes after any reset. The Boot Block interrupt vectors are mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process.

Activated by Boot Loader when a valid User Program Signature is recognized in memory and Boot Loader operation is not forced. Interrupt vectors are not re-mapped and are found in the bottom of the Flash memory.

Activated by a User Program as desired. Interrupt vectors are re-mapped to the bottom of the Static RAM.

Criterion for valid user code”.

2.2.2 Memory re-mapping

In order to allow for compatibility with future derivatives, the entire Boot Block is mapped to the top of the on-chip memory space. In this manner, the use of larger or smaller flash modules will not require changing the location of the Boot Block (which would require changing the Boot Loader code itself) or changing the mapping of the Boot Block interrupt vectors. Memory spaces other than the interrupt vectors remain in fixed locations.

Figure 5

The portion of memory that is re-mapped to allow interrupt processing in different modes includes the interrupt vector area (32 bytes) and an additional 32 bytes, for a total of 64 bytes. The re-mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typical user program in the Flash memory can place the entire FIQ handler at address 0x0000 001C without any need to consider memory boundaries. The vector contained in the SRAM, external memory, and Boot Block must contain branches to the actual interrupt handlers, or to other instructions that accomplish the branch to the interrupt handlers.

There are three reasons this configuration was chosen:

1. To give the FIQ handler in the Flash memory the advantage of not having to take a

User manual Rev. 01 — 12 January 2006 12

shows the on-chip memory mapping in the modes defined above.

memory boundary caused by the remapping into account.

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Volume 1 Chapter 2: Memory map

2. Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space.

3. To provide space to store constants for jumping beyond the range of single word branch instructions.

Re-mapped memory areas, including the interrupt vectors, continue to appear in their original location in addition to the re-mapped address.

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Details on re-mapping and examples can be found in Section 3.7 “

control” on page 23.

2.0 GB

2.0 GB - 8 kB

1.0 GB

(BOOT BLOCK INTERRUPT VECTORS)

8 kB BOOT BLOCK

RESERVED ADDRESS SPACE

ON-CHIP SRAM LPC2103: 8 kB ( 0x4000 2000 LPC2102: 4 kB (0x4000 1000) LPC2101: 2 kB (0x4000 0800)

(SRAM INTERRUPT VECTORS)

RESERVED ADDRESS SPACE

32 kB ON-CHIP FLASH MEMORY

ACTIVE INTERRUPT VECTORS

0.0 GB

FROM BOOT BLOCK

Memory mapping

0x7FFF FFFF

0x7FFF E000

0x4000 0000

0x0000 7FFF

0x0000 0000

Fig 5. Map of lower memory is showing re-mapped and re-mappable areas (LPC2103

with 32 kB Flash)

2.3 Prefetch abort and data abort exceptions

The LPC2101/02/03 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are:

• Areas of the memory map that are not implemented for a specific ARM derivative. For

the LPC2101/02/03, this is:

– Address space between on-chip Non-Volatile Memory and on-chip SRAM, labelled

"Reserved Address Space" in Figure 2 address range from 0x0000 8000 to 0x3FFF FFFF, for 16 kB Flash device this is memory address range from 0x0000 4000 to 0x3FFF FFFF, and for 8 kB Flash device this is memory address range from 0x0000 2000 to 0x3FFF FFFF.

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. For 32 kB Flash device this is memory

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Volume 1 Chapter 2: Memory map

– Address space between on-chip Static RAM and the Boot Block. Labelled

– Address space between 0x8000 0000 and 0xDFFF FFFF, labelled "Reserved

– Reserved regions of the AHB and APB spaces. See Figure 3

• Unassigned AHB peripheral spaces. See Figure 4.

• Unassigned APB peripheral spaces. See Ta bl e 2 .

For these areas, both attempted data access and instruction fetch generate an exception. In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to an AHB or APB peripheral address.

Within the address space of an existing APB peripheral, a data abort exception is not generated in response to an access to an undefined address. Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself. For example, an access to address 0xE000 D000 (an undefined address within the UART0 space) may result in an access to the register defined at address 0xE000 C000. Details of such address aliasing within a peripheral space are not defined in the LPC2101/02/03 documentation and are not a supported feature.

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"Reserved Address Space" in Figure 2 address range from 0x4000 2000 to 0x7FFF DFFF, for 4 kB SRAM device this is memory address range from 0x4000 1000 to 0x7FFF DFFF, and for 2 kB SRAM device this range is from 0x4000 0800 to 0x7FFF DFFF.

Address Space".

. For 8 kB SRAM device this is memory

Note that the ARM core stores the Prefetch Abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This prevents accidental aborts that could be caused by prefetches that occur when code is executed very close to a memory boundary.

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Chapter 3: System control block

Rev. 01 — 12 January 2006 User manual

3.1 Summary of system control block functions

The System control block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include:

• Crystal oscillator

• External interrupt inputs

• Miscellaneous system controls and status

• Memory mapping control

• PLL

• Power control

• Reset

• APB divider

• Wake-up timer

Each type of function has its own register(s) if any are required, and unneeded bits are defined as reserved in order to allow future expansion. Unrelated functions never share the same register addresses

3.2 Pin description

Ta bl e 5 shows pins that are associated with System Control block functions.

Table 5: Pin summary

Pin name Pin

X1 Input Crystal Oscillator Input - Input to the oscillator and internal clock

X2 Output Crystal Oscillator Output - Output from the oscillator amplifier

EINT0 Input External Interrupt Input 0 - An active LOW/HIGH level or

EINT1 Input External Interrupt Input 1 - See the EINT0 description above.

EINT2 Input External Interrupt Input 2 - See the EINT0 description above.

RESET

Pin description

direction

generator circuits

falling/rising edge general purpose interrupt input. This pin may be used to wake up the processor from Idle or Power-down modes.

Pin P0.16 can be selected to perform EINT0 function.

Pin P0.14 can be selected to perform EINT1 function.

Important: LOW level on pin P0.14 immediately after reset is considered as an external hardware request to start the ISP command handler. More details on ISP and Serial Boot Loader can be found in Section 19.4 on page 229

Pins P0.7 and P0.15 can be selected to perform EINT2 function.

Input External Reset input - A LOW on this pin resets the chip, causing

I/O ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000 0000.

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3.3 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

Table 6: Summary of system control registers

Name Description Access Reset

External Interrupts

EXTINT External Interrupt Flag Register R/W 0 0xE01F C140

INTWAKE Interrupt Wake-up Register R/W 0 0xE01F C144

EXTMODE External Interrupt Mode Register R/W 0 0xE01F C148

EXTPOLAR External Interrupt Polarity Register R/W 0 0xE01F C14C

Memory Mapping Control

MEMMAP Memory Mapping Control R/W 0 0xE01F C040

Phase Locked Loop

PLLCON PLL Control Register R/W 0 0xE01F C080

PLLCFG PLL Configuration Register R/W 0 0xE01F C084

PLLSTAT PLL Status Register RO 0 0xE01F C088

PLLFEED PLL Feed Register WO NA 0xE01F C08C

Power Control

PCON Power Control Register R/W 0 0xE01F C0C0

PCONP Power Control for Peripherals R/W 0x03BE 0xE01F C0C4

APB Divider

APBDIV APB Divider Control R/W 0 0xE01F C100

Reset

RSIR Reset Source Identification Register R/W 0 0xE01F C180

Code Security/Debugging

CSPR Code Security Protection Register RO 0 0xE01F C184

Syscon Miscellaneous Registers

SCS System Controls and Status R/W 0 0xE01F C1A0

value

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Address

[1]

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

3.4 Crystal oscillator

The LPC2101/02/03 onboard oscillator circuit supports external crystals in the range of 1 MHz to 25 MHz only. If the on-chip PLL system or the boot-loader is used, the input clock frequency is limited to an exclusive range of 10 MHz to 25 MHz.

The oscillator output frequency is called F referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. F and CCLK are the same value unless the PLL is running and connected. Refer to the

Section 3.8 “

The onboard oscillator in the LPC2101/02/03 can operate in one of two modes: slave mode and oscillation mode.

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Phase Locked Loop (PLL)” on page 24 for details and frequency limitations.

and the ARM processor clock frequency is

OSC

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Volume 1 Chapter 3: System control block

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (C

in Figure 6, drawing a), with an amplitude of at least 200 mVrms. The X2 pin in this

configuration can be left not connected. If slave mode is selected, the F duty cycle can range from 1 MHz to 50 MHz.

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signal of 50-50

OSC

External components and models used in oscillation mode are shown in Figure 6 drawings b and c, and in Ta b le 7 a crystal and the capacitances C fundamental mode oscillation (the fundamental frequency is represented by L, C R

). Capacitance CP in Figure 6, drawing c, represents the parallel package capacitance

and should not be larger than 7 pF. Parameters F crystal manufacturer.

Choosing an oscillation mode as an on-board oscillator mode of operation limits F clock selection to 1 MHz to 30 MHz.

LPC2101/02/03 LPC2101/02/03

X1X1 X2X2

Clock

Xtal

. Since the feedback resistance is integrated on chip, only

and CX2 need to be connected externally in case of

and

, CL, RS and CP are supplied by the

OSC

< = >

a) b) c)

Fig 6. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external

crystal model used for C

Table 7: Recommended values for C

Fundamental oscillation frequency F

OSC

1 MHz - 5 MHz 10 pF NA NA

5 MHz - 10 MHz 10 pF < 300 Ω 18 pF, 18 pF

10 MHz - 15 MHz 10 pF < 300 Ω 18 pF, 18 pF

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evaluation

X1/X2

components parameters)

Crystal load capacitance C

20 pF NA NA 30 pF < 300 Ω 58 pF, 58 pF

20 pF < 300 Ω 38 pF, 38 pF 30 pF < 300 Ω 58 pF, 58 pF

20 pF < 220 Ω 38 pF, 38 pF 30 pF < 140 Ω 58 pF, 58 pF

in oscillation mode (crystal and external

X1/X2

Maximum crystal

series resistance R

External load capacitors C

X1, CX2

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Volume 1 Chapter 3: System control block

UM10161

Table 7: Recommended values for C

in oscillation mode (crystal and external

X1/X2

components parameters)

Fundamental oscillation frequency F

OSC

Crystal load capacitance C

Maximum crystal

series resistance R

External load capacitors CX1,

15 MHz - 20 MHz 10 pF < 220 Ω 18 pF, 18 pF

20 pF < 140 Ω 38 pF, 38 pF 30 pF < 80 Ω 58 pF, 58 pF

20 MHz - 25 MHz 10 pF < 160 Ω 18 pF, 18 pF

20 pF < 90 Ω 38 pF, 38 pF 30 pF < 50 Ω 58 pF, 58 pF

25 MHz - 30 MHz 10 pF < 130 Ω 18 pF, 18 pF

20 pF < 50 Ω 38 pF, 38 pF

30 pF NA NA

selection

OSC

true

on-chip PLL used

in application?

false

ISP used for initial

code download?

false

external crystal

oscillator used?

true

CX2

false

MIN f

Fig 7. F

= 10 MHz

OSC

MAX f

= 25 MHz

OSC

mode a and/or b mode a mode b

selection algorithm

OSC

MIN f

MAX f

= 1 MHz

OSC

= 50 MHz

OSC

MIN f

MAX f

= 1 MHz

OSC

= 30 MHz

OSC

3.5 External interrupt inputs

The LPC2101/02/03 includes up to three External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as three independent interrupt signals. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.

Additionally, all 10 capture inputs can also be used as external interrupts without the option to wake up the device from Power-down mode.

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3.5.1 Register description

The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags and the EXTWAKE register contains bits that enable individual external interrupts to wake up the microcontroller from Power-down mode. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.

Table 8: External interrupt registers

Name Description Access Reset

EXTINT The External Interrupt Flag Register contains

EXTWAKE The Interrupt wake-up register contains four

EXTMODE The External Interrupt Mode Register controls

EXTPOLAR The External Interrupt Polarity Register controls

interrupt flags for EINT0, EINT1, EINT2 and EINT3. See Ta bl e 9

enable bits that control whether each external interrupt will cause the processor to wake up from Power-down mode. See Ta b l e 1 0

whether each pin is edge- or level sensitive.

which level or edge on each pin will cause an interrupt.

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Address

[1]

value

R/W 0 0xE01F C140

R/W 0 0xE01F C144

R/W 0 0xE01F C148

R/W 0 0xE01F C14C

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

3.5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)

When a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in this register. This asserts the corresponding interrupt request to the VIC, which will cause an interrupt if interrupts from the pin are enabled.

Writing ones to bits EINT0 through EINT2 in EXTINT register clears the corresponding bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive state.

Once a bit from EINT0 to EINT2 is set and an appropriate code starts to execute (handling wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise the event that was just triggered by activity on the EINT pin will not be recognized in the future.

Important: whenever a change of external interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in the EXTINT register must be cleared! For details see Section

3.5.4 “External Interrupt Mode register (EXTMODE - 0xE01F C148)” and Section 3.5.5 “External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”.

For example, if a system wakes up from power-down using a LOW level on external interrupt 0 pin, its post-wake-up code must reset the EINT0 bit in order to allow future entry into the power-down mode. If the EINT0 bit is left set to 1, subsequent attempt(s) to invoke power-down mode will fail. The same goes for external interrupt handling.

More details on power-down mode will be discussed in the following chapters.

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Table 9: External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description

Bit Symbol Description Reset

0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT0 is selected to be LOW level sensitive and a LOW level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes HIGH).

1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT1 is selected to be LOW level sensitive and a LOW level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes HIGH).

2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in

its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT2 is selected to be LOW level sensitive and a LOW level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes HIGH).

7:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved

bit is not defined.

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value

3.5.3 Interrupt Wake-up register (INTWAKE - 0xE01F C144)

Enable bits in the INTWAKE register allow the external interrupts and other sources to wake up the processor if it is in Power-down mode. The related EINTn function must be mapped to the pin in order for the wake-up process to take place. It is not necessary for the interrupt to be enabled in the Vectored Interrupt Controller for a wake-up to take place. This arrangement allows additional capabilities, such as having an external interrupt input wake up the processor from Power-down mode without causing an interrupt (simply resuming operation), or allowing an interrupt to be enabled during Power-down without waking the processor up if it is asserted (eliminating the need to disable the interrupt if the wake-up feature is not desirable in the application).

For an external interrupt pin to be a source that would wake up the microcontroller from Power-down mode, it is also necessary to clear the corresponding bit in the External Interrupt Flag register (see Section 3.5.2 on page 19

Table 10: Interrupt Wake-up register (INTWAKE - address 0xE01F C144) bit description

Bit Symbol Description Reset

0 EXTWAKE0 When one, assertion of EINT0 will wake up the processor from

Power-down mode.

1 EXTWAKE1 When one, assertion of EINT1 will wake up the processor from

Power-down mode.

value

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Table 10: Interrupt Wake-up register (INTWAKE - address 0xE01F C144) bit description

Bit Symbol Description Reset

2 EXTWAKE2 When one, assertion of EINT2 will wake up the processor from

14:3 - Reserved, user software should not write ones to reserved bits.

15 RTCWAKE When one, assertion of an RTC interrupt will wake up the

3.5.4 External Interrupt Mode register (EXTMODE - 0xE01F C148)

The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function (see Section7.4 on page66 VICIntEnable register (see Section 5.4.4 on page 48 External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions).

Note: Software should only change a bit in this register when its interrupt is disabled in the VICIntEnable register, and should write the corresponding 1 to the EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear the EXTINT bit that could be set by changing the mode.

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value

Power-down mode.

The value read from a reserved bit is not defined.

processor from Power-down mode.

) and enabled via the

) can cause interrupts from the

Table 11: External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit

description

Bit Symbol Valu e Description Reset

0 EXTMODE0 0 Level-sensitivity is selected for EINT0. 0

1 EINT0 is edge sensitive.

1 EXTMODE1 0 Level-sensitivity is selected for EINT1. 0

1 EINT1 is edge sensitive.

2 EXTMODE2 0 Level-sensitivity is selected for EINT2. 0

1 EINT2 is edge sensitive.

7:3 - - Reserved, user software should not write ones to reserved

bits. The value read from a reserved bit is not defined.

3.5.5 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)

In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function (see Section 7.4

on page 66) and enabled in the VICIntEnable register (see Section 5.4.4 on page 48) can

cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions).

value

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Table 12: External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit

Bit Symbol Va lue Description Reset

0 EXTPOLAR0 0 EINT0 is low-active or falling-edge sensitive (depending on

1 EXTPOLAR1 0 EINT1 is low-active or falling-edge sensitive (depending on

2 EXTPOLAR2 0 EINT2 is low-active or falling-edge sensitive (depending on

7:3 - - Reserved, user software should not write ones to reserved

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description

value

EXTMODE0).

1 EINT0 is high-active or rising-edge sensitive (depending on

EXTMODE0).

EXTMODE1).

1 EINT1 is high-active or rising-edge sensitive (depending on

EXTMODE1).

EXTMODE2).

1 EINT2 is high-active or rising-edge sensitive (depending on

EXTMODE2).

bits. The value read from a reserved bit is not defined.

EINTi

EXTPOLARi

EXTMODEi

APB Bus Data

GLITCH

FILTER

write 1 to EXTINTi

reset

wakeup enable

(one bit of EXTWAKE)

D Q

PCLK

(one bit of EXTINT)

APB Read of EXTWAKE

EINTi to wakeup

timer

interrupt flag

PCLK

to VIC

APB read of EXTINT

(1) See Figure 10 “Reset block diagram including the wake-up timer” on page 35

Fig 8. External interrupt logic

3.6 Other system controls

Some aspects of controlling LPC2101/02/03 operation that do not fit into peripheral or other registers are grouped here.

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3.6.1 System Control and Status flags register (SCS - 0xE01F C1A0)

Table 13: System Control and Status flags register (SCS - address 0xE01F C1A0) bit description

Bit Symbol Valu e Description Reset

value

0 GPIO0M GPIO port 0 mode selection. 0

0 GPIO port 0 is accessed via APB addresses in a fashion compatible with previous

LCP2000 devices.

1 High speed GPIO is enabled on GPIO port 0, accessed via addresses in the on-chip

memory range. This mode includes the port masking feature described in the GPIO chapter on page Section 8.4.2 “

FIO0MASK - 0x3FFF C010)” on page 74.

31:1 - Reserved, user software should not write ones to reserved bits. The value read from

a reserved bit is not defined.

Fast GPIO port 0 Mask register (FIOMASK, Port 0:

3.7 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. This allows code running in different memory spaces to have control of the interrupts.

3.7.1 Memory Mapping control register (MEMMAP - 0xE01F C040)

Whenever an exception handling is necessary, the microcontroller will fetch an instruction residing on the exception corresponding address as described in Table 3 “

vector locations” on page 12. The MEMMAP register determines the source of data that

will fill this table.

Table 14: Memory Mapping control register (MEMMAP - address 0xE01F C040) bit

description

Bit Symbol Value Description Reset

1:0 MAP 00 Boot Loader Mode. Interrupt vectors are re-mapped to Boot

01 User Flash Mode. Interrupt vectors are not re-mapped and

10 User RAM Mode. Interrupt vectors are re-mapped to Static

11 Reserved. Do not use this option.

Warning: Improper setting of this value may result in incorrect operation of the device.

7:2 - - Reserved, user software should not write ones to reserved

Block.

reside in Flash.

RAM.

bits. The value read from a reserved bit is not defined.

ARM exception

3.7.2 Memory mapping control usage notes

value

The Memory Mapping Control simply selects one out of three available sources of data (sets of 64 bytes each) necessary for handling ARM exceptions (interrupts).

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For example, whenever a Software Interrupt request is generated, the ARM core will always fetch 32-bit data "residing" on 0x0000 0008 see Table 3 “

locations” on page 12. This means that when MEMMAP[1:0]=10 (User RAM Mode), a

read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of MEMMAP[1:0]=00 (Boot Loader Mode), a read/fetch from 0x0000 0008 will provide data available also at 0x7FFF E008 (Boot Block remapped from on-chip Bootloader).

3.8 Phase Locked Loop (PLL)

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 10 MHz to 60 MHz using a Current Controlled Oscillators (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on the LPC2104/05/06 due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle. A block diagram of the PLL is shown in Figure 9

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ARM exception vector

PLL activation is controlled via the PLLCON register. The PLL multiplier and divider values are controlled by the PLLCFG register. These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all chip operations, including the watchdog timer, are dependent on the PLL when it is providing the chip clock, accidental changes to the PLL setup could result in unexpected behavior of the microcontroller. The protection is accomplished by a feed sequence similar to that of the watchdog timer. Details are provided in the description of the PLLFEED register.

The PLL is turned off and bypassed following a chip Reset and when by entering Power-down mode. The PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.

3.8.1 Register description

The PLL is controlled by the registers shown in Ta bl e 1 5 . More detailed descriptions follow.

Warning: Improper setting of the PLL values may result in incorrect operation of the device!

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Table 15: PLL registers

Generic name

PLLCON PLL Control Register. Holding register for

PLLCFG PLL Configuration Register. Holding register

PLLSTAT PLL Status Register. Read-back register for

PLLFEED PLL Feed Register. This register enables

UM10161

Description Access Reset

value

R/W 0 0xE01F C080 updating PLL control bits. Values written to this register do not take effect until a valid PLL feed sequence has taken place.

R/W 0 0xE01F C084 for updating PLL configuration values. Values written to this register do not take effect until a valid PLL feed sequence has taken place.

RO 0 0xE01F C088 PLL control and configuration information. If PLLCON or PLLCFG have been written to, but a PLL feed sequence has not yet occurred, they will not reflect the current PLL state. Reading this register provides the actual values controlling the PLL, as well as the status of the PLL.

WO NA 0xE01F C08C loading of the PLL control and configuration information from the PLLCON and PLLCFG registers into the shadow registers that actually affect PLL operation.

Address

[1]

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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PLLC

direct

PSEL[1:0]

UM10161

CLOCK

SYNCHRONIZATION

PLLE

OSC

PLOCK

MSEL[4:0]

Fig 9. PLL block diagram

bypass

PHASE-

FREQUENCY

DETECTOR

OUT

DIV-BY-M

MSEL<4:0>

CCO

/2P

CCLK

3.8.2 PLL Control register (PLLCON - 0xE01F C080)

The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting the PLL causes the processor and all chip functions to run from the PLL output clock. Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given (see Section 3.8.7 “

0xE01F C08C)” and Section 3.8.3 “PLL Configuration register (PLLCFG - 0xE01F C084)” on page 27).

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PLL Feed register (PLLFEED -

Philips Semiconductors

Volume 1 Chapter 3: System control block

Table 16: PLL Control register (PLLCON - address 0xE01F C080) bit description

Bit Symbol Description Reset

0 PLLE PLL Enable. When one, and after a valid PLL feed, this bit will

1 PLLC PLL Connect. When PLLC and PLLE are both set to one, and after a

7:2 - Reserved, user software should not write ones to reserved bits. The

The PLL must be set up, enabled, and Lock established before it may be used as a clock source. When switching from the oscillator clock to the PLL output or vice versa, internal circuitry synchronizes the operation in order to ensure that glitches are not generated. Hardware does not insure that the PLL is locked before it is connected or automatically disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is likely that the oscillator clock has become unstable and disconnecting the PLL will not remedy the situation.

UM10161

activate the PLL and allow it to lock to the requested frequency. See PLLSTAT register, Ta bl e 1 8

valid PLL feed, connects the PLL as the clock source for the microcontroller. Otherwise, the oscillator clock is used directly by the microcontroller. See PLLSTAT register, Ta b l e 1 8

value read from a reserved bit is not defined.

value

3.8.3 PLL Configuration register (PLLCFG - 0xE01F C084)

The PLLCFG register contains the PLL multiplier and divider values. Changes to the PLLCFG register do not take effect until a correct PLL feed sequence has been given (see

Section 3.8.7 “

for the PLL frequency, and multiplier and divider values are found in the PLL Frequency Calculation section on Section 3.8.9 “

Table 17: PLL Configuration register (PLLCFG - address 0xE01F C084) bit description

Bit Symbol Description Reset

4:0 MSEL PLL Multiplier value. Supplies the value "M" in the PLL frequency

6:5 PSEL PLL Divider value. Supplies the value "P" in the PLL frequency

7 - Reserved, user software should not write ones to reserved bits. The

PLL Feed register (PLLFEED - 0xE01F C08C)” on page 29). Calculations

calculations.

Note: For details on selecting the right value for MSEL see Section

3.8.9 “PLL frequency calculation” on page 29.

calculations.

Note: For details on selecting the right value for PSEL see Section

3.8.9 “PLL frequency calculation” on page 29.

value read from a reserved bit is not defined.

PLL frequency calculation” on page 29.

3.8.4 PLL Status register (PLLSTAT - 0xE01F C088)

value

The read-only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred (see Section 3.8.7 “

0xE01F C08C)”).

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PLL Feed register (PLLFEED -

Philips Semiconductors

Volume 1 Chapter 3: System control block

Table 18: PLL Status register (PLLSTAT - address 0xE01F C088) bit description

Bit Symbol Description Reset

4:0 MSEL Read-back for the PLL Multiplier value. This is the value currently

6:5 PSEL Read-back for the PLL Divider value. This is the value currently

7 - Reserved, user software should not write ones to reserved bits.

8 PLLE Read-back for the PLL Enable bit. When one, the PLL is currently

9 PLLC Read-back for the PLL Connect bit. When PLLC and PLLE are both

10 PLOCK Reflects the PLL Lock status. When zero, the PLL is not locked.

15:11 - Reserved, user software should not write ones to reserved bits.

UM10161

value

used by the PLL.

The value read from a reserved bit is not defined.

0 activated. When zero, the PLL is turned off. This bit is automatically cleared when Power-down mode is activated.

0 one, the PLL is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, the PLL is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated.

0 When one, the PLL is locked onto the requested frequency.

NA The value read from a reserved bit is not defined.

3.8.5 PLL interrupt

The PLOCK bit in the PLLSTAT register is connected to the interrupt controller. This allows for software to turn on the PLL and continue with other functions without having to wait for the PLL to achieve lock. When the interrupt occurs (PLOCK = 1), the PLL may be connected, and the interrupt disabled. For details on how to enable and disable the PLL interrupt, see Section 5.4.4 “

page 48 and Section 5.4.5 “Interrupt Enable Clear register (VICIntEnClear 0xFFFF F014)” on page 49.

3.8.6 PLL modes

The combinations of PLLE and PLLC are shown in Tab l e 1 9 .

Table 19: PLL Control bit combinations

PLLC PLLE PLL Function

0 0 PLL is turned off and disconnected. The CCLK equals the unmodified clock

0 1 The PLL is active, but not yet connected. The PLL can be connected after

1 0 Same as 00 combination. This prevents the possibility of the PLL being

1 1 The PLL is active and has been connected. CCLK/system clock is sourced

Interrupt Enable register (VICIntEnable - 0xFFFF F010)” on

input.

PLOCK is asserted.

connected without also being enabled.

from the PLL.

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3.8.7 PLL Feed register (PLLFEED - 0xE01F C08C)

A correct feed sequence must be written to the PLLFEED register in order for changes to the PLLCON and PLLCFG registers to take effect. The feed sequence is:

1. Write the value 0xAA to PLLFEED.

2. Write the value 0x55 to PLLFEED.

The two writes must be in the correct sequence, and must be consecutive APB bus cycles. The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not become effective.

Table 20: PLL Feed register (PLLFEED - address 0xE01F C08C) bit description

Bit Symbol Description Reset

7:0 PLLFEED The PLL feed sequence must be written to this register in order for

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value

0x00

PLL configuration and control register changes to take effect.

3.8.8 PLL and Power-down mode

Power-down mode automatically turns off and disconnects activated PLL(s). Wake-up from Power-down mode does not automatically restore the PLL settings. This must be done in software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL can be called at the beginning of any interrupt service routine that might be called due to the wake-up. It is important not to attempt to restart the PLL by simply feeding it when execution resumes after a wake-up from Power-down mode. This would enable and connect the PLL at the same time, before PLL lock is established.

3.8.9 PLL frequency calculation

The PLL equations use the following parameters:

Table 21: Elements determining PLL’s frequency

Element Description

OSC

CCO

CCLK the PLL output frequency (also the processor clock frequency)

M PLL Multiplier value from the MSEL bits in the PLLCFG register

P PLL Divider value from the PSEL bits in the PLLCFG register

The PLL output frequency (when the PLL is both active and connected) is given by:

the frequency from the crystal oscillator/external oscillator

the frequency of the PLL current controlled oscillator

CCLK = M × F

The CCO frequency can be computed as:

= CCLK × 2 × P or F

CCO

User manual Rev. 01 — 12 January 2006 29

or CCLK = F

OSC

CCO

= F

/ (2 × P)

× M × 2 × P

OSC

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Volume 1 Chapter 3: System control block

The PLL inputs and settings must meet the following:

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• F

• CCLK is in the range of 10 MHz to F

• F

is in the range of 10 MHz to 25 MHz.

OSC

(the maximum allowed frequency for the

max

microcontroller - determined by the system microcontroller is embedded in).

is in the range of 156 MHz to 320 MHz.

CCO

3.8.10 Procedure for determining PLL settings

If a particular application uses the PLL, its configuration may be determined as follows:

1. Choose the desired processor operating frequency (CCLK). This may be based on processor throughput requirements, need to support a specific set of UART baud rates, etc. Bear in mind that peripheral devices may be running from a lower clock than the processor (see Section 3.11 “

2. Choose an oscillator frequency (F multiple of F

3. Calculate the value of M to configure the MSEL bits. M = CCLK / F the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M − 1 (see

Ta bl e 2 3

4. Find a value for P to configure the PSEL bits, such that F frequency limits. F of the values 1, 2, 4, or 8. The value written to the PSEL bits in PLLCFG is 00 for P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see Ta bl e 2 2

OSC

is calculated using the equation given above. P must have one

CCO

APB divider” on page 36).

). CCLK must be the whole (non-fractional)

OSC

Table 22: PLL Divider values

PSEL Bits (PLLCFG bits [6:5]) Value of P

00 1

01 2

10 4

11 8

. M must be in

OSC

is within its defined

CCO

Table 23: PLL Multiplier values

MSEL Bits (PLLCFG bits [4:0]) Val ue o f M

00000 1

00001 2

00010 3

00011 4

... ...

11110 31

11111 32

3.8.11 PLL configuring examples

Example: an application configuring the PLL

System design asks for F

User manual Rev. 01 — 12 January 2006 30

= 10 MHz and requires CCLK = 60 MHz.

OSC

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Based on these specifications, M = CCLK / Fosc = 60 MHz / 10 MHz = 6. Consequently, M - 1 = 5 will be written as PLLCFG[4:0].

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Value for P can be derived from P = F in range of 156 MHz to 320 MHz. Assuming the lowest allowed frequency for F

CCO

produces P = 2.67. The only solution for P that satisfies both of these requirements and is listed in Ta bl e 2 2

3.9 Power control

The LPC2101/02/03 supports two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down, and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip pins remain static. The Power-down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero.

If the RTC is running with its external 32 kHz oscillator at the time of entry into Power-down mode, operation can resume using an interrupt from the RTC (see Section

17.4.1 “RTC interrupts”).

/ (CCLK x 2), using condition that F

CCO

= 156 MHz, P = 156 MHz / (2 x 60 MHz) = 1.3. The highest F

is P = 2. Therefore, PLLCFG[6:5] = 1 will be used.

CCO

frequency criteria

CCO

must be

Entry to Power-down and Idle modes must be coordinated with program execution. Wake-up from Power-down or Idle modes via an interrupt resumes program execution in such a way that no instructions are lost, incomplete, or repeated. Wake up from Power-down mode is discussed further in Section 3.12 “

A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.

3.9.1 Register description

The Power Control function contains two registers, as shown in Ta b l e 2 4 . More detailed descriptions follow.

Wake-up timer” on page 37.

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Table 24: Power control registers

Name Description Access Reset

PCON Power Control Register. This register contains

PCONP Power Control for Peripherals Register. This

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

3.9.2 Power Control register (PCON - 0xE01F COCO)

The PCON register contains two bits. Writing a one to the corresponding bit causes entry to either the Power-down or Idle mode. If both bits are set, Power-down mode is entered.

Table 25: Power Control register (PCON - address 0xE01F COCO) bit description

Bit Symbol Description Reset

0 IDL Idle mode - when 1, this bit causes the processor clock to be stopped,

1 PD Power-down mode - when 1, this bit causes the oscillator and all

7:2 - Reserved, user software should not write ones to reserved bits. The

control bits that enable the two reduced power operating modes of the microcontroller. See

Ta bl e 2 5

register contains control bits that enable and disable individual peripheral functions, Allowing elimination of power consumption by peripherals that are not needed.

while on-chip peripherals remain active. Any enabled interrupt from a peripheral or an external interrupt source will cause the processor to resume execution.

on-chip clocks to be stopped. A wake-up condition from an external interrupt can cause the oscillator to restart, the PD bit to be cleared, and the processor to resume execution.

value read from a reserved bit is not defined.

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[1]

value

R/W 0x00 0xE01F C0C0

R/W 0x0018 17BE 0xE01F C0C4

Address

value

3.9.3 Power Control for Peripherals register (PCONP - 0xE01F COC4)

The PCONP register allows turning off selected peripheral functions for the purpose of saving power. This is accomplished by gating off the clock source to the specified peripheral blocks. A few peripheral functions cannot be turned off (i.e. the watchdog timer, GPIO, the Pin Connect block, and the System Control block). Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Each bit in PCONP controls one of the peripherals. The bit numbers correspond to the related peripheral number as shown in the APB peripheral map Table 2 “

maps” on page 8.

If a peripheral control bit is 1, that peripheral is enabled. If a peripheral bit is 0, that peripheral is disabled to conserve power. For example if bit 19 is 1, the I enabled. If bit 19 is 0, the I

Important: valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register!

User manual Rev. 01 — 12 January 2006 32

APB peripheries and base addresses” in Section 2.1 “Memory

C1 interface is disabled.

C1 interface is

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Volume 1 Chapter 3: System control block

Table 26: Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit

Bit Symbol Description Reset

0 - Reserved, user software should not write ones to reserved bits. The

1 PCTIM0 Timer/Counter 0 power/clock control bit. 1

2 PCTIM1 Timer/Counter 1 power/clock control bit. 1

3 PCUART0 UART0 power/clock control bit. 1

4 PCUART1 UART1 power/clock control bit. 1

6:5 - Reserved, user software should not write ones to reserved bits. The

7PCI2C0The I

8 PCSPI The SPI interface power/clock control bit. 1

9 PCRTC The RTC power/clock control bit. 1

10 PCSPI The SSP interface power/clock control bit. 1

11 - Reserved, user software should not write ones to reserved bits. The

12 PCAD A/D converter 0 (ADC0) power/clock control bit.

18:13 - Reserved, user software should not write ones to reserved bits. The

19 PCI2C1 The I

27:20 - Reserved, user software should not write ones to reserved bits. The

28 PCTIM2 The Timer/Counter 2 power/clock control bit. 1

29 PCTIM3 The Timer/Counter3 power/clock control bit. 1

31:30 - Reserved, user software should not write ones to reserved bits. The

description

value read from a reserved bit is not defined.

Note: Clear the PDN bit in the ADCR before clearing this bit, and set this bit before setting PDN.

value read from a reserved bit is not defined.

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C0 interface power/clock control bit. 1

C1 interface power/clock control bit. 1

value

3.9.4 Power control usage notes

After every reset, the PCONP register contains the value that enables all interfaces and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, the user’s application has no need to access the PCONP in order to start using any of the on-board peripherals.

Power saving oriented systems should have 1’s in the PCONP register only in positions that match peripherals really used in the application. All other bits, declared to be "Reserved" or dedicated to the peripherals not used in the current application, must be cleared to 0.

3.10 Reset

Reset has two sources on the LPC2101/02/03: the RESET pin and watchdog reset. The RESET Reset by any source starts the wake-up timer (see description in Section 3.12 “

User manual Rev. 01 — 12 January 2006 33

pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip

Wake-up

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Volume 1 Chapter 3: System control block

timer” in this chapter), causing reset to remain asserted until the external Reset is

de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip circuitry has completed its initialization. The relationship between Reset, the oscillator, and the wake-up timer are shown in Figure 10

The Reset glitch filter allows the processor to ignore external reset pulses that are very short, and also determines the minimum duration of RESET order to guarantee a chip reset. Once asserted, RESET crystal oscillator is fully running and an adequate signal is present on the X1 pin of the microcontroller. Assuming that an external crystal is used in the crystal oscillator subsystem, after power on, the RESET subsequent resets when crystal oscillator is already running and stable signal is on the X1 pin, the RESET

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

External and internal Resets have some small differences. An external Reset causes the value of certain pins to be latched to configure the part. External circuitry cannot determine when an internal Reset occurs in order to allow setting up those special pins, so those latches are not reloaded during an internal Reset. Pin 26 (RTCK) is examined during an external Reset (see Section 6.2 on page 61 P0.14 (see Section 19.4 on page 229 code is executed after every Reset.

It is possible for a chip Reset to occur during a Flash programming or erase operation. The Flash memory will interrupt the ongoing operation and hold off the completion of Reset to the CPU until internal Flash high voltages have settled.

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that must be asserted in

pin can be deasserted only when

pin should be asserted for 10 ms. For all

pin needs to be asserted for 300 ns only.

and Section 7.4 on page 66). Pin

) is examined by the on-chip bootloader when this

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external

reset

watchdog

reset

power

down

EINT0 wake-up EINT1 wake-up EINT2 wake-up

oscillator

output (F

OSC

)

PLL

Fig 10. Reset block diagram including the wake-up timer

reset to the on-chip circuitry

reset to PCON.PD

WAKE-UP TIMER

START

COUNT 2

write “1”

from APB

Reset

ABP read of PDBIT in PCON

OSC

to CPU

3.10.1 Reset Source Identification Register (RSIR - 0xE01F C180)

This register contains one bit for each source of Reset. Writing a 1 to any of these bits clears the corresponding read-side bit to 0. The interactions among the four sources are described below.

Table 27: Reset Source identification Register (RSIR - address 0xE01F C180) bit description

Bit Symbol Description Reset

0 POR Power-On Reset (POR) event sets this bit, and clears all of the other bits

in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset.

1 EXTR Assertion of the RESET signal sets this bit. This bit is cleared by POR,

but is not affected by WDT reset.

2 WDTR This bit is set when the watchdog timer times out and the WDTRESET

bit in the Watchdog Mode Register is 1. It is cleared by any of the other sources of Reset.

7:3 - Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

value

see text

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3.11 APB divider

The APB Divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB Divider serves two purposes.

The first is to provides peripherals with desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to one half or one fourth of the processor clock rate. Because the APB bus must work properly at power up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus to run at one quarter speed.

The second purpose of the APB Divider is to allow power savings when an application does not require any peripherals to run at the full processor rate.

The connection of the APB Divider relative to the oscillator and the processor clock is shown in Figure 11 remains active (if it was running) during Idle mode.

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. Because the APB Divider is connected to the PLL output, the PLL

3.11.1 Register description

Only one register is used to control the APB Divider.

Table 28: APB divider register map

Name Description Access Reset

APBDIV Controls the rate of the APB clock in relation to

the processor clock.

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

3.11.2 APBDIV register (APBDIV - 0xE01F C100)

The APB Divider register contains two bits, allowing three divider values, as shown in

Ta bl e 2 9

Table 29: APB Divider register (APBDIV - address 0xE01F C100) bit description

Bit Symbol Val ue Description Reset

1:0 APBDIV 00 APB bus clock is one fourth of the processor clock. 00

7:2 - - Reserved, user software should not write ones to reserved

01 APB bus clock is the same as the processor clock.

10 APB bus clock is one half of the processor clock.

11 Reserved. If this value is written to the APBDIV register, it

has no effect (the previous setting is retained).

bits. The value read from a reserved bit is not defined.

Address

[1]

value

R/W 0x00 0xE01F C100

value

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Fig 11. APB divider connections

3.12 Wake-up timer

The purpose of the wake-up timer is to ensure that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.

crystal oscillator or

external clock source

)

OSC

PLL0

processor clock

(CCLK)

APB DIVIDER

ramp (in the case of power on), the type of crystal

APB clock

(PCLK)

Once a clock is detected, the wake-up timer counts 4096 clocks, then enables the on-chip circuitry to initialize. When the onboard modules initialization is complete, the processor is released to execute instructions if the external Reset has been deasserted. In the case where an external clock source is used in the system (as opposed to a crystal connected to the oscillator pins), the possibility that there could be little or no delay for oscillator start-up must be considered. The wake-up timer design then ensures that any other required chip functions will be operational prior to the beginning of program execution.

Any of the various Resets can bring the microcontroller out of Power-down mode, as can the external interrupts EINT2:0 and the RTC interrupt if the RTC is operating from its own oscillator on the RTCX1-2 pins. When one of these interrupts is enabled for wake-up and its selected event occurs, an oscillator wake-up cycle is started. The actual interrupt (if any) occurs after the wake-up timer expires, and is handled by the Vectored Interrupt Controller.

However, the pin multiplexing on the LPC2101/02/03 (see Section6.2 on page61

Section 7.4 on page 66

Power-down mode. The pin-function pairing allows interrupts from events relating to RI1 / EINT2.

User manual Rev. 01 — 12 January 2006 37

) was designed to allow other peripherals to bring the device out of

and

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To put the device in Power-down mode and allow activity on one or more of these buses or lines to power it back up, software should reprogram the pin function to External Interrupt, select the appropriate mode and polarity for the interrupt, and then select Power-down mode. Upon wake-up software should restore the pin multiplexing to the peripheral function.

To summarize: on the LPC2101/02/03, the wake-up timer enforces a minimum reset duration based on the crystal oscillator, and is activated whenever there is a wake-up from Power-down mode or any type of Reset.

3.13 Code security vs. debugging

Applications in development typically need the debugging and tracing facilities in the LPC2101/02/03. Later in the life cycle of an application, it may be more important to protect the application code from observation by hostile or competitive eyes. The following feature of the LPC2101/02/03 allows an application to control whether it can be debugged or protected from observation.

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Details on the way Code Read Protection works can be found in Section 19.7 “

Protection (CRP)” on page 235.

Code Read

User manual Rev. 01 — 12 January 2006 38

4.1 Introduction

4.2 Operation

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Chapter 4: Memory Acceleration Module (MAM)

Rev. 01 — 12 January 2006 User manual

The MAM block in the LPC2101/02/03 maximizes the performance of the ARM processor when it is running code in flash memory using a single flash bank.

Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM instruction that will be needed in its latches in time to prevent CPU fetch stalls. The LPC2101/02/03 uses one bank of Flash memory, compared to the two banks used on predecessor devices. It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer and the Data Buffer. When an Instruction Fetch is not satisfied by either the Prefetch or Branch Trail buffer, nor has a prefetch been initiated for that line, the ARM is stalled while a fetch is initiated for the 128-bit line. If a prefetch has been initiated but not yet completed, the ARM is stalled for a shorter time. Unless aborted by a data access, a prefetch is initiated as soon as the Flash has completed the previous access. The prefetched line is latched by the Flash module, but the MAM does not capture the line in its prefetch buffer until the ARM core presents the address from which the prefetch has been made. If the core presents a different address from the one from which the prefetch has been made, the prefetched line is discarded.

The Prefetch and Branch Trail Buffers each include four 32-bit ARM instructions or eight 16-bit Thumb instructions. During sequential code execution, typically the prefetch buffer contains the current instruction and the entire Flash line that contains it.

The MAM uses the LPROT[0] line to differentiate between instruction and data accesses. Code and data accesses use separate 128-bit buffers. 3 of every 4 sequential 32-bit code or data accesses "hit" in the buffer without requiring a Flash access (7 of 8 sequential 16-bit accesses, 15 of every 16 sequential byte accesses). The fourth (eighth, 16th) sequential data access must access Flash, aborting any prefetch in progress. When a Flash data access is concluded, any prefetch that had been in progress is re-initiated.

Timing of Flash read operations is programmable and is described later in this section.

In this manner, there is no code fetch penalty for sequential instruction execution when the CPU clock period is greater than or equal to one fourth of the Flash access time. The average amount of time spent doing program branches is relatively small (less than 25%) and may be minimized in ARM (rather than Thumb) code through the use of the conditional execution feature present in all ARM instructions. This conditional execution may often be used to avoid small forward branches that would otherwise be necessary.

Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above. The Branch Trail Buffer captures the line to which such a non-sequential break occurs. If the same branch is taken again, the next instruction is taken from the Branch Trail Buffer. When a branch outside the contents of the Prefetch and Branch Trail Buffer is taken, a stall of several clocks is needed to load the Branch Trail Buffer. Subsequently, there will typically be no further instruction fetch delays until a new and different branch occurs.

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4.3 MAM blocks

The Memory Accelerator Module is divided into several functional blocks:

• A Flash Address Latch and an incrementor function to form prefetch addresses

• A 128-bit Prefetch Buffer and an associated Address latch and comparator

• A 128-bit Branch Trail Buffer and an associated Address latch and comparator

• A 128-bit Data Buffer and an associated Address latch and comparator

• Control logic

• Wait logic

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Figure 12

In the following descriptions, the term “fetch” applies to an explicit Flash read request from the ARM. “Pre-fetch” is used to denote a Flash read of instructions beyond the current processor fetch address.

shows a simplified block diagram of the Memory Accelerator Module data paths.

4.3.1 Flash memory bank

There is one bank of Flash memory with the LPC2101/02/03 MAM.

Flash programming operations are not controlled by the MAM but are handled as a separate function. A “boot block” sector contains flash programming algorithms that may be called as part of the application program and a loader that may be run to allow serial programming of the flash memory.

ARM LOCAL BUS

MEMORY ADDRESS

FLASH MEMORY BANK

BUS

INTERFACE

BUFFERS

Fig 12. Simplified block diagram of the Memory Accelerator Module (MAM)

4.3.2 Instruction latches and data latches

Code and Data accesses are treated separately by the Memory Accelerator Module. There is a 128-bit Latch, a 15-bit Address

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Latch, and a 15-bit comparator associated with each buffer (prefetch, branch trail, and data). Each 128-bit latch holds 4 words (4 ARM instructions, or 8 Thumb instructions). Also associated with each buffer are 32 4:1 Multiplexers that select the requested word from the 128-bit line.

Each Data access that is not in the Data latch causes a Flash fetch of 4 words of data, which are captured in the Data latch. This speeds up sequential Data operations, but has little or no effect on random accesses.

4.3.3 Flash programming issues

Since the Flash memory does not allow accesses during programming and erase operations, it is necessary for the MAM to force the CPU to wait if a memory access to a Flash address is requested while the Flash module is busy. (This is accomplished by asserting the ARM7TDMI-S local bus signal CLKEN.) Under some conditions, this delay could result in a watchdog time-out. The user will need to be aware of this possibility and take steps to insure that an unwanted watchdog reset does not cause a system failure while programming or erasing the Flash memory.

In order to preclude the possibility of stale data being read from the Flash memory, the LPC2101/02/03 MAM holding latches are automatically invalidated at the beginning of any Flash programming or erase operation. Any subsequent read from a Flash address will cause a new fetch to be initiated after the Flash operation has completed.

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4.4 MAM operating modes

Three modes of operation are defined for the MAM, trading off performance for ease of predictability:

Mode 0: MAM off. All memory requests result in a Flash read operation (see note 2 below). There are no instruction prefetches.

Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the holding latches if the data is present. Instruction prefetch is enabled. Non-sequential instruction accesses initiate Flash read operations (see note 2 below). This means that all branches cause memory fetches. All data operations cause a Flash read because buffered data access timing is hard to predict and is very situation dependent.

Mode 2: MAM fully enabled. Any memory request (code or data) for a value that is contained in one of the corresponding holding latches is fulfilled from the latch. Instruction prefetch is enabled. Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches.

Table 30: MAM Responses to program accesses of various types

Program Memory Request Type MAM Mode

Sequential access, data in latches Initiate Fetch

Sequential access, data not in latches Initiate Fetch Initiate Fetch

Non-sequential access, data in latches Initiate Fetch

Non-sequential access, data not in latches Initiate Fetch Initiate Fetch

0 1 2

[2]

Use Latched

[1]

Data

[1]

[2]

Initiate Fetch

[1][2]

[1]

Use Latched

[1]

Data

Initiate Fetch

Use Latched

[1]

Data

Initiate Fetch

[1]

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[1] Instruction prefetch is enabled in modes 1 and 2.

[2] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This

saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock.

Table 31: MAM responses to data and DMA accesses of various types

Data Memory Request Type MAM Mode

Sequential access, data in latches Initiate Fetch

Sequential access, data not in latches Initiate Fetch Initiate Fetch Initiate Fetch

Non-sequential access, data in latches Initiate Fetch

Non-sequential access, data not in latches Initiate Fetch Initiate Fetch Initiate Fetch

[1] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This

saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock.

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0 1 2

[1]

Initiate Fetch

[1]

Initiate Fetch

[1]

Use Latched Data

4.5 MAM configuration

After reset the MAM defaults to the disabled state. Software can turn memory access acceleration on or off at any time. This allows most of an application to be run at the highest possible performance, while certain functions can be run at a somewhat slower but more predictable rate if more precise timing is required.

4.6 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

Table 32: Summary of MAM registers

Name Description Access Reset

MAMCR Memory Accelerator Module Control Register.

Determines the MAM functional mode, that is, to what extent the MAM performance enhancements are enabled. See Ta bl e 3 3 .

MAMTIM Memory Accelerator Module Timing control.

Determines the number of clocks used for Flash memory fetches (1 to 7 processor clocks).

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

Address

[1]

value

R/W 0x0 0xE01F C000

R/W 0x07 0xE01F C004

4.7 MAM Control register (MAMCR - 0xE01F C000)

Two configuration bits select the three MAM operating modes, as shown in Tab le 33 . Following Reset, MAM functions are disabled. Changing the MAM operating mode causes the MAM to invalidate all of the holding latches, resulting in new reads of Flash information as required.

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Table 33: MAM Control Register (MAMCR - address 0xE01F C000) bit description

Bit Symbol Value Description Reset

1:0 MAM_mode

_control

7:2 - - Reserved, user software should not write ones to reserved

00 MAM functions disabled 0

01 MAM functions partially enabled

10 MAM functions fully enabled

11 Reserved. Not to be used in the application.

bits. The value read from a reserved bit is not defined.

4.8 MAM Timing register (MAMTIM - 0xE01F C004)

The MAM Timing register determines how many CCLK cycles are used to access the Flash memory. This allows tuning MAM timing to match the processor operating frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash accesses would essentially remove the MAM from timing calculations. In this case the MAM mode may be selected to optimize power usage.

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value

Table 34: MAM Timing register (MAMTIM - address 0xE01F C004) bit description

Bit Symbol Value Description Reset

2:0 MAM_fetch_

cycle_timing

7:3 - - Reserved, user software should not write ones to reserved

4.9 MAM usage notes

When changing MAM timing, the MAM must first be turned off by writing a zero to MAMCR. A new value may then be written to MAMTIM. Finally, the MAM may be turned on again by writing a value (1 or 2) corresponding to the desired operating mode to MAMCR.

value

000 0 - Reserved. 07

001 1 - MAM fetch cycles are 1 processor clock (CCLK) in

010 2 - MAM fetch cycles are 2 CCLKs in duration

011 3 - MAM fetch cycles are 3 CCLKs in duration

100 4 - MAM fetch cycles are 4 CCLKs in duration

101 5 - MAM fetch cycles are 5 CCLKs in duration

110 6 - MAM fetch cycles are 6 CCLKs in duration

111 7 - MAM fetch cycles are 7 CCLKs in duration

Warning: These bits set the duration of MAM Flash fetch operations as listed here. Improper setting of this value may result in incorrect operation of the device.

duration

bits. The value read from a reserved bit is not defined.

For system clock slower than 20 MHz, MAMTIM can be 001. For system clock between 20 MHz and 40 MHz, Flash access time is suggested to be 2 CCLKs, while in systems with system clock faster than 40 MHz, 3 CCLKs are proposed.

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5.1 Features

5.2 Description

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Chapter 5: Vectored Interrupt Controller (VIC)

Rev. 01 — 12 January 2006 User manual

• ARM PrimeCell™ Vectored Interrupt Controller

• 32 interrupt request inputs

• 16 vectored IRQ interrupts

• 16 priority levels dynamically assigned to interrupt requests

• Software interrupt generation

The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and programmably assigns them into 3 categories, FIQ, vectored IRQ, and non-vectored IRQ. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.

Fast Interrupt reQuest (FIQ) requests have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority, but only 16 of the 32 requests can be assigned to this category. Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.

All registers in the VIC are word registers. Byte and halfword reads and write are not supported.

Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell™ Vectored Interrupt Controller (PL190) documentation.

5.3 Register description

The VIC implements the registers shown in Tab l e 3 5 . More detailed descriptions follow.

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Table 35: VIC register map

Name Description Access Reset

value

VICIRQStatus IRQ Status Register. This register reads out the state of

those interrupt requests that are enabled and classified as IRQ.

VICFIQStatus FIQ Status Requests. This register reads out the state of

those interrupt requests that are enabled and classified as FIQ.

VICRawIntr Raw Interrupt Status Register. This register reads out the

state of the 32 interrupt requests / software interrupts, regardless of enabling or classification.

VICIntSelect Interrupt Select Register. This register classifies each of the

32 interrupt requests as contributing to FIQ or IRQ.

VICIntEnable Interrupt Enable Register. This register controls which of the

32 interrupt requests and software interrupts are enabled to contribute to FIQ or IRQ.

VICIntEnClr Interrupt Enable Clear Register. This register allows

software to clear one or more bits in the Interrupt Enable register.

VICSoftInt Software Interrupt Register. The contents of this register are

ORed with the 32 interrupt requests from various peripheral functions.

VICSoftIntClear Software Interrupt Clear Register. This register allows

software to clear one or more bits in the Software Interrupt register.

VICProtection Protection enable register. This register allows limiting

access to the VIC registers by software running in privileged mode.

VICVectAddr Vector Address Register. When an IRQ interrupt occurs, the

IRQ service routine can read this register and jump to the value read.

VICDefVectAddr Default Vector Address Register. This register holds the

address of the Interrupt Service routine (ISR) for non-vectored IRQs.

VICVectAddr0 Vector address 0 register. Vector Address Registers 0-15

hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

VICVectAddr1 Vector address 1 register. R/W 0 0xFFFF F104

VICVectAddr2 Vector address 2 register. R/W 0 0xFFFF F108

VICVectAddr3 Vector address 3 register. R/W 0 0xFFFF F10C

VICVectAddr4 Vector address 4 register. R/W 0 0xFFFF F110

VICVectAddr5 Vector address 5 register. R/W 0 0xFFFF F114

VICVectAddr6 Vector address 6 register. R/W 0 0xFFFF F118

VICVectAddr7 Vector address 7 register. R/W 0 0xFFFF F11C

VICVectAddr8 Vector address 8 register. R/W 0 0xFFFF F120

VICVectAddr9 Vector address 9 register. R/W 0 0xFFFF F124

VICVectAddr10 Vector address 10 register. R/W 0 0xFFFF F128

VICVectAddr11 Vector address 11 register. R/W 0 0xFFFF F12C

RO 0 0xFFFF F000

RO 0 0xFFFF F004

RO 0 0xFFFF F008

R/W 0 0xFFFF F00C

R/W 0 0xFFFF F010

WO 0 0xFFFF F014

R/W 0 0xFFFF F018

WO 0 0xFFFF F01C

R/W 0 0xFFFF F020

R/W 0 0xFFFF F030

R/W 0 0xFFFF F034

R/W 0 0xFFFF F100

Address

[1]

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Table 35: VIC register map

Name Description Access Reset

value

VICVectAddr12 Vector address 12 register. R/W 0 0xFFFF F130

VICVectAddr13 Vector address 13 register. R/W 0 0xFFFF F134

VICVectAddr14 Vector address 14 register. R/W 0 0xFFFF F138

VICVectAddr15 Vector address 15 register. R/W 0 0xFFFF F13C

VICVectCntl0 Vector control 0 register. Vector Control Registers 0-15 each

control one of the 16 vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest.

VICVectCntl1 Vector control 1 register. R/W 0 0xFFFF F204

VICVectCntl2 Vector control 2 register. R/W 0 0xFFFF F208

VICVectCntl3 Vector control 3 register. R/W 0 0xFFFF F20C

VICVectCntl4 Vector control 4 register. R/W 0 0xFFFF F210

VICVectCntl5 Vector control 5 register. R/W 0 0xFFFF F214

VICVectCntl6 Vector control 6 register. R/W 0 0xFFFF F218

VICVectCntl7 Vector control 7 register. R/W 0 0xFFFF F21C

VICVectCntl8 Vector control 8 register. R/W 0 0xFFFF F220

VICVectCntl9 Vector control 9 register. R/W 0 0xFFFF F224

VICVectCntl10 Vector control 10 register. R/W 0 0xFFFF F228

VICVectCntl11 Vector control 11 register. R/W 0 0xFFFF F22C

VICVectCntl12 Vector control 12 register. R/W 0 0xFFFF F230

VICVectCntl13 Vector control 13 register. R/W 0 0xFFFF F234

VICVectCntl14 Vector control 14 register. R/W 0 0xFFFF F238

VICVectCntl15 Vector control 15 register. R/W 0 0xFFFF F23C

R/W 0 0xFFFF F200

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Address

[1]

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

5.4 VIC registers

The following section describes the VIC registers in the order in which they are used in the VIC logic, from those closest to the interrupt request inputs to those most abstracted for use by software. For most people, this is also the best order to read about the registers when learning the VIC.

5.4.1 Software Interrupt register (VICSoftInt - 0xFFFF F018)

The contents of this register are ORed with the 32 interrupt requests from the various peripherals, before any other logic is applied.

Table 36: Software Interrupt register (VICSoftInt - address 0xFFFF F018) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24

Symbol ----TIMER3TIMER2--

Access R/W R/W R/W R/W R/W R/W R/W R/W

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Bit 23 22 21 20 19 18 17 16

Symbol ----I2C1AD0-EINT2

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 37: Software Interrupt register (VICSoftInt - address 0xFFFF F018) bit description

Bit Symbol Value Description Reset value

31:0 See VICSoftInt

bit allocation table.

0 Do not force the interrupt request with this bit number. Writing

zeroes to bits in VICSoftInt has no effect, see VICSoftIntClear (Section 5.4.2

1 Force the interrupt request with this bit number.

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5.4.2 Software Interrupt Clear register (VICSoftIntClear - 0xFFFF F01C)

This register allows software to clear one or more bits in the Software Interrupt register, without having to first read it.

Table 38: Software Interrupt Clear register (VICSoftIntClear - address 0xFFFF F01C) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24

Symbol ----TIMER3TIMER2--

Access WO WO WO WO WO WO WO WO

Bit 23 22 21 20 19 18 17 16

Symbol ----I2C1AD0-EINT2

Access WO WO WO WO WO WO WO WO

Bit 15 14 13 12 11 10 9 8

Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -

Access WO WO WO WO WO WO WO WO

Bit 7 6 5 4 3 2 1 0

Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT

Access WO WO WO WO WO WO WO WO

Table 39: Software Interrupt Clear register (VICSoftIntClear - address 0xFFFF F01C) bit description

Bit Symbol Value Description Reset

31:0 See

VICSoftIntClea r bit allocation table.

0 Writing a 0 leaves the corresponding bit in VICSoftInt unchanged. 0

1 Writing a 1 clears the corresponding bit in the Software Interrupt

value

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5.4.3 Raw Interrupt status register (VICRawIntr - 0xFFFF F008)

This is a read only register. This register reads out the state of the 32 interrupt requests and software interrupts, regardless of enabling or classification.

Table 40: Raw Interrupt status register (VICRawIntr - address 0xFFFF F008) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24

Symbol ----TIMER3TIMER2--

Access RO RO RO RO RO RO RO RO

Bit 23 22 21 20 19 18 17 16

Symbol ----I2C1AD0-EINT2

Access RO RO RO RO RO RO RO RO

Bit 15 14 13 12 11 10 9 8

Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -

Access RO RO RO RO RO RO RO RO

Bit 7 6 5 4 3 2 1 0

Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT

Access RO RO RO RO RO RO RO RO

Table 41: Raw Interrupt status register (VICRawIntr - address 0xFFFF F008) bit description

Bit Symbol Valu e Description Reset

value

31:0 See

VICRawIntr bit allocation table.

0 The interrupt request or software interrupt with this bit number is

negated.

1 The interrupt request or software interrupt with this bit number is

negated.

5.4.4 Interrupt Enable register (VICIntEnable - 0xFFFF F010)

This is a read/write accessible register. This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ.

Table 42: Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24

Symbol ----TIMER3TIMER2--

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol ----I2C1AD0-EINT2

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT

Access R/W R/W R/W R/W R/W R/W R/W R/W

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Table 43: Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit description

Bit Symbol Description Reset

31:0 See

VICIntEnable bit allocation table.

When this register is read, 1s indicate interrupt requests or software interrupts that are enabled to contribute to FIQ or IRQ.

When this register is written, ones enable interrupt requests or software interrupts to contribute to FIQ or IRQ, zeroes have no effect. See Section 5.4.5

“Interrupt Enable Clear register (VICIntEnClear - 0xFFFF F014)” on page 49

and Ta bl e 45 below for how to disable interrupts.

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value

5.4.5 Interrupt Enable Clear register (VICIntEnClear - 0xFFFF F014)

This is a write only register. This register allows software to clear one or more bits in the Interrupt Enable register (see Section 5.4.4 “

0xFFFF F010)” on page 48), without having to first read it.

Table 44: Software Interrupt Clear register (VICIntEnClear - address 0xFFFF F014) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24

Symbol ----TIMER3TIMER2--

Access WO WO WO WO WO WO WO WO

Bit 23 22 21 20 19 18 17 16

Symbol ----I2C1AD0-EINT2

Access WO WO WO WO WO WO WO WO

Bit 15 14 13 12 11 10 9 8

Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -

Access WO WO WO WO WO WO WO WO

Bit 7 6 5 4 3 2 1 0

Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT

Access WO WO WO WO WO WO WO WO

Interrupt Enable register (VICIntEnable -

Table 45: Software Interrupt Clear register (VICIntEnClear - address 0xFFFF F014) bit description

Bit Symbol Val ue Description Reset

value

31:0 See

VICIntEnClear bit allocation table.

0 Writing a 0 leaves the corresponding bit in VICIntEnable

unchanged.

1 Writing a 1 clears the corresponding bit in the Interrupt Enable

5.4.6 Interrupt Select register (VICIntSelect - 0xFFFF F00C)

This is a read/write accessible register. This register classifies each of the 32 interrupt requests as contributing to FIQ or IRQ.

Table 46: Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24

Symbol ----TIMER3TIMER2--

Access R/W R/W R/W R/W R/W R/W R/W R/W

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Bit 23 22 21 20 19 18 17 16

Symbol ----I2C1AD0-EINT2

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 47: Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit description

Bit Symbol Val ue Description Reset

31:0 See

VICIntSelect bit allocation table.

0 The interrupt request with this bit number is assigned to the IRQ

category.

1 The interrupt request with this bit number is assigned to the FIQ

category.

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value

5.4.7 IRQ Status register (VICIRQStatus - 0xFFFF F000)

This is a read only register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ. It does not differentiate between vectored and non-vectored IRQs.

Table 48: IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24

Symbol ----TIMER3TIMER2--

Access RO RO RO RO RO RO RO RO

Bit 23 22 21 20 19 18 17 16

Symbol ----I2C1AD0-EINT2

Access RO RO RO RO RO RO RO RO

Bit 15 14 13 12 11 10 9 8

Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -

Access RO RO RO RO RO RO RO RO

Bit 7 6 5 4 3 2 1 0

Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT

Access RO RO RO RO RO RO RO RO

Table 49: IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit description

Bit Symbol Description Reset

31:0 See

VICIRQStatus bit allocation table.

A bit read as 1 indicates a corresponding interrupt request being enabled, classified as IRQ, and asserted

value

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5.4.8 FIQ Status register (VICFIQStatus - 0xFFFF F004)

This is a read only register. This register reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.

Table 50: FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24

Symbol ----TIMER3TIMER2--

Access RO RO RO RO RO RO RO RO

Bit 23 22 21 20 19 18 17 16

Symbol ----I2C1AD0-EINT2

Access RO RO RO RO RO RO RO RO

Bit 15 14 13 12 11 10 9 8

Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -0

Access RO RO RO RO RO RO RO RO

Bit 7 6 5 4 3 2 1 0

Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT

Access RO RO RO RO RO RO RO RO

Table 51: FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit description

Bit Symbol Description Reset

31:0 See

VICFIQStatus bit allocation table.

A bit read as 1 indicates a corresponding interrupt request being enabled, classified as FIQ, and asserted

value

5.4.9 Vector Control registers 0-15 (VICVectCntl0-15 - 0xFFFF F200-23C)

These are a read/write accessible registers. Each of these registers controls one of the 16 vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest. Note that disabling a vectored IRQ slot in one of the VICVectCntl registers does not disable the interrupt itself, the interrupt is simply changed to the non-vectored form.

Table 52: Vector Control registers 0-15 (VICVectCntl0-15 - 0xFFFF F200-23C) bit description

Bit Symbol Description Reset

value

4:0 int_request/

sw_int_assig

5 IRQslot_en When 1, this vectored IRQ slot is enabled, and can produce a unique ISR

31:6 - Reserved, user software should not write ones to reserved bits. The value read

The number of the interrupt request or software interrupt assigned to this vectored IRQ slot. As a matter of good programming practice, software should not assign the same interrupt number to more than one enabled vectored IRQ slot. But if this does occur, the lower numbered slot will be used when the interrupt request or software interrupt is enabled, classified as IRQ, and asserted.

address when its assigned interrupt request or software interrupt is enabled, classified as IRQ, and asserted.

from a reserved bit is not defined.

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5.4.10 Vector Address registers 0-15 (VICVectAddr0-15 - 0xFFFF F100-13C)

These are a read/write accessible registers. These registers hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

Table 53: Vector Address registers (VICVectAddr0-15 - addresses 0xFFFF F100-13C) bit description

Bit Symbol Description Reset value

31:0 IRQ_vector When one or more interrupt request or software interrupt is (are) enabled,

classified as IRQ, asserted, and assigned to an enabled vectored IRQ slot, the value from this register for the highest-priority such slot will be provided when the IRQ service routine reads the Vector Address register -VICVectAddr (Section 5.4.10

0x0000 0000

5.4.11 Default Vector Address register (VICDefVectAddr - 0xFFFF F034)

This is a read/write accessible register. This register holds the address of the Interrupt Service routine (ISR) for non-vectored IRQs.

Table 54: Default Vector Address register (VICDefVectAddr - address 0xFFFF F034) bit description

Bit Symbol Description Reset value

31:0 IRQ_vector When an IRQ service routine reads the Vector Address register

(VICVectAddr), and no IRQ slot responds as described above, this address is returned.

0x0000 0000

5.4.12 Vector Address register (VICVectAddr - 0xFFFF F030)

This is a read/write accessible register. When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read.

Table 55: Vector Address register (VICVectAddr - address 0xFFFF F030) bit description

Bit Symbol Description Reset value

31:0 IRQ_vector If any of the interrupt requests or software interrupts that are assigned to a

vectored IRQ slot is (are) enabled, classified as IRQ, and asserted, reading from this register returns the address in the Vector Address Register for the highest-priority such slot (lowest-numbered) such slot. Otherwise it returns the address in the Default Vector Address Register.

Writing to this register does not set the value for future reads from it. Rather, this register should be written near the end of an ISR, to update the priority hardware.

0x0000 0000

5.4.13 Protection Enable register (VICProtection - 0xFFFF F020)

This is a read/write accessible register. It controls access to the VIC registers by software running in User mode.

Table 56: Protection Enable register (VICProtection - address 0xFFFF F020) bit description

Bit Symbol Val ue Description Reset

value

0 VIC_access 0 VIC registers can be accessed in User or privileged mode. 0

1 The VIC registers can only be accessed in privileged mode.

31:1 - Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

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5.5 Interrupt sources

Ta bl e 5 7 lists the interrupt sources for each peripheral function. Each peripheral device

has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Table 57: Connection of interrupt sources to the Vectored Interrupt Controller (VIC)

Block Flag(s) VIC Channel # and Hex

Mask

WDT Watchdog Interrupt (WDINT) 0 0x0000 0001

- Reserved for Software Interrupts only 1 0x0000 0002

ARM Core Embedded ICE, DbgCommRx 2 0x0000 0004

ARM Core Embedded ICE, DbgCommTX 3 0x0000 0008

TIMER0 Match 0 - 2 (MR0, MR1, MR2)

Capture 0 - 2 (CR0, CR1, CR2)

TIMER1 Match 0 - 3 (MR0, MR1, MR2, MR3)

Capture 0 - 3 (CR0, CR1, CR2, CR3)

UART0 Rx Line Status (RLS)

Transmit Holding Register Empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

UART1 Rx Line Status (RLS)

Transmit Holding Register Empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

- Reserved 8 0x0000 0100

C0 SI (state change) 9 0x0000 0200

SPI0 SPI0 Interrupt Flag (SPI0F)

Mode Fault (MODF)

SPI1 (SSP) TX FIFO at least half empty (TXRIS)

Rx FIFO at least half full (RXRIS)

Receive Timeout condition (RTRIS)

Receive overrun (RORRIS)

PLL PLL Lock (PLOCK) 12 0x0000 1000

RTC Counter Increment (RTCCIF)

Alarm (RTCALF)

System Control External Interrupt 0 (EINT0) 14 0x0000 4000

External Interrupt 1 (EINT1) 15 0x0000 8000

External Interrupt 2 (EINT2) 16 0x0001 0000

Reserved 17 0x0002 0000

ADC A/D Converter 0 end of conversion 18 0x0004 0000

C1 SI (state change) 19 0x0008 0000

4 0x0000 0010

5 0x0000 0020

6 0x0000 0040

7 0x0000 0080

10 0x0000 0400

11 0x0000 0800

13 0x0000 2000

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Table 57: Connection of interrupt sources to the Vectored Interrupt Controller (VIC)

Block Flag(s) VIC Channel # and Hex

Mask

I- Reserved 20-250x0010 0000

0x0200 0000

TIMER2 Match 0 - 2 (MR0, MR1, MR2)

Capture 0 - 2 (CR0, CR1, CR2)

TIMER3 Match 0 - 3 (MR0, MR1, MR2, MR3) 27 0x0800 0000

26 0x0400 0000

VICINT

SOURCE

[31:0]

vector interrupt 0

SOURCE

VECTORCNTL[5:0]

interrupt request, masking and selection

SOFTINTCLEAR

[31:0]

SOFTINT

[31:0]

RAWINTERRUPT

[31:0]

ENABLE

INTENABLECLEAR

[31:0]

INTENABLE

[31:0]

INTSELECT

[31:0]

priority 0

VECTORADDR

[31:0]

VECTIRQ0

VECTADDR0[31:0]

nVICFIQIN

FIQSTATUS[31:0]

IRQSTATUS[31:0]

non-vectored FIQ interrupt logic

FIQSTATUS

[31:0]

non-vectored IRQ interrupt logic

IRQSTATUS

[31:0]

interrupt priority logic

HARDWARE

PRIORITY

LOGIC

IRQ

address select for highest priority interrupt

nVICFIQ

NonVectIRQ

nVICIRQ

vector interrupt 1

vector interrupt 15

priority1

priority2

priority14

priority15

VECTIRQ1

VECTADDR1[31:0]

VECTIRQ15

VECTADDR15[31:0]

nVICIRQIN

DEFAULT

VECTORADDR

[31:0]

VICV ECTA DDRIN[31:0]

VECTORADDR

[31:0]

VICVECT

ADDROUT

[31:0]

Fig 13. Block diagram of the Vectored Interrupt Controller (VIC)

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5.6 Spurious interrupts

Spurious interrupts are possible in the ARM7TDMI based microcontrollers such as the LPC2101/02/03 due to asynchronous interrupt handling. The asynchronous character of the interrupt processing has its roots in the interaction of the core and the VIC. If the VIC state is changed between the moments when the core detects an interrupt, and the core actually processes an interrupt, problems may be generated.

Real-life applications may experience the following scenarios:

1. VIC decides there is an IRQ interrupt and sends the IRQ signal to the core.

2. Core latches the IRQ state.

3. Processing continues for a few cycles due to pipelining.

4. Core loads IRQ address from VIC.

Furthermore, It is possible that the VIC state has changed during step 3. For example, VIC was modified so that the interrupt that triggered the sequence starting with step 1) is no longer pending -interrupt got disabled in the executed code. In this case, the VIC will not be able to clearly identify the interrupt that generated the interrupt request, and as a result the VIC will return the default interrupt VicDefVectAddr (0xFFFF F034).

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This potentially disastrous chain of events can be prevented in two ways:

1. Application code should be set up in a way to prevent the spurious interrupts from occurring. Simple guarding of changes to the VIC may not be enough since, for example, glitches on level sensitive interrupts can also cause spurious interrupts.

2. VIC default handler should be set up and tested properly.

5.6.1 Details and case studies on spurious interrupts

This chapter contains details that can be obtained from the official ARM website, FAQ section.

What happens if an interrupt occurs as it is being disabled?

Applies to: ARM7TDMI

If an interrupt is received by the core during execution of an instruction that disables interrupts, the ARM7 family will still take the interrupt. This occurs for both IRQ and FIQ interrupts.

For example, consider the following instruction sequence:

MRS r0, cpsr ORR r0, r0, #I_Bit:OR:F_Bit ;disable IRQ and FIQ interrupts MSR cpsr_c, r0

If an IRQ interrupt is received during execution of the MSR instruction, then the behavior will be as follows:

• The IRQ interrupt is latched.

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• The MSR cpsr, r0 executes to completion setting both the I bit and the F bit in the

CPSR.

• The IRQ interrupt is taken because the core was committed to taking the interrupt

exception before the I bit was set in the CPSR.

• The CPSR (with the I bit and F bit set) is moved to the SPSR_IRQ.

This means that, on entry to the IRQ interrupt service routine, you can see the unusual effect that an IRQ interrupt has just been taken while the I bit in the SPSR is set. In the example above, the F bit will also be set in both the CPSR and SPSR. This means that FIQs are disabled upon entry to the IRQ service routine, and will remain so until explicitly re-enabled. FIQs will not be reenabled automatically by the IRQ return sequence.

Although the example shows both IRQ and FIQ interrupts being disabled, similar behavior occurs when only one of the two interrupt types is being disabled. The fact that the core processes the IRQ after completion of the MSR instruction which disables IRQs does not normally cause a problem, since an interrupt arriving just one cycle earlier would be expected to be taken. When the interrupt routine returns with an instruction like:

SUBS pc, lr, #4

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the SPSR_IRQ is restored to the CPSR. The CPSR will now have the I bit and F bit set, and therefore execution will continue with all interrupts disabled. However, this can cause problems in the following cases:

Problem 1: A particular routine maybe called as an IRQ handler, or as a regular subroutine. In the latter case, the system guarantees that IRQs would have been disabled prior to the routine being called. The routine exploits this restriction to determine how it was called (by examining the I bit of the SPSR), and returns using the appropriate instruction. If the routine is entered due to an IRQ being received during execution of the MSR instruction which disables IRQs, then the I bit in the SPSR will be set. The routine would therefore assume that it could not have been entered via an IRQ.

Problem 2: FIQs and IRQs are both disabled by the same write to the CPSR. In this case, if an IRQ is received during the CPSR write, FIQs will be disabled for the execution time of the IRQ handler. This may not be acceptable in a system where FIQs must not be disabled for more than a few cycles.

5.6.2 Workaround

There are 3 suggested workarounds. Which of these is most applicable will depend upon the requirements of the particular system.

5.6.3 Solution 1: test for an IRQ received during a write to disable IRQs

Add code similar to the following at the start of the interrupt routine.

SUB lr, lr, #4 ; Adjust LR to point to return STMFD sp!, {..., lr} ; Get some free regs MRS lr, SPSR ; See if we got an interrupt while TST lr, #I_Bit ; interrupts were disabled. LDMNEFD sp!, {..., pc}^ ; If so, just return immediately. ; The interrupt will remain pending since we haven’t ; acknowledged it and will be reissued when interrupts

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; are next enabled. ; Rest of interrupt routine

This code will test for the situation where the IRQ was received during a write to disable IRQs. If this is the case, the code returns immediately - resulting in the IRQ not being acknowledged (cleared), and further IRQs being disabled.

Similar code may also be applied to the FIQ handler, in order to resolve the first issue.

This is the recommended workaround, as it overcomes both problems mentioned above. However, in the case of problem two, it does add several cycles to the maximum length of time FIQs will be disabled.

5.6.4 Solution 2: disable IRQs and FIQs using separate writes to the CPSR

MRS r0, cpsr ORR r0, r0, #I_Bit ;disable IRQs MSR cpsr_c, r0 ORR r0, r0, #F_Bit ;disable FIQs MSR cpsr_c, r0

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This is the best workaround where the maximum time for which FIQs are disabled is critical (it does not increase this time at all). However, it does not solve problem one, and requires extra instructions at every point where IRQs and FIQs are disabled together.

5.6.5 Solution 3: re-enable FIQs at the beginning of the IRQ handler

As the required state of all bits in the c field of the CPSR are known, this can be most efficiently be achieved by writing an immediate value to CPSR_C, for example:

MSR cpsr_c, #I_Bit:OR:irq_MODE ;IRQ should be disabled ;FIQ enabled ;ARM state, IRQ mode

This requires only the IRQ handler to be modified, and FIQs may be re-enabled more quickly than by using workaround 1. However, this should only be used if the system can guarantee that FIQs are never disabled while IRQs are enabled. It does not address problem one.

5.7 VIC usage notes

If user code is running from an on-chip RAM and an application uses interrupts, interrupt vectors must be re-mapped to on-chip address 0x0. This is necessary because all the exception vectors are located at addresses 0x0 and above. This is easily achieved by configuring the MEMMAP register (see Section 3.7.1 “

(MEMMAP - 0xE01F C040)” on page 23) to User RAM mode. Application code should be

linked such that at 0x4000 0000 the Interrupt Vector Table (IVT) will reside.

Memory Mapping control register

Although multiple sources can be selected (VICIntSelect) to generate FIQ request, only one interrupt service routine should be dedicated to service all available/present FIQ request(s). Therefore, if more than one interrupt sources are classified as FIQ the FIQ interrupt service routine must read VICFIQStatus to decide based on this content what to

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do and how to process the interrupt request. However, it is recommended that only one interrupt source should be classified as FIQ. Classifying more than one interrupt sources as FIQ will increase the interrupt latency.

Following the completion of the desired interrupt service routine, clearing of the interrupt flag on the peripheral level will propagate to corresponding bits in VIC registers (VICRawIntr, VICFIQStatus and VICIRQStatus). Also, before the next interrupt can be serviced, it is necessary that write is performed into the VICVectAddr register before the return from interrupt is executed. This write will clear the respective interrupt flag in the internal interrupt priority hardware.

In order to disable the interrupt at the VIC you need to clear corresponding bit in the VICIntEnClr register, which in turn clears the related bit in the VICIntEnable register. This also applies to the VICSoftInt and VICSoftIntClear in which VICSoftIntClear will clear the respective bits in VICSoftInt. For example, if VICSoftInt = 0x0000 0005 and bit 0 has to be cleared, VICSoftIntClear = 0x0000 0001 will accomplish this. Before the new clear operation on the same bit in VICSoftInt using writing into VICSoftIntClear is performed in the future, VICSoftIntClear = 0x0000 0000 must be assigned. Therefore writing 1 to any bit in Clear register will have one-time-effect in the destination register.

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If the watchdog is enabled for interrupt on underflow or invalid feed sequence only then there is no way of clearing the interrupt. The only way you could perform return from interrupt is by disabling the interrupt at the VIC (using VICIntEnClr).

Example:

Assuming that UART0 and SPI0 are generating interrupt requests that are classified as vectored IRQs (UART0 being on the higher level than SPI0), while UART1 and I generating non-vectored IRQs, the following could be one possibility for VIC setup:

VICIntSelect = 0x0000 0000 ; SPI0, I2C0, UART1 and UART0 are IRQ => ; bit10, bit9, bit7 and bit6=0 VICIntEnable = 0x0000 06C0 ; SPI0, I2C0, UART1 and UART0 are enabled interrupts

=> ; bit10, bit9, bit 7 and bit6=1 VICDefVectAddr = 0x... ; holds address at what routine for servicing ; non-vectored IRQs (i.e. UART1 and I2C) starts VICVectAddr0 = 0x... ; holds address where UART0 IRQ service routine starts VICVectAddr1 = 0x... ; holds address where SPI0 IRQ service routine starts VICVectCntl0 = 0x0000 0026 ; interrupt source with index 6 (UART0) is enabled as ; the one with priority 0 (the highest) VICVectCntl1 = 0x0000 002A ; interrupt source with index 10 (SPI0) is enabled ; as the one with priority 1

After any of IRQ requests (SPI0, I2C, UART0 or UART1) is made, microcontroller will redirect code execution to the address specified at location 0x0000 0018. For vectored and non-vectored IRQ’s the following instruction could be placed at 0x0000 0018:

C are

LDR pc, [pc,#-0xFF0]

This instruction loads PC with the address that is present in VICVectAddr register.

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In case UART0 request has been made, VICVectAddr will be identical to VICVectAddr0, while in case SPI0 request has been made value from VICVectAddr1 will be found here. If neither UART0 nor SPI0 have generated IRQ request but UART1 and/or I reason, content of VICVectAddr will be identical to VICDefVectAddr.

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C were the

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Chapter 6: Pin configuration

Rev. 01 — 12 January 2006 User manual

6.1 LPC2101/2102/2103 pinout

4847464544434241403938

DDA

DD(3V3)

P0.14/DCD1/SCK1/EINT1

P0.25/AD0.6

P0.12/DSR1/MAT1.0/AD0.5

P0.19/MAT1.2/MISO1 P0.11/CTS1/CAP1.1/AD0.4

P0.20/MAT1.3/MOSI1 P0.10/RTS1/CAP1.0/AD0.3

P0.21/SSEL1/MAT3.0 P0.24/AD0.2

VBAT P0.23/AD0.1

DD(1V8)

RST V

P0.27/TRST/CAP2.0 P0.8/TXD1/MAT2.1

P0.28/TMS/CAP2.1 P0.7/SSEL0/MAT2.0

P0.29/TCK/CAP2.2 DBGSEL

X1 RTCK

X2 RTXC2

Fig 14. LQFP48 pin configuration

LPC2101/2102/2103

1314151617181920212223

DD(3V3)

P0.31/TDO P0.15/RI1/EINT2

P0.30/TDI/MAT3.3 P0.16/EINT0/MAT0.2

P0.0/TXD0/MAT3.1 P0.18/CAP1.3/SDA1

P0.1/RXD0/MAT3.2 P0.17/CAP1.2/SCL1

P0.2/SCL0/CAP0.0 V

RTXC1 P0.13/DTR1/MAT1.1

P0.4/SCK0/CAP0.1 P0.26/AD0.7

P0.3/SDA0/MAT0.0 V

P0.22/AD0.0

SSA

P0.9/RXD1/MAT2.2

002aab821

P0.6/MOSI0/CAP0.2

P0.5/MISO0/MAT0.1

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P0.18/CAP1.3/SDA1

P0.17/CAP1.2/SCL1

P0.16/EINT0/MAT0.2

P0.15/RI1/EINT2

P0.14/DCD1/SCK1/EINT1

543

DDA

P0.13/DTR1/MAT1.1

4443424140

DD(3V3)

P0.25/AD0.6

P0.12/DSR1/MAT1.0/AD0.5

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RST

LPC2101/2102/2103

1819202122232425262728

P0.31/TDO

P0.30/TDI/MAT3.3

P0.0/TXD0/MAT3.1

P0.1/RXD0/MAT3.2

P0.2/SCL0/CAP0.0

P0.19/MAT1.2/MISO1

P0.20/MAT1.3/MOSI1

P0.21/SSEL1/MAT3.0

DD(1V8)

P0.27/TRST/CAP2.0

P0.28/TMS/CAP2.1

P0.29/TCK/CAP2.2

Fig 15. PLCC44 pin configuration

6.2 Pin description for LPC2101/02/03

RTXC1

P0.3/SDA0/MAT0.0

002aab920

P0.4/SCK0/CAP0.1

P0.6/MOSI0/CAP0.2

P0.5/MISO0/MAT0.1

P0.11/CTS1/CAP1.1/AD0.4

P0.10/RTS1/CAP1.0/AD0.3

P0.24/AD0.2

P0.23/AD0.1

P0.22/AD0.0

SSA

P0.9/RXD1/MAT2.2

P0.8/TXD1/MAT2.1

P0.7/SSEL0/MAT2.0

DBGSEL

RTXC2

Pin description for LPC2101/02/03 and a brief explanation of corresponding functions are shown in the following table.

Table 58: Pin description

Symbol LQFP48 PLCC44 Type Description

P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction

controls for each bit. A total of 31 pins of the Port 0 can be used as general purpose bidirectional digital I/Os while P0.31 is an output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block.

P0.0/TXD0/

[1]

MAT3.1

P0.1/RXD0/

[2]

MAT3.2

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[1]

I/O P0.0 — General purpose Input/output digital pin (GPIO).

O TXD0 — Transmitter output for UART0.

O MAT3.1 — PWM output 1 for Timer 3.

[2]

I/O P0.1 — General purpose Input/output digital pin (GPIO).

I RXD0 — Receiver input for UART0.

O MAT3.2 — PWM output 2 for Timer 3.

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Table 58: Pin description

…continued

Symbol LQFP48 PLCC44 Type Description

P0.2/SCL0/ CAP0.0

[3]

I/O P0.2 — General purpose Input/output digital pin (GPIO).

I/O SCL0 — I

C-bus compliance).

I CAP0.0 — Capture input for Timer 0, channel 0.

P0.3/SDA0/ MAT0.0

[3]

I/O P0.3 — General purpose Input/output digital pin (GPIO).

I/O SDA0 — I

C-bus compliance).

O MAT0.0 — PWM output for Timer 0, channel 0.

P0.4/SCK0/ CAP0.1

[4]

I/O P0.4 — General purpose Input/output digital pin (GPIO).

I/O SCK0 — Serial clock for SPI0. SPI clock output from master

or input to slave.

I CAP0.1 — Capture input for Timer 0, channel 1.

P0.5/MISO0/ MAT0.1

[4]

I/O P0.5 — General purpose Input/output digital pin (GPIO).

I/O MISO0 — Master In Slave OUT for SPI0. Data input to SPI

master or data output from SPI slave.

O MAT0.1 — PWM output for Timer 0, channel 1.

P0.6/MOSI0/ CAP0.2

[4]

I/O P0.6 — General purpose Input/output digital pin (GPIO).

I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI

master or data input to SPI slave.

I CAP0.2 — Capture input for Timer 0, channel 2.

P0.7/SSEL0/ MAT2.0

[2]

I/O P0.7 — General purpose Input/output digital pin (GPIO).

I SSEL0 — Slave Select for SPI0. Selects the SPI interface as

a slave.

O MAT2.0 — PWM output for Timer 2, channel 0.

P0.8/TXD1/ MAT2.1

[4]

I/O P0.8 — General purpose Input/output digital pin (GPIO).

O TXD1 — Transmitter output for UART1.

O MAT2.1 — PWM output for Timer 2, channel 1.

P0.9/RXD1/ MAT2.2

[2]

I/O P0.9 — General purpose Input/output digital pin (GPIO).

I RXD1 — Receiver input for UART1.

O MAT2.2 — PWM output for Timer 2, channel 2.

P0.10/RTS1/ CAP1.0/AD0.3

[4]

I/O P0.10 — General purpose Input/output digital pin (GPIO).

O RTS1 — Request to Send output for UART1.

I CAP1.0 — Capture input for Timer 1, channel 0.

I AD0.3 — Analog Input 3.

P0.11/CTS1/ CAP1.1/AD0.4

[3]

I/O P0.11 — General purpose Input/output digital pin (GPIO).

I CTS1 — Clear to Send input for UART1.

I CAP1.1 — Capture input for Timer 1, channel 1.

I AD0.4 — Analog Input 4.

P0.12/DSR1/ MAT1.0/AD0.5

[4]

I/O P0.12 — General purpose Input/output digital pin (GPIO).

I DSR1 — Data Set Ready input for UART1.

O MAT1.0 — PWM output for Timer 1, channel 0.

I AD0.5 — Analog Input 5.

C0 clock Input/output. Open-drain output (for

C0 data input/output. Open-drain output (for

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Table 58: Pin description

…continued

Symbol LQFP48 PLCC44 Type Description

P0.13/DTR1/ MAT1.1

[4]

I/O P0.13 — General purpose Input/output digital pin (GPIO).

O DTR1 — Data Terminal Ready output for UART1.

O MAT1.1 — PWM output for Timer 1, channel 1.

P0.14/DCD1/ SCK1/EINT1

[3]

I/O P0.14 — General purpose Input/output digital pin (GPIO).

I DCD1 — Data Carrier Detect input for UART1.

I/O SCK1 — Serial Clock for SPI1. SPI clock output from master

or input to slave.

I EINT1 — External interrupt 1 input.

P0.15/RI1/ EINT2

[4]

I/O P0.15 — General purpose Input/output digital pin (GPIO).

I RI1 — Ring Indicator input for UART1.

I EINT2 — External interrupt 2 input.

P0.16/EINT0/ MAT0.2

[2]

I/O P0.16 — General purpose Input/output digital pin (GPIO).

I EINT0 — External interrupt 0 input.

O MAT0.2 — PWM output for Timer 0, channel 2.

P0.17/CAP1.2/ SCL1

[1]

I/O P0.17 — General purpose Input/output digital pin (GPIO).

I CAP1.2 — Capture input for Timer 1, channel 2.

I/O SCL1 — I

C-bus compliance).

P0.18/CAP1.3/ SDA1

[1]

I/O P0.18 — General purpose Input/output digital pin (GPIO).

I CAP1.3 — Capture input for Timer 1, channel 3.

I/O SDA1 — I

I2C-bus compliance).

P0.19/MAT1.2/ MISO1

[1]

I/O P0.19 — General purpose Input/output digital pin (GPIO).

O MAT1.2 — PWM output for Timer 1, channel 2.

I/O MISO1 — Master In Slave Out for SSP. Data input to SPI

master or data output from SSP slave.

P0.20/MAT1.3/ MOSI1

[2]

I/O P0.20 — General purpose Input/output digital pin (GPIO).

O MAT1.3 — PWM output for Timer 1, channel 3.

I/O MOSI1 — Master Out Slave for SSP. Data output from SSP

master or data input to SSP slave.

P0.21/SSEL1/ MAT3.0

[4]

I/O P0.21 — General purpose Input/output digital pin (GPIO).

I SSEL1 — Slave Select for SPI1. Selects the SPI interface as

a slave.

O MAT3.0 — PWM output for Timer 3, channel 0.

P0.22/AD0.0 32

[4]

I/O P0.22 — General purpose Input/output digital pin (GPIO).

I AD0.0 — Analog Input 0.

P0.23/AD0.1 33

[1]

I/O P0.23 — General purpose Input/output digital pin (GPIO).

I AD0.1 — Analog Input 1.

P0.24/AD0.2 34

[1]

I/O P0.24 — General purpose Input/output digital pin (GPIO).

I AD0.2 — Analog Input 2.

P0.25/AD0.6 38

[1]

I/O P0.25 — General purpose Input/output digital pin (GPIO).

I AD0.6 — Analog Input 6.

C1 clock Input/output. Open-drain output (for

C1 data Input/output. Open-drain output (for

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Table 58: Pin description

…continued

Symbol LQFP48 PLCC44 Type Description

P0.26/AD0.7 39

[1]

n.c. I/O P0.26 — General purpose Input/output digital pin (GPIO).

I AD0.7 — Analog Input 7.

P0.27/TRST/ CAP2.0

[4]

I/O P0.27 — General purpose Input/output digital pin (GPIO).

I TRST — Test Reset for JTAG interface.

I CAP2.0 — Capture input for Timer 2, channel 0.

P0.28/TMS/ CAP2.1

[4]

I/O P0.28 — General purpose Input/output digital pin (GPIO).

I TMS — Test Mode Select for JTAG interface.

I CAP2.1 — Capture input for Timer 2, channel 1.

P0.29/TCK/ CAP2.2

[4]

I/O P0.29 — General purpose Input/output digital pin (GPIO).

I TCK — Test Clock for JTAG interface.

I CAP2.2 — Capture input for Timer 2, channel 2.

P0.30/TDI/ MAT3.3

[4]

I/O P0.30 — General purpose Input/output digital pin (GPIO).

I TDI — Test Data In for JTAG interface.

O MAT3.3 — PWM output 3 for Timer 3.

P0.31/TDO 16

[4]

O P0.31 — General purpose output only digital pin (GPIO).

O TDO — Test Data Out for JTAG interface.

RTXC1 20

RTXC2 25

RTCK 26

[5]

n.c. I/O Returned test clock output: Extra signal added to the JTAG

I Input to the RTC oscillator circuit.

O Output from the RTC oscillator circuit.

port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up.

X1 11 16 I Input to the oscillator circuit and internal clock generator

circuits.

X2 12 17 O Output from the oscillator amplifier.

DBGSEL 27 30 I Debug select: When LOW, the part operates normally. When

HIGH, debug mode is entered. Input with internal pull-down.

RST

611IExternal reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

SSA

7, 19, 43 1, 12, 23 I Ground: 0 V reference.

31 34 I Analog ground: 0 V reference. This should be nominally the

same voltage as V

but should be isolated to minimize noise

and error.

DDA

42 44 I Analog 3.3 V power supply: This should be nominally the

same voltage as V

but should be isolated to minimize

DD(3V3)

noise and error. This voltage is used to power the on-chip PLL.

DD(1V8)

510I1.8 V core power supply: This is the power supply voltage for

internal circuitry.

DD(3V3)

17, 40 42 I 3.3 V pad power supply: This is the power supply voltage for

the I/O ports.

VBAT 4 n.c. I RTC power supply: 3.3 V on this pin supplies the power to

the RTC.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

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[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input

function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.

[3] Open-drain 5 V tolerant digital I/O I

functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured

for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled.

[5] Pad provides special analog functionality.

C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output

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User manual Rev. 01 — 12 January 2006 65

7.1 Features

The Pin connect block allows individual pin configuration.

7.2 Applications

The purpose of the pin connect block is to configure the microcontroller pins to the desired functions.

7.3 Description

The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.

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Rev. 01 — 12 January 2006 User manual

Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

Selection of a single function on a port pin completely excludes all other functions otherwise available on the same pin.

The only partial exception from the above rule of exclusion is the case of inputs to the A/D converter. Regardless of the function that is currently selected for the port pin hosting the A/D input, this A/D input can be read at any time and variations of the voltage level on this pin will be reflected in the A/D readings. However, valid analog reading(s) can be obtained if and only if the function of an analog input is selected. Only in this case the proper interface circuit is active between the physical pin and the A/D module. In all other cases, a part of digital logic necessary for the digital function to be performed will be active and will disrupt proper behavior of the A/D.

7.4 Register description

The Pin Control Module contains 2 registers as shown in Ta bl e 5 9 below.

Table 59: Pin connect block register map

Name Description Access Reset value

PINSEL0 Pin function select

PINSEL1 Pin function select

[1]

Read/Write 0x0000 0000 0xE002 C000

Read/Write 0x0000 0000 0xE002 C004

Address

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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7.4.1 Pin function Select register 0 (PINSEL0 - 0xE002 C000)

The PINSEL0 register controls the functions of the pins as per the settings listed in

Ta bl e 6 2

function is selected for a pin. For other functions, direction is controlled automatically.

Table 60: Pin function select register 0 (PINSEL0 - 0xE002 C000)

PINSEL0 Pin name Va lue Function Value after

1:0 P0.0 0 0 GPIO Port 0.0 0

3:2 P0.1 0 0 GPIO Port 0.1 0

5:4 P0.2 0 0 GPIO Port 0.2 0

7:6 P0.3 0 0 GPIO Port 0.3 0

9:8 P0.4 0 0 GPIO Port 0.4 0

11:10 P0.5 0 0 GPIO Port 0.5 0

13:12 P0.6 0 0 GPIO Port 0.6 0

15:14 P0.7 0 0 GPIO Port 0.7 0

17:16 P0.8 0 0 GPIO Port 0.8 0

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. The direction control bit in the IO0DIR register is effective only when the GPIO

reset

01TXD0 (UART0)

1 0 MAT3.1(Timer 3)

11Reserved

01RXD0 (UART0)

1 0 MAT3.2 (Timer 3)

11Reserved

C0)

0 1 SCL0 (I

1 0 CAP0.0 (Timer 0)

11Reserved

01SDA0 (I

1 0 MAT0.0 (Timer 0)

11Reserved

0 1 SCK0 (SPI0)

1 0 CAP0.1 (Timer 0)

11Reserved

0 1 MISO0 (SPI0)

1 0 MAT0.1 (Timer 0)

11Reserved

0 1 MOSI0 (SPI0)

1 0 CAP0.2 (Timer 0)

11Reserved

0 1 SSEL0 (SPI0)

1 0 MAT2.0 (Timer 2)

11Reserved

01TXD1 (UART1)

1 0 MAT2.1 (Timer 2)

11Reserved

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Table 60: Pin function select register 0 (PINSEL0 - 0xE002 C000)

PINSEL0 Pin name Va lue Function Value after

19:18 P0.9 0 0 GPIO Port 0.9 0

01RXD1 (UART1)

1 0 MAT2.2 (Timer 2)

11Reserved

21:20 P0.10 0 0 GPIO Port 0.10 0

0 1 RTS1(UART1)

1 0 CAP1.0 (Timer 1)

11AD0.3

23:22 P0.11 0 0 GPIO Port 0.11 0

01CTS1(UART1)

1 0 CAP1.1 (Timer 1)

11AD0.4

25:24 P0.12 0 0 GPIO Port 0.12 0

0 1 DSR1 (UART1)

1 0 MAT1.0 (Timer 1)

11AD0.5

27:26 P0.13 0 0 GPIO Port 0.13 0

0 1 Reserved

1 0 MAT1.1 (Timer 1)

11DTR1(UART1)

29:28 P0.14 0 0 GPIO Port 0.14 0

01EINT1

1 0 SCK1 (SSP1)

1 1 DCD1 (UART1)

31:30 P0.15 0 0 GPIO Port 0.15 0

01EINT2

10Reserved

11RI1(UART1)

…continued

reset

7.4.2 Pin function Select register 1 (PINSEL1 - 0xE002 C004)

The PINSEL1 register controls the functions of the pins as per the settings listed in following tables. The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically.

Table 61: Pin function select register 1 (PINSEL1 - 0xE002 C004)

PINSEL1 Pin Name Valu e Function Value after reset

1:0 P0.16 0 0 GPIO Port 0.16 0

01EINT0

1 0 MAT0.2 (Timer 0)

11Reserved

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Table 61: Pin function select register 1 (PINSEL1 - 0xE002 C004)

PINSEL1 Pin Name Valu e Function Value after reset

3:2 P0.17 0 0 GPIO Port 0.17 0

C1)

01SCL1 (I

10CAP1.2 (Timer1)

11Reserved

5:4 P0.18 0 0 GPIO Port 0.18 0

01SDA1 (I

10CAP1.3 (Timer1)

11Reserved

7:6 P0.19 0 0 GPIO Port 0.19 0

01MISO1 (SPI1)

1 0 MAT1.2 (Timer 1)

11Reserved

9:8 P0.20 0 0 GPIO Port 0.20 0

01MOSI1 (SPI1)

1 0 MAT1.3 (Timer 1)

11Reserved

11:10 P0.21 0 0 GPIO Port 0.21 0

0 1 SSEL1 (SPI1)

1 0 MAT3.0 (Timer 3)

11Reserved

13:12 P0.22 0 0 GPIO Port 0.22 0

01Reserved

10Reserved

11AD0.0

15:14 P0.23 0 0 GPIO Port 0.23 0

01Reserved

10Reserved

11AD0.1

17:16 P0.24 0 0 GPIO Port 0.24 0

01Reserved

1 0 Reserved

11AD0.2

19:18 P0.25 0 0 GPIO Port 0.25 0

01Reserved

10Reserved

11AD0.6

21:20 P0.26 0 0 GPIO Port 0.26 0

01Reserved

10Reserved

11AD0.7

…continued

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UM10161

Table 61: Pin function select register 1 (PINSEL1 - 0xE002 C004)

PINSEL1 Pin Name Valu e Function Value after reset

23:22 P0.27 0 0 GPIO Port 0.27 0

01TRST (JTAG)

10CAP2.0 (Timer2)

11Reserved

25:24 P0.28 0 0 GPIO Port 0.28 0

01TMS (JTAG)

10CAP2.1 (Timer2)

11Reserved

27:26 P0.29 0 0 GPIO Port 0.29 0

01TCK (JTAG)

10CAP2.2 (Timer2)

11Reserved

29:28 P0.30 0 0 GPIO Port 0.30 0

01TDI (JTAG)

1 0 MAT3.3 (Timer 3)

11Reserved

31:30 P0.31 0 0 GPIO Port 0.31 0

01TDO (JTAG)

10Reserved

11Reserved

…continued

7.4.3 Pin function select register values

The PINSEL registers control the functions of device pins as shown below. Pairs of bits in these registers correspond to specific device pins.

Table 62: Pin function select register bits

PINSEL0 and PINSEL1 Values Function Value after Reset

00 Primary (default) function, typically GPIO

port

01 First alternate function

10 Second alternate function

11 Third alternate function

The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Each derivative typically has a different pinout and therefore a different set of functions possible for each pin. Details for a specific derivative may be found in the appropriate data sheet.

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8.1 Features

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Chapter 8: General Purpose Input/Output ports (GPIO)

Rev. 01 — 12 January 2006 User manual

• Every physical GPIO port is accessible via either the group of registers providing an

enhanced features and accelerated port access or the legacy group of registers.

• Accelerated GPIO functions:

– GPIO registers are relocated to the ARM local bus to achieve the fastest possible

I/O timing.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Individual bits can be direction controlled.

• All I/O default to inputs after reset.

• Backward compatibility with other earlier devices is maintained with legacy registers

appearing at the original addresses on the APB bus.

8.2 Applications

• General purpose I/O

• Driving LEDs or other indicators

• Controlling off-chip devices

• Sensing digital inputs

8.3 Pin description

Table 63: GPIO pin description

Pin Type Description

P0.0-P0.31 Input/

Output

General purpose input/output. The number of GPIOs actually available depends on the use of alternate functions.

8.4 Register description

LPC2101/02/03 has one 32-bit General Purpose I/O port. A total of 32 input/output pins are available on PORT0. PORT0 is controlled by the registers shown in Ta bl e 6 4

Ta bl e 6 5

Legacy registers shown in Ta bl e 6 4 devices, using existing code. The functions and relative timing of older GPIO implementations is preserved.

and

allow backward compatibility with earlier family

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The registers in Ta bl e 6 5 represent the enhanced GPIO features available on the LPC2101/02/03. All of these registers are located directly on the local bus of the CPU for the fastest possible read and write timing. An additional feature has been added that provides byte addressability of all GPIO registers. A mask register allows treating groups of bits in a single GPIO port separately from other bits on the same port.

User must select whether a GPIO will be accessed via registers that provide enhanced features or a legacy set of registers (see Section 3.6.1 “

registers are controlling the same physical pins, these two port control branches are mutually exclusive and operate independently. For example, changing a pin’s output via a fast register will not be observable via the corresponding legacy register.

The following text will refer to the legacy GPIO as "the slow" GPIO, while GPIO equipped with the enhanced features will be referred as "the fast" GPIO.

Table 64: GPIO register map (legacy APB accessible registers)

Generic Name

IOPIN GPIO Port Pin value register. The current

IOSET GPIO Port Output Set register. This

IODIR GPIO Port Direction control register. This

IOCLR GPIO Port Output Clear register. This

System Control and Status flags

Description AccessReset value

R/W NA 0xE002 8000 state of the GPIO configured port pins can always be read from this register, regardless of pin direction.

R/W 0x0000 0000 0xE002 8004 register controls the state of output pins in conjunction with the IOCLR register. Writing ones produces HIGHs at the corresponding port pins. Writing zeroes has no effect.

register controls the state of output pins. Writing ones produces LOW at the corresponding port pins and clears the corresponding bits in the IOSET register. Writing zeroes has no effect.

R/W 0x0000 0000 0xE002 8008

WO 0x0000 0000 0xE002 800C

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[1]

PORT0 Address & Name

IO0PIN

IO0SET

IO0DIR

IO0CLR

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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Table 65: GPIO register map (local bus accessible registers - enhanced GPIO features)

Generic Name

FIODIR Fast GPIO Port Direction control register.

FIOMASK Fast Mask register for port. Writes, sets,

FIOPIN Fast GPIO Port Pin value register using

FIOSET Fast GPIO Port Output Set register using

FIOCLR Fast GPIO Port Output Clear register

Description AccessReset value

R/W 0x0000 0000 0x3FFF C000 This register individually controls the direction of each port pin.

R/W 0x0000 0000 0x3FFF C010 clears, and reads to port (done via writes to FIOPIN, FIOSET, and FIOCLR, and reads of FIOPIN) alter or return only the bits enabled by zeros in this register.

R/W 0x0000 0000 0x3FFF C014 FIOMASK. The current state of digital port pins can be read from this register, regardless of pin direction or alternate function selection (as long as pins is not configured as an input to ADC). The value read is masked by ANDing with FIOMASK. Writing to this register places corresponding values in all bits enabled by ones in FIOMASK.

R/W 0x0000 0000 0x3FFF C018 FIOMASK. This register controls the state of output pins. Writing 1s produces HIGH at the corresponding port pins. Writing 0s has no effect. Reading this register returns the current contents of the port output register. Only bits enabled by ones in FIOMASK can be altered.

using FIOMASK. This register controls the state of output pins. Writing 1s produces LOW at the corresponding port pins. Writing 0s has no effect. Only bits enabled by ones in FIOMASK can be altered.

WO 0x0000 0000 0x3FFF C01C

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[1]

PORT0 Address & Name

FIO0DIR

FIO0MASK

FIO0PIN

FIO0SET

FIO0CLR

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

8.4.1 GPIO port 0 Direction register (IODIR, Port 0: IO0DIR - 0xE002 8008; FIODIR, Port 0: FIO0DIR - 0x3FFF C000)

This word accessible register is used to control the direction of the pins when they are configured as GPIO port pins. Direction bit for any pin must be set according to the pin functionality.

IO0DIR is the legacy register while the enhanced GPIO functions are supported via the FIO0DIR register.

Table 66: GPIO port 0 Direction register (IO0DIR - address 0xE002 8008) bit description

Bit Symbol Val ue Description Reset value

31:0 P0xDIR

1 Controlled pin is output.

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Slow GPIO Direction control bits. Bit 0 controls P0.0 ... bit 30 controls P0.30.

Controlled pin is input.

0x0000 0000

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Volume 1 Chapter 8: GPIO

Table 67: Fast GPIO port 0 Direction register (FIO0DIR - address 0x3FFF C000) bit description

Bit Symbol Val ue Description Reset value

31:0 FP0xDIR

1 Controlled pin is output.

Table 68: Fast GPIO port 0 Direction control byte and half-word accessible register description

FIO0DIR0 8 (byte) 0x3FFF C000 Fast GPIO Port 0 Direction control register 0. Bit 0 in FIO0DIR0

FIO0DIR1 8 (byte) 0x3FFF C001 Fast GPIO Port 0 Direction control register 1. Bit 0 in FIO0DIR1

FIO0DIR2 8 (byte) 0x3FFF C002 Fast GPIO Port 0 Direction control register 2. Bit 0 in FIO0DIR2

FIO0DIR3 8 (byte) 0x3FFF C003 Fast GPIO Port 0 Direction control register 3. Bit 0 in FIO0DIR3

FIO0DIRL 16

FIO0DIRU 16

(half-word)

Fast GPIO Direction control bits. Bit 0 in FIO0DIR controls P0.0 ... Bit 30 in FIO0DIR controls P0.30.

Controlled pin is input.

Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Ta bl e 6 8

registers allow easier and faster access to the physical port pins.

. Next to providing the same functions as the FIODIR register, these additional

Address Description Reset

0x3FFF C000 Fast GPIO Port 0 Direction control Lower half-word register. Bit 0 in

FIO0DIRL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C002 Fast GPIO Port 0 Direction control Upper half-word register. Bit 0 in

FIO0DIRU register corresponds to P0.16 ... bit 15 to P0.31.

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0x0000 0000

value

0x00

0x0000

8.4.2 Fast GPIO port 0 Mask register (FIOMASK, Port 0: FIO0MASK 0x3FFF C010)

This register is available in the enhanced group of registers only. It is used to select the port’s pins that will and will not be affected by a write accesses to the FIOPIN, FIOSET or FIOCLR register. The mask register also filters out the port’s content when the FIOPIN register is read.

A zero in this register’s bit enables an access to the corresponding physical pin via a read or write access. If a bit in this register is one, the corresponding pin will not be changed with write access and if read, will not be reflected in the updated FIOPIN register. For software examples, see Section 8.5 “

Table 69: Fast GPIO port 0 Mask register (FIO0MASK - address 0x3FFF C010) bit description

Bit Symbol Va lue Description Reset value

31:0 FP0xMASK

1 Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN

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Fast GPIO physical pin access control.

Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers. Current state of the pin will be observable in the FIOPIN register.

registers. When the FIOPIN register is read, this bit will not be updated with the state of the physical pin.

GPIO usage notes” on page 78

0x0000 0000

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Volume 1 Chapter 8: GPIO

Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Ta bl e 7 0

registers allow easier and faster access to the physical port pins.

Table 70: Fast GPIO port 0 Mask byte and half-word accessible register description

FIO0MASK0 8 (byte) 0x3FFF C010 Fast GPIO Port 0 Mask register 0. Bit 0 in FIO0MASK0 register

FIO0MASK1 8 (byte) 0x3FFF C011 Fast GPIO Port 0 Mask register 1. Bit 0 in FIO0MASK1 register

FIO0MASK2 8 (byte) 0x3FFF C012 Fast GPIO Port 0 Mask register 2. Bit 0 in FIO0MASK2 register

FIO0MASK3 8 (byte) 0x3FFF C013 Fast GPIO Port 0 Mask register 3. Bit 0 in FIO0MASK3 register

FIO0MASKL 16

FIO0MASKU 16

(half-word)

. Next to providing the same functions as the FIOMASK register, these additional

Address Description Reset

corresponds to P0.0 ... bit 7 to P0.7.

corresponds to P0.8 ... bit 7 to P0.15.

corresponds to P0.16 ... bit 7 to P0.23.

corresponds to P0.24 ... bit 7 to P0.31.

0x3FFF C001 Fast GPIO Port 0 Mask Lower half-word register. Bit 0 in

FIO0MASKL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C012 Fast GPIO Port 0 Mask Upper half-word register. Bit 0 in

FIO0MASKU register corresponds to P0.16 ... bit 15 to P0.31.

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value

0x00

0x0000

8.4.3 GPIO port 0 Pin value register (IOPIN, Port 0: IO0PIN - 0xE002 8000; FIOPIN, Port 0: FIO0PIN - 0x3FFF C014)

This register provides the value of port pins that are configured to perform only digital functions. The register will give the logic value of the pin regardless of whether the pin is configured for input or output, or as GPIO or an alternate digital function. As an example, a particular port pin may have GPIO input or GPIO output, UART receive, and PWM output as selectable functions. Any configuration of that pin will allow its current logic state to be read from the IOPIN register.

If a pin has an analog function as one of its options, the pin state cannot be read if the analog configuration is selected. Selecting the pin as an A/D input disconnects the digital features of the pin. In that case, the pin value read in the IOPIN register is not valid.

Writing to the IOPIN register stores the value in the port output register, bypassing the need to use both the IOSET and IOCLR registers to obtain the entire written value. This feature should be used carefully in an application since it affects the entire port.

The legacy register is the IO0PIN, while the enhanced GPIOs are supported via the FIO0PIN register. Access to a port pins via the FIOPIN register is conditioned by the corresponding FIOMASK register (see Section 8.4.2 “

(FIOMASK, Port 0: FIO0MASK - 0x3FFF C010)”).

Only pins masked with zeros in the Mask register (see Section 8.4.2 “

Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010)”) will be correlated to the

current content of the Fast GPIO port pin value register.

Fast GPIO port 0 Mask register

Fast GPIO port 0

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Table 71: GPIO port 0 Pin value register (IO0PIN - address 0xE002 8000) bit description

Bit Symbol Description Reset value

31:0 P0xVAL Slow GPIO pin value bits. Bit 0 in IO0PIN corresponds to P0.0 ... Bit 31 in IO0PIN

corresponds to P0.31.

Table 72: Fast GPIO port 0 Pin value register (FIO0PIN - address 0x3FFF C014) bit description

Bit Symbol Description Reset value

31:0 FP0xVAL Fast GPIO pin value bits. Bit 0 in FIO0PIN corresponds to P0.0 ... Bit 31 in FIO0PIN

corresponds to P0.31.

Aside from the 32-bit long and word only accessible FIOPIN register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Ta bl e 7 3

registers allow easier and faster access to the physical port pins.

Table 73: Fast GPIO port 0 Pin value byte and half-word accessible register description

FIO0PIN0 8 (byte) 0x3FFF C014 Fast GPIO Port 0 Pin value register 0. Bit 0 in FIO0PIN0 register

FIO0PIN1 8 (byte) 0x3FFF C015 Fast GPIO Port 0 Pin value register 1. Bit 0 in FIO0PIN1 register

FIO0PIN2 8 (byte) 0x3FFF C016 Fast GPIO Port 0 Pin value register 2. Bit 0 in FIO0PIN2 register

FIO0PIN3 8 (byte) 0x3FFF C017 Fast GPIO Port 0 Pin value register 3. Bit 0 in FIO0PIN3 register

FIO0PINL 16

FIO0PINU 16

(half-word)

. Next to providing the same functions as the FIOPIN register, these additional

Address Description Reset

corresponds to P0.0 ... bit 7 to P0.7.

corresponds to P0.8 ... bit 7 to P0.15.

corresponds to P0.16 ... bit 7 to P0.23.

corresponds to P0.24 ... bit 7 to P0.31.

0x3FFF C014 Fast GPIO Port 0 Pin value Lower half-word register. Bit 0 in

FIO0PINL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C016 Fast GPIO Port 0 Pin value Upper half-word register. Bit 0 in

FIO0PINU register corresponds to P0.16 ... bit 15 to P0.31.

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value

0x00

0x0000

8.4.4 GPIO port 0 output Set register (IOSET, Port 0: IO0SET - 0xE002 8004; FIOSET, Port 0: FIO0SET - 0x3FFF C018)

This register is used to produce a HIGH level output at the port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing 1 to the corresponding bit in the IOSET has no effect.

Reading the IOSET register returns the value of this register, as determined by previous writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins.

IO0SET is the legacy register while the enhanced GPIOs are supported via the FIO0SET register. Access to a port pins via the FIOSET register is conditioned by the corresponding FIOMASK register (see Section 8.4.2 “

FIO0MASK - 0x3FFF C010)”).

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Fast GPIO port 0 Mask register (FIOMASK, Port 0:

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Table 74: GPIO port 0 output Set register (IO0SET - address 0xE002 8004 bit description

Bit Symbol Description Reset value

31:0 P0xSET Slow GPIO output value Set bits. Bit 0 in IO0SET corresponds to P0.0 ... Bit 31

in IO0SET corresponds to P0.31.

Table 75: Fast GPIO port 0 output Set register (FIO0SET - address 0x3FFF C018) bit description

Bit Symbol Description Reset value

31:0 FP0xSET Fast GPIO output value Set bits. Bit 0 in FIO0SET corresponds to P0.0 ... Bit 31

in FIO0SET corresponds to P0.31.

Aside from the 32-bit long and word only accessible FIOSET register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Ta bl e 7 6

registers allow easier and faster access to the physical port pins.

Table 76: Fast GPIO port 0 output Set byte and half-word accessible register description

FIO0SET0 8 (byte) 0x3FFF C018 Fast GPIO Port 0 output Set register 0. Bit 0 in FIO0SET0 register

FIO0SET1 8 (byte) 0x3FFF C019 Fast GPIO Port 0 output Set register 1. Bit 0 in FIO0SET1 register

FIO0SET2 8 (byte) 0x3FFF C01A Fast GPIO Port 0 output Set register 2. Bit 0 in FIO0SET2 register

FIO0SET3 8 (byte) 0x3FFF C01B Fast GPIO Port 0 output Set register 3. Bit 0 in FIO0SET3 register

FIO0SETL 16

FIO0SETU 16

(half-word)

. Next to providing the same functions as the FIOSET register, these additional

Address Description Reset

corresponds to P0.0 ... bit 7 to P0.7.

corresponds to P0.8 ... bit 7 to P0.15.

corresponds to P0.16 ... bit 7 to P0.23.

corresponds to P0.24 ... bit 7 to P0.31.

0x3FFF C018 Fast GPIO Port 0 output Set Lower half-word register. Bit 0 in

FIO0SETL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C01A Fast GPIO Port 0 output Set Upper half-word register. Bit 0 in

FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.

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0x0000 0000

value

0x00

0x0000

8.4.5 GPIO port 0 output Clear register (IOCLR, Port 0: IO0CLR 0xE002 800C; FIOCLR, Port 0: FIO0CLR - 0x3FFF C01C)

This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears the corresponding bit in the IOSET register. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing to IOCLR has no effect.

IO0CLR is the legacy register while the enhanced GPIOs are supported via the FIO0CLR register. Access to a port pins via the FIOCLR register is conditioned by the corresponding FIOMASK register (see Section 8.4.2 “

(FIOMASK, Port 0: FIO0MASK - 0x3FFF C010)”).

Table 77: GPIO port 0 output Clear register 0 (IO0CLR - address 0xE002 800C) bit description

Bit Symbol Description Reset value

31:0 P0xCLR Slow GPIO output value Clear bits. Bit 0 in IO0CLR corresponds to P0.0 ... Bit

31 in IO0CLR corresponds to P0.31.

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Fast GPIO port 0 Mask register

0x0000 0000

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Table 78: Fast GPIO port 0 output Clear register 0 (FIO0CLR - address 0x3FFF C01C) bit description

Bit Symbol Description Reset value

31:0 FP0xCLR Fast GPIO output value Clear bits. Bit 0 in FIO0CLR corresponds to P0.0 ... Bit

31 in FIO0CLR corresponds to P0.31.

Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Ta bl e 7 9

registers allow easier and faster access to the physical port pins.

Table 79: Fast GPIO port 0 output Clear byte and half-word accessible register description

FIO0CLR0 8 (byte) 0x3FFF C01C Fast GPIO Port 0 output Clear register 0. Bit 0 in FIO0CLR0 register

FIO0CLR1 8 (byte) 0x3FFF C01D Fast GPIO Port 0 output Clear register 1. Bit 0 in FIO0CLR1 register

FIO0CLR2 8 (byte) 0x3FFF C01E Fast GPIO Port 0 output Clear register 2. Bit 0 in FIO0CLR2 register

FIO0CLR3 8 (byte) 0x3FFF C01F Fast GPIO Port 0 output Clear register 3. Bit 0 in FIO0CLR3 register

FIO0CLRL 16

FIO0CLRU 16

(half-word)

. Next to providing the same functions as the FIOCLR register, these additional

Address Description Reset

corresponds to P0.0 ... bit 7 to P0.7.

corresponds to P0.8 ... bit 7 to P0.15.

corresponds to P0.16 ... bit 7 to P0.23.

corresponds to P0.24 ... bit 7 to P0.31.

0x3FFF C01C Fast GPIO Port 0 output Clear Lower half-word register. Bit 0 in

FIO0CLRL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C01E Fast GPIO Port 0 output Clear Upper half-word register. Bit 0 in

FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.

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0x0000 0000

value

0x00

0x0000

8.5 GPIO usage notes

8.5.1 Example 1: sequential accesses to IOSET and IOCLR affecting the same GPIO pin/bit

State of the output configured GPIO pin is determined by writes into the pin’s port IOSET and IOCLR registers. Last of these accesses to the IOSET/IOCLR register will determine the final output of a pin.

In case of a code:

IO0DIR = 0x0000 0080 ;pin P0.7 configured as output IO0CLR = 0x0000 0080 ;P0.7 goes LOW IO0SET = 0x0000 0080 ;P0.7 goes HIGH IO0CLR = 0x0000 0080 ;P0.7 goes LOW

pin P0.7 is configured as an output (write to IO0DIR register). After this, P0.7 output is set to LOW (first write to IO0CLR register). Short high pulse follows on P0.7 (write access to IO0SET), and the final write to IO0CLR register sets pin P0.7 back to LOW level.

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8.5.2 Example 2: an immediate output of 0s and 1s on a GPIO port

Write access to port’s IOSET followed by write to the IOCLR register results with pins outputting 0s being slightly later then pins outputting 1s. There are systems that can tolerate this delay of a valid output, but for some applications simultaneous output of a binary content (mixed 0s and 1s) within a group of pins on a single GPIO port is required. This can be accomplished by writing to the port’s IOPIN register.

The following code will preserve existing output on PORT0 pins P0.[31:16] and P0.[7:0] and at the same time set P0.[15:8] to 0xA5, regardless of the previous value of pins P0.[15:8]:

IO0PIN = (IO0PIN && 0xFFFF00FF) || 0x0000A500

The same outcome can be obtained using the fast port access.

Solution 1: using 32-bit (word) accessible fast GPIO registers

FIO0MASK = 0xFFFF00FF; FIO0PIN = 0x0000A500;

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Solution 2: using 16-bit (half-word) accessible fast GPIO registers

FIO0MASKL = 0x00FF; FIO0PINL = 0xA500;

Solution 3: using 8-bit (byte) accessible fast GPIO registers

FIO0PIN1 = 0xA5;

8.5.3 Writing to IOSET/IOCLR vs. IOPIN

Write to the IOSET/IOCLR register allows easy change of the port’s selected output pin(s) to HIGH/LOW level at a time. Only pin/bit(s) in the IOSET/IOCLR written with 1 will be set to HIGH/LOW level, while those written as 0 will remain unaffected. However, by just writing to either IOSET or IOCLR register it is not possible to instantaneously output arbitrary binary data containing mixture of 0s and 1s on a GPIO port.

Write to the IOPIN register enables instantaneous output of a desired content on the parallel GPIO. Binary data written into the IOPIN register will affect all output configured pins of that parallel port: 0s in the IOPIN will produce LOW level pin outputs and 1s in IOPIN will produce HIGH level pin outputs. In order to change output of only a group of port’s pins, application must logically AND readout from the IOPIN with mask containing 0s in bits corresponding to pins that will be changed, and 1s for all others. Finally, this result has to be logically ORred with the desired content and stored back into the IOPIN register. Example 2 from above illustrates output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as they were before.

8.5.4 Output signal frequency considerations when using the legacy and enhanced GPIO registers

The enhanced features of the fast GPIO ports available on this microcontroller make GPIO pins more responsive to the code that has task of controlling them. In particular, software access to a GPIO pin is 3.5 times faster via the fast GPIO registers than it is when the legacy set of registers is used. As a result of the access speed increase, the

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maximum output frequency of the digital pin is increased 3.5 times, too. This tremendous increase of the output frequency is not always that visible when a plain C code is used. To gain full benefit from the fast GPIO features, write the portion of the application handling the fast port output in assembly code and execute in the ARM mode.

Here is a code where the pin control section is written in assembly language for ARM. First, port 0 is configured as slow port, and the program generates two pulses on P0.20. Then port 0 is configured as fast port, and two pulses are generated on P0.16. This illustrates the difference between the fast and slow GPIO port output capabilities. Once this code is compiled in the ARM mode, its execution from the on-chip Flash will yield the best results when the MAM module is configured as described in Section 4.9 “

notes” on page 43. Execution from the on-chip SRAM is independent from the MAM

setup.

ldr r0,=0xe01fc1a0 /*register address--SCS register*/ mov r1,#0x0 /*set bit 0 to 0*/ str r1,[r0] /*enable slow port*/ ldr r1,=0xffffffff /* */ ldr r0,=0xe0028008 /*register address--IODIR*/ str r1,[r0] /*set port 0 to output*/ ldr r2,=0x00100000 /*select P0.20*/ ldr r0,=0xe0028004 /*register address--IOSET*/ ldr r1,=0xe002800C /*register address--IOCLR*/

str r2,[r0] /*HIGH*/ str r2,[r1] /*LOW*/ str r2,[r0] /*HIGH*/ str r2,[r1] /*LOW*/

ldr r0,=0xe01fc1a0 /*register address--enable fast port*/ mov r1,#0x1 str r1,[r0] /*enable fast port0*/ ldr r1,=0xffffffff ldr r0,=0x3fffc000 /*direction of fast port0*/ str r1,[r0] ldr r0,=0x3fffc018 /*FIO0SET -- fast port0 register*/ ldr r1,=0x3fffc01c /*FIO0CLR0 -- fast port0 register*/ ldr r2,=0x00010000 /*select fast port 0.16 for toggle*/

str r2,[r0] str r2,[r1] str r2,[r0] str r2,[r1]

loop: b loop

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MAM usage

/*set port 0 to slow GPIO */

/*generate 2 pulses using slow GPIO on P0.20*/

/*set port 0 to fast GPIO */

/*generate 2 pulses on the fast port*/

Figure 16 illustrates the code from above executed from the LPC2101/02/03 Flash

memory. The PLL generated F was fully enabled with MEMCR = 2 and MEMTIM = 3, and APBDIV = 1 (PCLK = CCLK).

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=60 MHz out of external F

CCLK

= 12 MHz. The MAM

OSC

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Fig 16. Illustration of the fast and slow GPIO access and output showing 3.5 x increase of the pin output

frequency

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Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (UART0)

Rev. 01 — 12 January 2006 User manual

9.1 Features

• 16 byte Receive and Transmit FIFOs

• Register locations conforming to ‘550 industry standard

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

• Built-in fractional baud rate generator with autobauding capabilities.

• Mechanism that enables software and hardware flow control implementation

9.2 Pin description

Table 80: UART0 pin description

Pin Type Description

RXD0 Input Serial Input. Serial receive data.

TXD0 Output Serial Output. Serial transmit data.

9.3 Register description

UART0 contains registers organized as shown in Tab l e 8 1 . The Divisor Latch Access Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.

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Table 81: UART0 register map

Name Description Bit functions and addresses Access Reset

U0RBR Receiver Buffer

U0THR Transmit Holding

U0DLL Divisor Latch LSB 8-bit Data R/W 0x01 0xE000 C000

U0DLM Divisor Latch MSB 8-bit Data R/W 0x00 0xE000 C004

U0IER Interrupt Enable

U0IIRInterrupt ID Reg.------ABTO IntABEO Int RO 0x01 0xE000 C008

U0FCR FIFO Control

U0LCR Line Control

U0LSR Line Status

U0SCR Scratch Pad Reg. 8-bit Data R/W 0x00 0xE000 C01C

U0ACR Auto-baud Control

U0FDR Fractional Divider

U0TERTX. Enable Reg.TXEN-------R/W0x800xE000C030

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

MSB LSB

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

8-bit Read Data RO NA 0xE000 C000

8-bit Write Data WO NA 0xE000 C000

------En.ABTOEn.ABEO R/W 0x00 0xE000 C004

-----En.RX

FIFOs Enabled - - IIR3 IIR2 IIR1 IIR0

RX Trigger - - - TX FIFO

DLAB Set

Break

RX FIFO

Error

------ABTO

-----Aut.Rstrt.ModeStart

TEMT THRE BI FE PE OE DR RO 0x60 0xE000 C014

Stick

Parity

MulVal DivAddVal

Even

Par.Selct.

Reserved[31:8] 0x10 0xE000 C028

Parity

Enable

Lin.St.Int

Reset

No. of

Stop Bits

Address

[1]

value

(DLAB=0)

(DLAB=1)

Enable

THRE Int

RX FIFO

Reset

Word Length Select R/W 0x00 0xE000 C00C

Int.Clr

En.RX

Dat.Av.Int

FIFO

Enable

ABEO Int.Clr

WO 0x00 0xE000 C008

R/W 0x00 0xE000 C020

(DLAB=0)

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Volume 1 Chapter 9: UART0

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[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

Philips Semiconductors

Volume 1 Chapter 9: UART0

9.3.1 UART0 Receiver Buffer register (U0RBR - 0xE000 C000, when DLAB = 0, Read Only)

The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes.

The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0RBR. The U0RBR is always Read Only.

Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U0LSR register, and then to read a byte from the U0RBR.

Table 82: UART0 Receiver Buffer Register (U0RBR - address 0xE000 C000, when DLAB = 0,

Bit Symbol Description Reset value

7:0 RBR The UART0 Receiver Buffer Register contains the oldest

UM10161

Read Only) bit description

undefined

received byte in the UART0 Rx FIFO.

9.3.2 UART0 Transmit Holding Register (U0THR - 0xE000 C000, when DLAB = 0, Write Only)

The U0THR is the top byte of the UART0 TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit.

The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0THR. The U0THR is always Write Only.

Table 83: UART0 Transmit Holding Register (U0THR - address 0xE000 C000, when

DLAB = 0, Write Only) bit description

Bit Symbol Description Reset value

7:0 THR Writing to the UART0 Transmit Holding Register causes the data

to be stored in the UART0 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.

9.3.3 UART0 Divisor Latch registers (U0DLL - 0xE000 C000 and U0DLM 0xE000 C004, when DLAB = 1)

The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock, which must be 16x the desired baud rate (Equation 1 and U0DLM registers together form a 16 bit divisor where U0DLL contains the lower 8 bits of the divisor and U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U0LCR must be one in order to access the UART0 Divisor Latches.

). The U0DLL

Details on how to select the right value for U0DLL and U0DLM can be found later on in this chapter.

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Table 84: UART0 Divisor Latch LSB register (U0DLL - address 0xE000 C000, when

Bit Symbol Description Reset value

7:0 DLL The UART0 Divisor Latch LSB Register, along with the U0DLM

Table 85: UART0 Divisor Latch MSB register (U0DLM - address 0xE000 C004, when

Bit Symbol Description Reset value

7:0 DLM The UART0 Divisor Latch MSB Register, along with the U0DLL

9.3.4 UART0 Fractional Divider Register (U0FDR - 0xE000 C028)

The UART0 Fractional Divider Register (U0FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at user’s discretion. This pre-scaler takes the APB clock and generates an output clock per specified fractional requirements.

Table 86: UART0 Fractional Divider Register (U0FDR - address 0xE000 C028) bit description

Bit Function Description Reset value

3:0 DIVADDVAL Baudrate generation pre-scaler divisor value. If this field is 0,

7:4 MULVAL Baudrate pre-scaler multiplier value. This field must be greater

31:8 - Reserved, user software should not write ones to reserved bits.

DLAB = 1) bit description

fractional baudrate generator will not impact the UART0 baudrate.

or equal 1 for UART0 to operate properly, regardless of whether the fractional baudrate generator is used or not.

The value read from a reserved bit is not defined.

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0x01

0x00

This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART0 disabled making sure that UART0 is fully software and hardware compatible with UARTs not equipped with this feature.

UART0 baudrate can be calculated as:

(1)

UART0

Where PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART0 baud rate divider registers, and DIVADDVAL and MULVAL are UART0 fractional baudrate generator specific parameters.

The value of MULVAL and DIVADDVAL should comply to the following conditions:

1. 0 < MULVAL ≤ 15

2. 0 ≤ DIVADDVAL ≤ 15

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baudrate

-------------------------------------------------------------------------------------------------------------------------------

16 16 U0DLM× U0DLL+()× 1

PCLK

DivAddVal

⎛⎞

-----------------------------

⎝⎠

MulVal

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If the U0FDR register value does not comply to these two requests then the fractional divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided.

The value of the U0FDR should not be modified while transmitting/receiving data or data may be lost or corrupted.

Usage Note: For practical purposes, UART0 baudrate formula can be written in a way that identifies the part of a UART baudrate generated without the fractional baudrate generator, and the correction factor that this module adds:

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(2)

UART0

Based on this representation, fractional baudrate generator contribution can also be described as a prescaling with a factor of MULVAL / (MULVAL + DIVADDVAL).

baudrate

-----------------------------------------------------------------------------

16 16 U0D LM× U0DLL+()×

9.3.5 UART0 baudrate calculation

Example 1: Using UART0baudrate formula from above, it can be determined that system

with PCLK = 20 MHz, U0DL = 130 (U0DLM = 0x00 and U0DLL = 0x82), DIVADDVAL = 0 and MULVAL = 1 will enable UART0 with UART0baudrate = 9615 bauds.

Example 2: Using UART0baudrate formula from above, it can be determined that system with PCLK = 20 MHz, U0DL = 93 (U0DLM = 0x00 and U0DLL = 0x5D), DIVADDVAL = 2 and MULVAL = 5 will enable UART0 with UART0baudrate = 9600 bauds.

Table 87: Baudrates available when using 20 MHz peripheral clock (PCLK = 20 MHz)

Desired baudrate

50 61A8 25000 0.0000 25000 1/(1+0) 0.0000

75 411B 16667 0.0020 12500 3/(3+1) 0.0000

110 2C64 11364 0.0032 6250 11/(11+9) 0.0000

134.5 244E 9294 0.0034 3983 3/(3+4) 0.0001

150 208D 8333 0.0040 6250 3/(3+1) 0.0000

300 1047 4167 0.0080 3125 3/(3+1) 0.0000

600 0823 2083 0.0160 1250 3/(3+2) 0.0000

1200 0412 1042 0.0320 625 3/(3+2) 0.0000

1800 02B6 694 0.0640 625 9/(9+1) 0.0000

2000 0271 625 0.0000 625 1/(1+0) 0.0000

2400 0209 521 0.0320 250 12/(12+13) 0.0000

3600 015B 347 0.0640 248 5/(5+2) 0.0064

4800 0104 260 0.1600 125 12/(12+13) 0.0000

MULVAL = 0 DIVADDVAL = 0 Optimal MULVAL & DIVADDVAL

U0DLM:U0DLL % error

hex

[2]

dec

[1]

PCLK

[3]

U0DLM:U0DLL

[1]

dec

------------------------------------------------------------

×=

MulVal

MulVal DivAddVal+()

Fractional

pre-scaler value

MULDIV

MULDIV + DIVADDVAL

% error

[3]

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Table 87: Baudrates available when using 20 MHz peripheral clock (PCLK = 20 MHz)

Desired baudrate

7200 00AE 174 0.2240 124 5/(5+2) 0.0064

9600 0082 130 0.1600 93 5/(5+2) 0.0064

19200 0041 65 0.1600 31 10/(10+11) 0.0064

38400 0021 33 1.3760 12 7/(7+12) 0.0594

56000 0021 22 1.4400 13 7/(7+5) 0.0160

57600 0016 22 1.3760 19 7/(7+1) 0.0594

112000 000B 11 1.4400 6 7/(7+6) 0.1600

115200 000B 11 1.3760 4 7/(7+12) 0.0594

224000 0006 6 7.5200 3 7/(7+6) 0.1600

448000 0003 3 7.5200 2 5/(5+2) 0.3520

[1] Values in the row represent decimal equivalent of a 16 bit long content (DLM:DLL).

[2] Values in the row represent hex equivalent of a 16 bit long content (DLM:DLL).

[3] Refers to the percent error between desired and actual baudrate.

MULVAL = 0 DIVADDVAL = 0 Optimal MULVAL & DIVADDVAL

U0DLM:U0DLL % error

hex

[2]

dec

[1]

[3]

U0DLM:U0DLL

[1]

dec

Fractional

pre-scaler value

MULDIV

MULDIV + DIVADDVAL

UM10161

% error

[3]

9.3.6 UART0 Interrupt Enable Register (U0IER - 0xE000 C004, when DLAB = 0)

The U0IER is used to enable UART0 interrupt sources.

Table 88: UART0 Interrupt Enable Register (U0IER - address 0xE000 C004, when DLAB = 0)

bit description

Bit Symbol Value Description Reset

0RBR

Interrupt Enable

1 Enable the RDA interrupts.

1THRE

Interrupt Enable

2RX Line

Status Interrupt Enable

7:3 - - Reserved, user software should not write ones to

1 Enable the THRE interrupts.

1 Enable the RX line status interrupts.

U0IER[0] enables the Receive Data Available interrupt for UART0. It also controls the Character Receive Time-out interrupt.

Disable the RDA interrupts.

U0IER[1] enables the THRE interrupt for UART0. The status of this can be read from U0LSR[5].

Disable the THRE interrupts.

U0IER[2] enables the UART0 RX line status interrupts. The status of this interrupt can be read from U0LSR[4:1].

Disable the RX line status interrupts.

reserved bits. The value read from a reserved bit is not defined.

value

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Table 88: UART0 Interrupt Enable Register (U0IER - address 0xE000 C004, when DLAB = 0)

Bit Symbol Value Description Reset

8 ABTOIntEn

9 ABEOIntEn

31:10 - - Reserved, user software should not write ones to

9.3.7 UART0 Interrupt Identification Register (U0IIR - 0xE000 C008, Read Only)

The U0IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U0IIR access. If an interrupt occurs during an U0IIR access, the interrupt is recorded for the next U0IIR access.

bit description

U0IER8 enables the auto-baud time-out interrupt.

Disable Auto-baud Time-out Interrupt.

1 Enable Auto-baud Time-out Interrupt.

U0IER9 enables the end of auto-baud interrupt.

Disable End of Auto-baud Interrupt.

1 Enable End of Auto-baud Interrupt.

reserved bits. The value read from a reserved bit is not defined.

UM10161

value

Table 89: UART0 Interrupt Identification Register (UOIIR - address 0xE000 C008, read only)

bit description

Bit Symbol Value Description Reset

0 Interrupt

Pending

3:1 Interrupt

Identification

5:4 - Reserved, user software should not write ones to reserved

7:6 FIFO Enable These bits are equivalent to U0FCR[0]. 0

8 ABEOInt End of auto-baud interrupt. True if auto-baud has finished

9 ABTOInt Auto-baud time-out interrupt. True if auto-baud has timed

31:10 - Reserved, user software should not write ones to reserved

Note that U0IIR[0] is active LOW. The pending interrupt can be determined by evaluating U0IIR[3:1].

At least one interrupt is pending.

1 No pending interrupts.

U0IER[3:1] identifies an interrupt corresponding to the UART0 Rx FIFO. All other combinations of U0IER[3:1] not listed above are reserved (000,100,101,111).

011

1 - Receive Line Status (RLS).

010 2a - Receive Data Available (RDA).

110 2b - Character Time-out Indicator (CTI).

001 3 - THRE Interrupt

bits. The value read from a reserved bit is not defined.

successfully and interrupt is enabled.

out and interrupt is enabled.

bits. The value read from a reserved bit is not defined.

value

Interrupts are handled as described in Ta bl e 9 0

. Given the status of U0IIR[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The U0IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine.

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The UART0 RLS interrupt (U0IIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART0 Rx input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART0 Rx error condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared upon an U0LSR read.

The UART0 RDA interrupt (U0IIR[3:1] = 010) shares the second level priority with the CTI interrupt (U0IIR[3:1] = 110). The RDA is activated when the UART0 Rx FIFO reaches the trigger level defined in U0FCR[7:6] and is reset when the UART0 Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level.

The CTI interrupt (U0IIR[3:1] = 110) is a second level interrupt and is set when the UART0 Rx FIFO contains at least one character and no UART0 Rx FIFO activity has occurred in

3.5 to 4.5 character times. Any UART0 Rx FIFO activity (read or write of UART0 RSR) will clear the interrupt. This interrupt is intended to flush the UART0 RBR after a message has been received that is not a multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters.

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Table 90: UART0 interrupt handling

U0IIR[3:0] value

0001 - None None -

0110 Highest RX Line Status / Error OE

0100 Second RX Data Available Rx data available or trigger level reached in FIFO

1100 Second Character Time-out

0010 Third THRE THRE

Priority Interrupt Type Interrupt Source Interrupt Reset

[1]

[2]

(U0FCR0=1)

Minimum of one character in the Rx FIFO and no

indication

[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.

[2] For details see Section 9.3.10 “

[3] For details see Section 9.3.1 “UART0 Receiver Buffer register (U0RBR - 0xE000 C000, when DLAB = 0,

Read Only)”

[4] For details see Section 9.3.7 “UART0 Interrupt Identification Register (U0IIR - 0xE000 C008, Read Only)”

and Section 9.3.2 “

Only)”

character input or removed during a time period depending on how many characters are in FIFO and what the trigger level is set at (3.5 to 4.5 character times).

The exact time will be: [(word length) × 7

number of characters) × 8 + 1] RCLKs

UART0 Transmit Holding Register (U0THR - 0xE000 C000, when DLAB = 0, Write

or PE

[2]

or FE

[2]

or BI

[2]

− 2] × 8 + [(trigger level −

[2]

UART0 Line Status Register (U0LSR - 0xE000 C014, Read Only)”

U0LSR Read

U0RBR Read UART0 FIFO drops below trigger level

U0RBR Read

U0IIR Read (if source of interrupt) or THR write

[2]

[3]

[4]

The UART0 THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt and is activated when the UART0 THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART0 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The

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initialization conditions implement a one character delay minus the stop bit whenever THRE=1 and there have not been at least two characters in the U0THR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to U0THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART0 THR FIFO has held two or more characters at one time and currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).

9.3.8 UART0 FIFO Control Register (U0FCR - 0xE000 C008)

The U0FCR controls the operation of the UART0 Rx and TX FIFOs.

Table 91: UART0 FIFO Control Register (U0FCR - address 0xE000 C008) bit description

Bit Symbol Value Description Reset value

0 FIFO Enable 0 UART0 FIFOs are disabled. Must not be used in the

1 RX FIFO

Reset

2 TX FIFO

Reset

5:3 - 0 Reserved, user software should not write ones to

7:6 RX Trigger

Level

UM10161

application.

1 Active HIGH enable for both UART0 Rx and TX

FIFOs and U0FCR[7:1] access. This bit must be set for proper UART0 operation. Any transition on this bit will automatically clear the UART0 FIFOs.

0 No impact on either of UART0 FIFOs. 0

1 Writing a logic 1 to U0FCR[1] will clear all bytes in

UART0 Rx FIFO and reset the pointer logic. This bit is self-clearing.

0 No impact on either of UART0 FIFOs. 0

1 Writing a logic 1 to U0FCR[2] will clear all bytes in

01 trigger level 1 (4 characters or 0x04).

10 trigger level 2 (8 characters or 0x08).

11 trigger level 3 (14 characters or 0x0E).

UART0 TX FIFO and reset the pointer logic. This bit is self-clearing.

reserved bits. The value read from a reserved bit is not defined.

These two bits determine how many receiver UART0 FIFO characters must be written before an interrupt is activated.

trigger level 0 (1 character or 0x01).

9.3.9 UART0 Line Control Register (U0LCR - 0xE000 C00C)

The U0LCR determines the format of the data character that is to be transmitted or received.

Table 92: UART0 Line Control Register (U0LCR - address 0xE000 C00C) bit description

Bit Symbol Value Description Reset value

1:0 Word Length

Select

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00 5 bit character length 0

01 6 bit character length

10 7 bit character length

11 8 bit character length

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Volume 1 Chapter 9: UART0

Table 92: UART0 Line Control Register (U0LCR - address 0xE000 C00C) bit description

Bit Symbol Value Description Reset value

2 Stop Bit Select 0 1 stop bit. 0

1 2 stop bits (1.5 if U0LCR[1:0]=00).

3 Parity Enable 0 Disable parity generation and checking. 0

1 Enable parity generation and checking.

5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and the

attached parity bit will be odd.

01 Even Parity. Number of 1s in the transmitted character and the

attached parity bit will be even.

10 Forced "1" stick parity.

11 Forced "0" stick parity.

6 Break Control 0 Disable break transmission. 0

1 Enable break transmission. Output pin UART0 TXD is forced to

logic 0 when U0LCR[6] is active HIGH.

7 Divisor Latch

Access Bit (DLAB)

0 Disable access to Divisor Latches. 0

1 Enable access to Divisor Latches.

9.3.10 UART0 Line Status Register (U0LSR - 0xE000 C014, Read Only)

The U0LSR is a read-only register that provides status information on the UART0 TX and RX blocks.

Table 93: UART0 Line Status Register (U0LSR - address 0xE000 C014, read only) bit description

Bit Symbol Val ue Description Reset value

0 Receiver Data

Ready (RDR)

1 Overrun Error

(OE)

2 Parity Error

(PE)

U0LSR0 is set when the U0RBR holds an unread character and is cleared when the UART0 RBR FIFO is empty.

U0RBR is empty.

1 U0RBR contains valid data.

The overrun error condition is set as soon as it occurs. An U0LSR read clears U0LSR1. U0LSR1 is set when UART0 RSR has a new character assembled and the UART0 RBR FIFO is full. In this case, the UART0 RBR FIFO will not be overwritten and the character in the UART0 RSR will be lost.

Overrun error status is inactive.

1 Overrun error status is active.

When the parity bit of a received character is in the wrong state, a parity error occurs. An U0LSR read clears U0LSR[2]. Time of parity error detection is dependent on U0FCR[0].

Note: A parity error is associated with the character at the top of the UART0 RBR FIFO.

Parity error status is inactive.

1 Parity error status is active.

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Table 93: UART0 Line Status Register (U0LSR - address 0xE000 C014, read only) bit description

Bit Symbol Val ue Description Reset value

3 Framing Error

(FE)

4 Break Interrupt

(BI)

5 Transmitter

Holding Register Empty (THRE))

6 Transmitter

Empty (TEMT)

7 Error in RX

FIFO (RXFE)

When the stop bit of a received character is a logic 0, a framing error occurs. An U0LSR read clears U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error.

Note: A framing error is associated with the character at the top of the UART0 RBR FIFO.

Framing error status is inactive.

1 Framing error status is active.

When RXD0 is held in the spacing state (all 0’s) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD0 goes to marking state (all 1’s). An U0LSR read clears this status bit. The time of break detection is dependent on U0FCR[0].

Note: The break interrupt is associated with the character at the top of the UART0 RBR FIFO.

Break interrupt status is inactive.

1 Break interrupt status is active.

THRE is set immediately upon detection of an empty UART0 THR and is cleared on a U0THR write.

U0THR contains valid data.

1 U0THR is empty.

TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data.

U0THR and/or the U0TSR contains valid data.

1 U0THR and the U0TSR are empty.

U0LSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the UART0 FIFO.

U0RBR contains no UART0 RX errors or U0FCR[0]=0.

1 UART0 RBR contains at least one UART0 RX error.

9.3.11 UART0 Scratch Pad Register (U0SCR - 0xE000 C01C)

The U0SCR has no effect on the UART0 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred.

Table 94: UART0 Scratch Pad Register (U0SCR - address 0xE000 C01C) bit description

Bit Symbol Description Reset value

7:0 Pad A readable, writable byte. 0x00

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9.3.12 UART0 Auto-baud Control Register (U0ACR - 0xE000 C020)

The UART0 Auto-baud Control Register (U0ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion.

Table 95: Auto-baud Control Register (U0ACR - 0xE000 C020) bit description

Bit Symbol Value Description Reset value

0 Start This bit is automatically cleared after auto-baud

1 Mode Auto-baud mode select bit. 0

2 AutoRestart 0 No restart 0

7:3 - NA Reserved, user software should not write ones to

8 ABEOIntClr End of auto-baud interrupt clear bit (write only

9 ABTOIntClr Auto-baud time-out interrupt clear bit (write only

31:10 - NA Reserved, user software should not write ones to

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completion.

0 Auto-baud stop (auto-baud is not running).

1 Auto-baud start (auto-baud is running).Auto-baud run

bit. This bit is automatically cleared after auto-baud completion.

0 Mode 0.

1 Mode 1.

1 Restart in case of time-out (counter restarts at next

UART0 Rx falling edge)

reserved bits. The value read from a reserved bit is not defined.

accessible). Writing a 1 will clear the corresponding interrupt in the U0IIR. Writing a 0 has no impact.

reserved bits. The value read from a reserved bit is not defined.

9.3.13 Auto-baud

The UART0 auto-baud function can be used to measure the incoming baud-rate based on the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers U0DLM and U0DLL accordingly.

Auto-baud is started by setting the U0ACR Start bit. Auto-baud can be stopped by clearing the U0ACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished).

Two auto-baud measuring modes are available which can be selected by the U0ACR Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the UART0 Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent rising edge of the UART0 Rx pin (the length of the start bit).

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The U0ACR AutoRestart bit can be used to automatically restart baud-rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate measurement will restart at the next falling edge of the UART0 Rx pin.

The auto-baud function can generate two interrupts.

• The U0IIR ABTOInt interrupt will get set if the interrupt is enabled (U0IER ABToIntEn

is set and the auto-baud rate measurement counter overflows).

• The U0IIR ABEOInt interrupt will get set if the interrupt is enabled (U0IER ABEOIntEn

is set and the auto-baud has completed successfully).

The auto-baud interrupts have to be cleared by setting the corresponding U0ACR ABTOIntClr and ABEOIntEn bits.

Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it is going to impact the measuring of UART0 Rx pin baud-rate, but the value of the U0FDR register is not going to be modified after rate measurement. Also, when auto-baud is used, any write to U0DLM and U0DLL registers should be done before U0ACR register write. The minimum and the maximum baudrates supported by UART0 are function of PCLK, number of data bits, stop-bits and parity bits.

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ratemin

2P× CLK

-------------------------

16 215×

UART0

≤≤ ratemax

baudrate

------------------------------------------------------------------------------------------------------------

16 2 databits paritybits s topbits++ +()×

PCLK

9.3.14 UART0 Transmit Enable Register (U0TER - 0xE000 C030)

LPC2101/02/03’s U0TER enables implementation of software flow control. When TXEn=1, UART0 transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UART0 transmission will stop.

Ta bl e 9 6

Table 96: UART0 Transmit Enable Register (U0TER - address 0xE000 C030) bit description

Bit Symbol Description Reset

6:0 - Reserved, user software should not write ones to reserved bits. The

7 TXEN When this bit is 1, as it is after a Reset, data written to the THR is output

describes how to use TXEn bit in order to achieve software flow control.

value read from a reserved bit is not defined.

on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character.

(3)

value

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Volume 1 Chapter 9: UART0

9.3.15 Auto-baud modes

When the software is expecting an ”AT" command, it configures the UART0 with the expected character format and sets the U0ACR Start bit. The initial values in the divisor latches U0DLM and U0DLM don‘t care. Because of the ”A" or ”a" ASCII coding (”A" = 0x41, ”a" = 0x61), the UART0 Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges. When the U0ACR Start bit is set, the auto-baud protocol will execute the following phases:

1. On U0ACR Start bit setting, the baud-rate measurement counter is reset and the UART0 U0RSR is reset. The U0RSR baud rate is switch to the highest rate.

2. A falling edge on UART0 Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting PCLK cycles optionally pre-scaled by the fractional baud-rate generator.

3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the (fractional baud-rate pre-scaled) UART0 input clock, guaranteeing the start bit is stored in the U0RSR.

4. During the receipt of the start bit (and the character LSB for mode = 0) the rate counter will continue incrementing with the pre-scaled UART0 input clock (PCLK).

5. If Mode = 0 then the rate counter will stop on next falling edge of the UART0 Rx pin. If Mode = 1 then the rate counter will stop on the next rising edge of the UART0 Rx pin.

6. The rate counter is loaded into U0DLM/U0DLL and the baud-rate will be switched to normal operation. After setting the U0DLM/U0DLL the end of auto-baud interrupt U0IIR ABEOInt will be set, if enabled. The U0RSR will now continue receiving the remaining bits of the ”A/a" character.

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Volume 1 Chapter 9: UART0

start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop

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'A' (0x41) or 'a' (0x61)

UART0 RX

U0ACR start

rate counter

16xbaud_rate

a. Mode 0 (start bit and LSB are used for auto-baud)

UART0 RX

U0ACR start

rate counter

16 cycles 16 cycles

start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop

start bit LSB of 'A' or 'a'

'A' (0x41) or 'a' (0x61)

start bit LSB of 'A' or 'a'

16xbaud_rate

b. Mode 1 (only start bit is used for auto-baud)

Fig 17. Autobaud a) mode 0 and b) mode 1 waveform.

16 cycles

9.4 Architecture

The architecture of the UART0 is shown below in the block diagram.

The APB interface provides a communications link between the CPU or host and the UART0.

The UART0 receiver block, U0RX, monitors the serial input line, RXD0, for valid input. The UART0 RX Shift Register (U0RSR) accepts valid characters via RXD0. After a valid character is assembled in the U0RSR, it is passed to the UART0 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface.

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Volume 1 Chapter 9: UART0

The UART0 transmitter block, U0TX, accepts data written by the CPU or host and buffers the data in the UART0 TX Holding Register FIFO (U0THR). The UART0 TX Shift Register (U0TSR) reads the data stored in the U0THR and assembles the data to transmit via the serial output pin, TXD0.

The UART0 Baud Rate Generator block, U0BRG, generates the timing enables used by the UART0 TX block. The U0BRG clock input source is the APB clock (PCLK). The main clock is divided down per the divisor specified in the U0DLL and U0DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT.

The interrupt interface contains registers U0IER and U0IIR. The interrupt interface receives several one clock wide enables from the U0TX and U0RX blocks.

Status information from the U0TX and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR.

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U0INTR

INTERRUPT

U0IER

U0IIR

U0SCR

U0TX

U0THR U0TSR

U0BRG

U0DLL

U0DLM

U0RX

U0RBR U0RSR

U0FCR

U0LSR

NTXRDY

TXD0

NBAUDOUT

RCLK

NRXRDY

RXD0

PA[2:0]

PSEL

PSTB

PWRITE

PD[7:0]

PCLK

Fig 18. UART0 block diagram

APB

INTERFACE

U0LCR

DDIS

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Chapter 10: Universal Asynchronous Receiver/Transmitter 1 (UART1)

Rev. 01 — 12 January 2006 User manual

10.1 Features

• UART1 is identical to UART0 with the addition of a modem interface.

• UART1 contains 16 byte Receive and Transmit FIFOs.

• Register locations conform to ‘550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.

• Fractional baud rate generator with autobauding capabilities is built-in.

• Mechanism enables software and hardware flow control implementation.

• Standard modem interface signals are included, and flow control (auto-CTS/RTS) is

fully supported in hardware.

10.2 Pin description

Table 97: UART1 pin description

Pin Type Description

RXD1 Input Serial Input. Serial receive data.

TXD1 Output Serial Output. Serial transmit data.

CTS1 Input Clear To Send. Active LOW signal indicates if the external modem is ready to accept transmitted

data via TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[4]. State change information is stored in U1MSR[0] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).

DCD1 Input Data Carrier Detect. Active LOW signal indicates if the external modem has established a

communication link with the UART1 and data may be exchanged. In normal operation of the modem interface (U1MCR[4]=0), the complement value of this signal is stored in U1MSR[7]. State change information is stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).

DSR1 Input Data Set Ready. Active LOW signal indicates if the external modem is ready to establish a

communications link with the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[5]. State change information is stored in U1MSR[1] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).

DTR1 Output Data Terminal Ready. Active LOW signal indicates that the UART1 is ready to establish connection

with external modem. The complement value of this signal is stored in U1MCR[0].

RI1 Input Ring Indicator. Active LOW signal indicates that a telephone ringing signal has been detected by

the modem. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[6]. State change information is stored in U1MSR[2] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).

RTS1 Output Request To Send. Active LOW signal indicates that the UART1 would like to transmit data to the

external modem. The complement value of this signal is stored in U1MCR[1].

10.3 Register description

UART1 contains registers organized as shown in Table 76. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches.

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Table 98: UART1 register map

Name Description Bit functions and addresses Access Reset

U1RBR Receiver Buffer

U1THR Transmit Holding

U1DLL Divisor Latch LSB 8-bit Data R/W 0x01 0xE001 0000

U1DLM Divisor Latch MSB 8-bit Data R/W 0x00 0xE001 0004

U1IER Interrupt Enable

U1IIR Interrupt ID Reg. - - - - - - ABTO Int ABEO Int RO 0x01 0xE001 0008

U1FCR FIFO Control

U1LCR Line Control

U1MCR Modem Ctrl. Reg. CTSen RTSen - LoopBck. - - RTS DTR R/W 0x00 0xE001 0010

U1LSR Line Status

U1MSR Modem Status

U1SCR Scratch Pad Reg. 8-bit Data R/W 0x00 0xE001 001C

U1ACR Auto-baud Control

U1FDR Fractional Divider

U1TER TX. Enable Reg. TXEN - - - - - - - R/W 0x80 0xE001 0030

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

MSB LSB

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

8-bit Read Data RO NA 0xE001 0000

8-bit Write Data WO NA 0xE001 0000

- - - - - - En.ABTO En.ABEO R/W 0x00 0xE001 0004

En.CTS

Int

FIFOs Enabled - - IIR3 IIR2 IIR1 IIR0

RX Trigger - - - TX FIFO

DLAB Set

RX FIFO

Error

DCD RI DSR CTS Delta

---- - -ABTO

---- -Aut.Rstrt.ModeStart

- - - E.Modem

Stick

Break

TEMT THRE BI FE PE OE DR RO 0x60 0xE001 0014

Parity

MulVal DivAddVal

Even

Par.Selct.

Reserved[31:8] R/W 0x10 0xE001 0028

St.Int

Parity

Enable

DCD

En. RX

Lin.St. Int

Reset

No. of

Stop Bits

Trailing

Edge RI

[1]

value

Enable

THRE Int

RX FIFO

Reset

Word Length Select R/W 0x00 0xE001 000C

Delta DSR

IntClr

En. RX

Dat.Av.Int

FIFO

Enable

Delta

CTS

ABEO

IntClr

WO 0x00 0xE001 0008

RO 0x00 0xE001 0018

R/W 0x00 0xE001 0020

Philips Semiconductors

Address

Volume 1 Chapter 10: UART1

(DLAB=0)

(DLAB=1)

(DLAB=0)

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[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

Philips LPC2101, LPC2103, LPC2102 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Introduction

Chapter 1: General information

1.2 Features

1.3 Applications

1.4 Device information

1.5 Architectural overview

1.6 ARM7TDMI-S processor

1.7 On-chip flash memory system

1.8 On-chip Static RAM (SRAM)

1.9 Block diagram

2.1 Memory maps

Chapter 2: LPC2101/02/03 Memory addressing

2.2 LPC2101/02/03 memory re-mapping and boot block

2.2.1 Memory map concepts and operating modes

2.2.2 Memory re-mapping

2.3 Prefetch abort and data abort exceptions

Chapter 3: System control block

3.1 Summary of system control block functions

3.2 Pin description

3.3 Register description

3.4 Crystal oscillator

3.5 External interrupt inputs

3.5.1 Register description

3.5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)

3.5.3 Interrupt Wake-up register (INTWAKE - 0xE01F C144)

3.5.4 External Interrupt Mode register (EXTMODE - 0xE01F C148)

3.5.5 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)

3.6 Other system controls

3.6.1 System Control and Status flags register (SCS - 0xE01F C1A0)

3.7 Memory mapping control

3.7.1 Memory Mapping control register (MEMMAP - 0xE01F C040)

3.7.2 Memory mapping control usage notes

3.8 Phase Locked Loop (PLL)

3.8.1 Register description

3.8.2 PLL Control register (PLLCON - 0xE01F C080)

3.8.3 PLL Configuration register (PLLCFG - 0xE01F C084)

3.8.4 PLL Status register (PLLSTAT - 0xE01F C088)

3.8.5 PLL interrupt

3.8.6 PLL modes

3.8.7 PLL Feed register (PLLFEED - 0xE01F C08C)

3.8.8 PLL and Power-down mode

3.8.9 PLL frequency calculation

3.8.10 Procedure for determining PLL settings

3.8.11 PLL configuring examples

3.9 Power control

3.9.1 Register description

3.9.2 Power Control register (PCON - 0xE01F COCO)

3.9.3 Power Control for Peripherals register (PCONP - 0xE01F COC4)

3.9.4 Power control usage notes

3.10 Reset

3.10.1 Reset Source Identification Register (RSIR - 0xE01F C180)

3.11 APB divider

3.11.1 Register description

3.11.2 APBDIV register (APBDIV - 0xE01F C100)

3.12 Wake-up timer

3.13 Code security vs. debugging

4.1 Introduction

4.2 Operation

Chapter 4: Memory Acceleration Module (MAM)

4.3 MAM blocks

4.3.1 Flash memory bank

4.3.2 Instruction latches and data latches

4.3.3 Flash programming issues

4.4 MAM operating modes

4.5 MAM configuration

4.6 Register description

4.7 MAM Control register (MAMCR - 0xE01F C000)

4.8 MAM Timing register (MAMTIM - 0xE01F C004)

4.9 MAM usage notes

5.1 Features

5.2 Description

Chapter 5: Vectored Interrupt Controller (VIC)

5.3 Register description

5.4 VIC registers

5.4.1 Software Interrupt register (VICSoftInt - 0xFFFF F018)

5.4.2 Software Interrupt Clear register (VICSoftIntClear - 0xFFFF F01C)