Philips LF398N, LF298N, LF298FE, LF398D Datasheet

0 (0)

Philips Semiconductors Linear Products	Product specification


Sample-and-hold amplifiers	LF198/LF298/LF398

DESCRIPTION

The LF198/LF298/LF398 are monolithic sample-and-hold circuits which utilize high-voltage ion-implant JFET technology to obtain ultra-high DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6μs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offset drift. The wide bandwidth allows the

LF198 to be included inside the feedback loop of 1MHz op amps without having stability problems. Input impedance of 1010Ω allows high source impedances to be used without degrading accuracy.

P-channel junction FETs are combined with bipolar devices in the output amplifier to give droop rates as low as 5mV/min with a 1μF hold capacitor. The JFETs have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design guarantees no feedthrough from input to output in the hold mode even for input signals equal to the supply voltages.

Logic inputs are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS; differential threshold is

1.4V. The LF198/LF298/LF398 will operate from ±5V to ±18V supplies. They are available in 8-pin plastic DIP, 8-pin Cerdip, and 14-pin plastic SO packages.

FEATURES

•Operates from ±5V to ±18V supplies

•Less than 10μs acquisition time

•TTL, PMOS, CMOS compatible logic input

•0.5mV typical hold step at CH=0.01μF

•Low input offset

•0.002% gain accuracy

•Low output noise in hold mode

•Input characteristics do not change during hold mode

•High supply rejection ratio in sample or hold

•Wide bandwidth

PIN CONFIGURATIONS

FE, N Packages


V+	1		8	LOGIC
V+				LOGIC

OFFSET VOLTAGE	2		7	LOGIC REFERENCE
OFFSET VOLTAGE				LOGIC REFERENCE

INPUT	3		6	Ch

V±	4		5	OUTPUT


		TOP VIEW

D1 Package

INPUT	1		14	VOS Adj

NC	2		13	NC


V±	3		12	V+

NC	4		11	LOGIC

NC	5		10	LOGIC REF

NC	6		9	NC

OUTPUT	7		8	Ch
		TOP VIEW

NOTE:

1. SO and non-standard pinouts.

APPLICATION

•The LF198/LF298/LF398 are ideally suited for a wide variety of sample-and-hold applications, including data acquisition, analog-to-digital conversion, synchronous demodulation, and automatic test setup

ORDERING INFORMATION

DESCRIPTION	TEMPERATURE RANGE	ORDER CODE	DWG #

8-Pin Ceramic Dual In-Line Package (CERDIP)	-55°C to +125°C	LF198FE	0580A

14-Pin Plastic Small Outline (SO) Package	0 to +70°C	LF398D	0175D

8-Pin Ceramic Dual In-Line Package (CERDIP)	0 to +70°C	LF398FE	0580A

8-Pin Plastic Dual In-Line Package (DIP)	0 to +70°C	LF398N	0404B

8-Pin Ceramic Dual In-Line Package (CERDIP)	-25°C to +85°C	LF298FE	0580A

8-Pin Plastic Dual In-Line Package (DIP)	-25°C to +85°C	LF298N	0404B

August 31, 1994

879

853-0135 13721

Philips Semiconductors Linear Products	Product specification

Sample-and-hold amplifiers	LF198/LF298/LF398

FUNCTIONAL DIAGRAM

TYPICAL APPLICATIONS

OFFSET

V+

30k

V±

OUTPUT

INPUT

S/H

OUTPUT

ANALOG INPUT

LOGIC

300

SAMPLE 5V

LOGIC

REFERENCE

HOLD 0V

INPUT

HOLD

CAPACITOR

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNIT

Supply voltage

±18

Maximum power dissipation

T =25°C (still-air)3

F package

780

N package

1160

D package

1040

Operating ambient temperature range

LF198

-55 to +125

°C

LF298

-25 to +85

°C

LF398

0 to +70

°C

TSTG

Storage temperature range

-65 to +150

°C

VIN

Input voltage

Equal to

supply voltage

Logic-to-logic reference differential

+7, -30

voltage2

Output short-circuit duration

Indefinite

Hold capacitor short-circuit duration

sec

TSOLD

Lead soldering temperature (10sec max)

300

°C

NOTES:

1.The maximum junction temperature of the LF398 is 150°C. When operating at elevated ambient temperature, the packages must be derated based on the thermal resistance specified.

2.Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least 2V below the positive supply and 3V above the negative supply.

3.Derate above 25°C, at the following rates:

F package at 6.2mW/°C

N package at 9.3mW/°C

D package at 8.3mW/°C

August 31, 1994

880

+ 3 hidden pages