Philips LF398N, LF298N, LF298FE, LF398D Datasheet

Philips Semiconductors Linear Products Product specification

LF198/LF298/LF398Sample-and-hold amplifiers

879

August 31, 1994 853-0135 13721

DESCRIPTION

The LF198/LF298/LF398 are monolithic sample-and-hold circuits
which utilize high-voltage ion-implant JFET technology to obtain
ultra-high DC accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, DC gain accuracy is 0.002%
typical and acquisition time is as low as 6µs to 0.01%. A bipolar
input stage is used to achieve low offset voltage and wide
bandwidth. Input offset adjust is accomplished with a single pin and
does not degrade input offset drift. The wide bandwidth allows the
LF198 to be included inside the feedback loop of 1MHz op amps
without having stability problems. Input impedance of 10

10

Ω allows

high source impedances to be used without degrading accuracy.
P-channel junction FETs are combined with bipolar devices in the

output amplifier to give droop rates as low as 5mV/min with a 1µF
hold capacitor. The JFETs have much lower noise than MOS
devices used in previous designs and do not exhibit high
temperature instabilities. The overall design guarantees no
feedthrough from input to output in the hold mode even for input
signals equal to the supply voltages.

Logic inputs are fully differential with low input current, allowing
direct connection to TTL, PMOS, and CMOS; differential threshold is

1.4V. The LF198/LF298/LF398 will operate from ±5V to ±18V
supplies. They are available in 8-pin plastic DIP, 8-pin Cerdip, and
14-pin plastic SO packages.

FEATURES

•Operates from ±5V to ±18V supplies

•Less than 10µs acquisition time

•TTL, PMOS, CMOS compatible logic input

•0.5mV typical hold step at CH=0.01µF

•Low input offset

•0.002% gain accuracy

•Low output noise in hold mode

•Input characteristics do not change during hold mode

•High supply rejection ratio in sample or hold

•Wide bandwidth

PIN CONFIGURATIONS

FE, N Packages

D

1

Package

NOTE:

1. SO and

non-standard pinouts.

TOP VIEW

TOP VIEW

1

2

3

4 5

6

7

8

1

2

3

4

5

6

7 8

14

13

12

11

10

9

V+

OFFSET VOLTAGE

INPUT

V–

NC

V+

OUTPUT

LOGIC

INPUT

V–

LOGIC REF

NC

NC

NC

NC

NC

LOGIC

LOGIC REFERENCE

OUTPUT

V

OS

Adj

C

h

C

h

APPLICATION

•The LF198/LF298/LF398 are ideally suited for a wide variety of

sample-and-hold applications, including data acquisition,
analog-to-digital conversion, synchronous demodulation, and
automatic test setup

ORDERING INFORMATION

DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #

8-Pin Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C LF198FE 0580A
14-Pin Plastic Small Outline (SO) Package 0 to +70°C LF398D 0175D
8-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C LF398FE 0580A
8-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C LF398N 0404B
8-Pin Ceramic Dual In-Line Package (CERDIP) -25°C to +85°C LF298FE 0580A
8-Pin Plastic Dual In-Line Package (DIP) -25°C to +85°C LF298N 0404B

Philips Semiconductors Linear Products Product specification

LF198/LF298/LF398Sample-and-hold amplifiers

August 31, 1994

880

FUNCTIONAL DIAGRAM

OFFSET

INPUT

LOGIC

LOGIC

REFERENCE

HOLD

CAPACITOR

OUTPUT

30k

300

3

8

7

6

5

–

+

TYPICAL APPLICATIONS

OUTPUT

INPUT

LOGIC

ANALOG INPUT

SAMPLE 5V

HOLD 0V

S/H

3

8

7

6

5

4

1

V+

V–

C

h

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNIT

V

S

Supply voltage ±18 V
Maximum power dissipation

T

A

=25°C (still-air)

3

F package 780 mW
N package 1160 mW
D package 1040 mW

T

A

Operating ambient temperature range

LF198 -55 to +125 °C
LF298 -25 to +85 °C
LF398 0 to +70 °C

T

STG

Storage temperature range -65 to +150 °C

V

IN

Input voltage

Equal to

supply voltage

Logic-to-logic reference differential

voltage

2

+7, -30 V

Output short-circuit duration Indefinite
Hold capacitor short-circuit duration 10 sec

T

SOLD

Lead soldering temperature (10sec max) 300 °C

NOTES:

1. The maximum junction temperature of the LF398 is 150°C.

When operating at elevated ambient temperature, the packages must be derated

based on the thermal resistance specified.

2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least 2V
below the positive supply and 3V above the negative supply.

3. Derate above 25°C, at the following rates:

F package at 6.2mW/°C
N package at 9.3mW/°C
D package at 8.3mW/°C