Philips FTT1010-M-TG, FTT1010-M-IG, FTT1010-M-HG, FTT1010-M-EG Datasheet

IMAGE SENSORS

FTT1010-M

Frame Transf er CCD Image Sensor

Product specification 1999 September 21
File under Image Sensors

Philips
Semiconductors

TRAD

Philips Semiconductors Product specification

g

Frame Transfer CCD Image Sensor FTT1010-M

• 1-inch optical format

• 1M active pixels (1024H x 1024V)

• Progressive scan

• Excellent anti-blooming

• V ariable electr onic shuttering

• Square pixel structure

• H and V binning

• 100% optical fill factor

• High dynamic range (>72dB)
Description

• High sensitivity

• Low dark current and fixed pattern noise

• Low read-out noise

• Data rate up to 2 x 40 MHz

• Mirrored and split read-out

The FTT 1010-M is a monochrome progressive-scan frame-transfer
image sensor offering 1K x 1K pixels at 30 frames per second through
a single output buffer. The combination of high speed and a high
linear dynamic range (>12 true bits at room temperature without
cooling) makes this device the perf ect solution for high-end real time
medical X-ray, scientific and industrial applications. A second output
can either be used for mirrored images, or can be read out
simultaneously with the other output to double the frame rate. The
device structure is shown in figure 1.

Device structure

Optical size: 12.288 mm (H) x 12.288 mm (V)
Chip size: 14.572 mm (H) x 26.508 mm (V)
Pixel size: 12 µm x 12 µm
Active pixels: 1024 (H) x 1024 (V)
Total no. of pixels: 1072 (H) x 1030 (V)
Optical black pixels: Left: 20 Right: 20
Timing pixels: Left: 4 Right: 4
Dummy register cells: Left: 7 Right: 7
Optical black lines: Bottom: 6 Top: 6

Figure 1 - Device structure

1999 September 2

ZY

4

20

WX

Output
amplifier

7

6 black lines

Image Section

1024 active pixels

Storage Section

6 black lines

Output re

ister

1024
active
lines

4

20

2060
lines

71072 cells

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Architecture of the FTT1010-M

The FTT1010-M consists of a shielded storage section and an open
image section. Both sections are electronically the same and have
the same cell structure with the same properties. The only diff erence
between the two sections is the optical light shield.

The optical centres of all pixels in the image section form a square
grid. The charge is generated and integrated in this section. Output
registers are located below the storage section. The output amplifiers
Y and Z are not used in Frame Transfer mode and should be
connected as not-used amplifiers.

After the integration time the charge collected in the image section
is shifted to the storage section. The charge is read out line by line
through the lower output register.

IMAGE SECTION

The left and the right half of each output register can be controlled
independently. This enables either single or multiple read-out.

During vertical transpor t the C3 gates separate the pixels in the
register. The letters W, X, Y and Z are used to define the four
quadrants of the sensor. The central C3 gates of both registers are
part of the W and Z quadrants of the sensor.

Both upper and lower registers can be used for vertical binning.
Both registers also have a summing gate at each end that can be
used for horizontal binning. Figure 2 shows the detailed internal
structure.

Image diagonal (active video only)
Aspect ratio
Active image width x height
Pixel width x height
Geometric fill factor
Image clock pins
Capacity of each clock phase
Number of active lines
Number of black reference lines
Number of dummy black lines
Total number of lines
Number of active pixels per line
Number of overscan (timing) pixels per line
Number of black reference pixels per line
Total number of pixels per line

Storage width x height
Cell width x height
Storage clock phases
Capacity of each clock phase
Number of cells per line
Number of lines

17.38 mm
1:1

12.288 x 12.288 mm
12x12 µm

2

100%
A1, A2, A3, A4

2.5nF per pin
1024
2
4
1030
1024
8 (2x4)
40 (2x20)
1072

STORAGE SECTION

12.864 x 12.360 mm
12x12 µm

2

B1, B2, B3, B4

2.5nF per pin
1072
1030

2

2

OUTPUT REGISTERS

Output buffers (three-stage source foll ower)
Number of registers
Number of dummy cells per register
Number of register cells per register
Output register horizontal transport clock pins
Capacity of each C-clock phase
Overlap capacity between neighbouring C-clocks
Output register Summing Gates
Capacity of each SG
Reset Gate clock phases
Capacity of each RG

4 (one on each corner)
2 (one above, one below)
14 (2x7)
1072
C1, C2, C3
60pF per pin
20pF
4 pins (SG)
15pF
4 pins (RG)
15pF

1999 September 3

Philips Semiconductors Product specification

)

Frame Transfer CCD Image Sensor FTT1010-M

RD

RGRG

OUT_Z
(not used) (not used

SG: summing gate
OG: output gate
RG: reset gate

RD: reset dr ain

OUT_W

OG

SG

RG

RD

7 dummy

pixels

C3 C3 C3 C3 C3 C3 C3 C3 C3C3 C3

One Pixel

C3 C3 C3C3 C3 C3 C3C3 C3 C3 C3

20 black & 4

timing columns

C1C1SG C2OG C2 C2 C1 C2 C1 C2 C1 C2 C1 C2 C2C1 C1 C2 C1 C2 C1 C2 C1 C2 C1 SG OGC1 C3
A1 A1

A2
A3

A4

A1
A2
A3

A4

A1

A2
A3

A4

A1

A2
A3A3

A4

B2
B3
B4

A1

B1

B2
B3
B4

B1

B2
B3
B4

B1

B2
B3
B4

B1

C1C1C2 C2 C2 C1 C2 C1 C2C1 C3

column

1

6 black
lines

1K active
images lines

1K storage
lines

6 black lines

1K image 20 black & 4 timing

pixels

IMAGE

FT CCD

STORAGE

C1C2 C2 C1

C2 C1 C2 C2C1 C1

column

24 + 1

C3

column
24 + 1K

columns

A2
A3

A4

A1
A2
A3

A4

A1
A2
A3

A4

A1
A2
A3

A4

B1B1

B2
B3
B4

A1

B1

B2
B3
B4

B1

B2
B3
B4

B1

B2
B3
B4

B1

C2

C1

column

24 + 1K + 24

7 dummy

pixels

C1 C2

C1 SG

RD

OUT_Y

OUT_X

OG

RD

RG

RG

A1, A2, A3, A4: clocks of image section B1, B2, B3, B4: clocks of storage section C1, C2, C3: clocks of horizontal registers

Figure 2 - Detailed internal structure

1999 September 4

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Specifications

ABSOLUTE MAXIMUM RATINGS

GENERAL:
storage temperature
ambient temperature during operation
voltage between any two gates
DC current through any clock phase (absolute value)
OUT current (no short circuit protection)

VOLTAGES IN RELAT ION TO VPS:
VNS, SFD, RD
VCS, SFS
all other pins

VOLTAGES IN RELAT ION TO VNS:
SFD, RD
VCS, SFS, VPS
all other pins

2

VNS
VPS
SFD
SFS
VCS
OG
RD

DC CONDITIONS

3

N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain

1

MIN. MAX. UNIT

-55

-40

-20

-0.2
0

-0.5

-8

-5

-15

-30

-30

+80
+60
+20
+2.0
10

+30
+5
+25

+0.5
+0.5
+0.5

°C
°C
V
µA
mA

V
V
V

V
V
V

MIN. [V] TYPICAL [V] MAX . [V] MAX. [m A]

18
1
16

-

-5
4
13

24
3
20
0
0
6

15.5

28
7
24

­3
8
18

15
15

4.5
1

-

-

-

AC CLOCK LEVEL CONDITIONS

2

MIN. TYPICAL MAX. UNIT

IMAGE CLOCKS:
A-clock amplitude during integration and hold
A-clock amplitude during vertical trans port (duty cycle=5/8)
A-clock low level
Charge Reset (CR) level on A-clock

5

4

8
10

-5

10
14
0

-5

V
V
V
V

STORAGE CLOCKS:
B-clock amplitude during hold
B-clock amplitude during vertical trans port (duty cycle=5/8)

8
10

10
14

V
V

OUTPUT REGISTER CLOCKS:
C-clock amplitude (duty cycle during hor. trans port = 3/6)
C-clock low level
Summing Gate (SG) amplitude
Summing Gate (SG) low level

4.75
2

5

3.5
10

3.5

5.25
10

V
V
V
V

OTHER CLOCKS:
Reset Gate (RG) amplitude
Reset Gate (RG) low level
Charge Reset (CR) pulse on Nsub

1

During Charge Reset it is allowed to exceed maximum rating levels (see note5).

2

All voltages in relation to SFS.

3

To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values.

4

Three-level cloc k is preferred for maximum charge; the s wing during vertical transport should be 4V higher than the voltage during integration.

A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed.

5

Charge Reset can be achieved in two ways:

5

5
0

10
3
10

10
10

V
V
V

• The typical CR level is applied to all image clocks simultaneously (preferred).

• The typical A-clock low le vel is applied to all image cloc ks; f or proper CR, an additional Charge Reset pulse on VNS is required. This will also aff ect
the charge handling capacity in the storage areas.

1999 September 5

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Timing diagrams (for default operation)

AC CHARACTERISTICS MIN. TYPICAL MAX. UNIT

Horizontal frequency (1/Tp)
Vertical frequency
Charge Reset (CR) time
Rise and fall times: image clocks (A)

1

Tp = 1 clock period

2

Duty cycle = 50% and phase shift of the C clocks is 120 degrees.

1

storage clocks (B)
register clocks (C)
summing gate (SG)
reset gate (RG)

0
0
2
10

2

10
3
3
3

18
450
5
20
20
5
5
5

40
1000

1/6 Tp
1/6 Tp
1/6 Tp

MHz
kHz
µs
ns
ns
ns
ns
ns

Line Timing

SSC

B1

B2

B3

B4

CR

AHigh

VD

BLC

Pixel Timing

SSC

C1

C2

C3

SG

RG
Tp = 1 clock period = 1 / 18MHz = 55.56ns

Pixel output sequence: 7 dumm y, 20 black, 4 timing, 1024 active, 4 timing, 20 black Line Time: 1184 x Tp = 65.7µs
* During AHigh = H the phiA high level is increased from 10V to 14V

H

L

H

L

H

L

H

L

H

L

H

L

H

*

L

H

L

H

L

30Tp

19Tp

14Tp

15Tp

24Tp

Tp2

34Tp

H

L

H

L

H

L

H

L

H

L

H

L

105Tp

25Tp

15Tp

15Tp

Tp101

Tp105

141Tp

1079 pixels

1Tp

Tp / 6

VD: Frame pulse
CR: Charge Reset
BLC: Black Level Clamp
B1 to B4: Vertical storage clocks

Figure 3 - Line and pixel timing diagrams

1999 September 6

C1 to C3: Horizontal register clocks
SSC: Start-Stop C-clocks
SG: Summing gate
RG: Reset gate

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Frame Timing

Sensor Output

SSC

A1, A2, A3

A4

B1

B2, B3, B4

CR

Ahigh

VD

BLC

EXT. SHUTTER

Frame Shift Timing

*

A1

A2

A3

A4

B1

B2

B3

B4

1019 10241023102210211020

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

Integration Time

Black

BB BB12

Frame Shift

Tframe shift = 1027 x 8 x N clock periods

B

1

43

1

8 phases correspond with 2 line shifts

Horizontal freq.

N = , for example: = 5

Ver tical freq. x 8

18MHz

450kHz x 8

VD: Frame pulse
CR: Charge Reset
BLC: Black Level Clamp
A1 to A4: Vertical image clocks

Figure 4 - Frame timing diagrams

1999 September 7

B1 to B4: Vertical storage clocks
C1 to C3: Horizontal register clocks
SSC: Start-Stop C-clocks
SG: Summing gate
RG: Reset gate

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Line timing

SSC

B1

B2

B3

Pixel timing

B4

—> time

Y / Div. : 10V (B1, B2, B3, B4); 5V (SSC)

Figure 5 - Vertical readout

C1

C2

C3

SG

RG

Y / Div. : 5V (C1, C2, C3); 10V (SG, RG)

Figure 6 - Start horizontal readout

1999 September 8

—> time

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Performance

The test conditions for the perfo rmance characteristics are as follows:

• All values are measured using typical operating conditions.

• VNS is adjusted as low as possible while maintaining proper
Ver tical Anti-Blooming.

• Sensor temperature = 60°C (333K).

• Horizontal transport frequency = 18MHz.

LINEAR OPERATION MIN. TYPICAL MAX. UNIT

Linear dynamic range

1

Charge Transfer Efficiency 2 vertical
Charge Transfer Efficiency

2

horizontal

Image lag

3

Smear
Resolution (MTF) @ 42 lp/mm
Responsivity
Quantum efficiency @ 530 nm
White Shading
Random Non-Uniformity (RNU)

4

5

VNS required for good Vertical Anti-Blooming (VAB)
Power dissipation at 15 frames/s

• V ertical transport frequency = 450kHz (unless specified otherwise).

• Integration time = 10ms (unless specified otherwise).

• The light source is a 3200K lamp with neutral density filters and
a 1.7mm thick BG40 infrared cut-off filter. For Linear Operation
measurements, a temperature conv ersion filter (Melles Griot type
no. 03FCG261, -120 mired, thickness: 2.5mm) is applied.

4200:1

0.999995

0.999999

65
180
25

18

-39

250
30

0.3
24
410

0
0

2.5
5
28

%
dB
%
kel/lux·s
%
%
%
V
mW

1

Linear dynamic range is defined as the ratio of Q

2

Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer.

3

Smear is defined as the ratio of 10% of the vertical transport time to the integration time. It indicates how visible a spot of 10% of the image

to read-out noise (the latter reduced by Correlated Double Sampling).

lin

height would become.

4

White Shading is defined as the ratio of the one-σ value of the pixel output distribution expressed as a percentage of the mean value output
(low pass image).

5

RNU is defined as the ratio of the one-σ value of the highpass image to the mean signal value at nominal light.

Linear Dynamic Range

20,000
18,000

35ºC

45ºC

55ºC

0

0 5 10 15 20 25 30 35 40

Hor. Frequency (MHz)

LDR

16,000
14,000
12,000
10,000

8,000
6,000
4,000
2,000

Figure 7 - Typical Linear dynamic range vs. horizontal read-out frequency and sensor temperature

1999 September 9

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Maximum Read-out Speed

80

2 outputs

70

60

50

40

1 output

Images/sec.

30

20

10

0

0 102030405060708090100

Integration time (ms)

Figure 8 - Maximum number of images/second versus integration time

Quantum Efficiency

30

25

20

15

10

Quantum efficiency (%)

5

0

400 450 500 550 600 650 700 750 800

Wavelength (nm)

Figure 9 - Quantum efficiency versus wavelength

1999 September 10

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

LINEAR/SATURATION MIN. TYPICAL MAX. UNIT

Full-well capacity saturation level (Qmax)
Full-well capacity shading (Qmax, shading)
Full-well capacity linear operation (Qlin)
Charge handling capacity

4

1

2

3

Overexposure 5 handling

1

Qmax is determined from the lowpass filtered image.

2

Qmax, shading is the maximum difference of the full-well charges of all pixels, relative to Qmax.

3

The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The evaluation test guarantees 97% linearity.

4

Charge handling capacity is the largest charge packet that can be transported through the register and read-out through the output buffer.

5

Overexposure over entire area while maintaining good Vertical Anti-Blooming (VAB). It is tested by measur ing the dark line.

250

200

100

500
10
350
600
200

600
50

kel.
%
kel.
kel.
x Qmax level

Charge Handling vs. Integration/Transport Voltage

600

10V/14V

500

400

9V/13V

Output Signal (kel.)

300

200

100

8V/12V

0

123456

Exposure (arbitrary units)

Figure 10 - Charge handling versus integration/transport voltage

1999 September 11

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

OUTPUT BUFFERS MIN. TYPICAL MAX. UNIT

Conversion factor
Mutual conversion factor matching (∆ACF)

1

Supply current
Bandwidth
Output impedance buffer (R

1

Matching of the four outputs is specified as ∆ACF with respect to reference measured at the operating point (Q

= 3.3kΩ, C

load

= 2pF)

load

68

0
4
110
400

DARK CONDITION MIN. TYPICAL MAX. UNIT

Dark current level @ 30° C
Dark current level @ 60° C
Fixed Pattern Noise

1

(FPN) @ 60° C

RMS readout noise @ 9MHz bandwidth after CDS

1

FPN is the one-σ value of the highpass image.

20

0.3
15
25

12
2

30

0.6
25
30

µV/el.
µV/el.
mA
MHz

Ω

/2).

lin

2

pA/cm

2

nA/cm
el.
el.

1000

)

2

100

10

Dark Current (pA/cm

1

0 102030405060

Dark Current

Temp. (oC)

Figure 11 - Dark current versus temperature

1999 September 12

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Application information

Current handling

One of the purposes of VPS is to drain the holes that are generated
during exposure of the sensor to light. Free electrons are either
transported to the VRD connection and, if excessive (from over­exposure), free electrons are drained to VNS. No current should
flow into any VPS connection of the sensor . During high ov erexposure
a total current 10 to 15mA through all VPS connections together
may be expected. The PNP emitter follower in the circuit diagram
(figure 12) serves these current requirements.

VNS drains superfluous electrons as a result of overexposure. In
other words, it only sinks current. During high overexposure a total
current of 10 to 15mA through all VNS connections together ma y be
expected. The NPN emitter follower in the circuit diagram meets
these current requirements. The clamp circuit, consisting of the diode
and electrolytic capacitor, enables the addition of a Charge Reset
(CR) pulse on top of an otherwise stable VNS v oltage . To protect the
CCD, the current resulting from this pulse should be limited. This
can be accomplished by designing a pulse generator with a rather
high output impedance.

Decoupling of DC voltages

All DC voltages (not VNS, which has additional CR pulses as
described above) should be decoupled with a 100nF decoupling
capacitor. This capacitor must be mounted as close as possible to
the sensor pin. Further noise reduction (by bandwidth limiting) is
achieved by the resistors in the connections between the sensor
and its voltage supplies. The electrons that build up the charge
packets that will reach the floating diffusions only add up to a small
current, which will flow through VRD . Theref ore a large series resistor
in the VRD connection may be used.

The CCD output buffer can easily be destroyed by ESD. By using
this emitter follower, this danger is suppressed; do NOT reintroduce
this danger by measuring directly on the output pin of the sensor
with an oscilloscope probe. Instead, measure on the output of the
emitter follower. Slew rate limitation is avoided by avoiding a too­small quiescent current in the emitter follower; about 10mA should
do the job. The collector of the emitter follow er should be decoupled
properly to suppress the Miller effect from the base-collector
capacitance.

A CCD output load resistor of 3.3kΩ typically results in a bandwidth
of 110MHz. The bandwidth can be enlarged to about 130MHz by
using a resistor of 2.2kΩ instead, which, however, also enlarges the
on-chip power dissipation.

Device protection

The output buffers of the FTT1010-M are likely to be damaged if
VPS rises above SFD or RD at any time. This danger is most realistic
during power-on or power-off of the camera. The RD voltage should
always be lower than the SFD voltage.

Never exceed the maximum output current. This may damage the
device permanently. The maximum output current should be limited
to 10mA. Be especially a ware that the output buffers of these image
sensors are very sensitive to ESD damage.

Because of the fact that our CCDs are built on an n-type substrate,
we are dealing with some parasitic npn transistors. To avoid activ ation
of these transistors during switch-on and switch-off of the camera,
we recommend the application diagram of figure 12.

Outputs

T o limit the on-chip po wer dissipation, the output buff ers are designed
with open source outputs. Outputs to be used should therefore be
loaded with a current source or more simply with a resistance to
GND. In order to prevent the output (which typically has an output
impedance of about 400Ω) from bandwidth limitation as a result of
capacitive loading, load the output with an emitter follo wer b uilt from
a high-frequency transistor. Mount the base of this transistor as close
as possible to the sensor and keep the connection between the
emitter and the next stage short.

Unused sections

To reduce power consumption the following steps can be taken.
Connect unused output register pins (C1...C3, SG, OG) and unused
SFS pins to zero Volts.

More information

Detailed application information is provided in the application note
AN01 entitled ‘Camera Electronics for the mK x nK CCD Image
Sensor Family’.

1999 September 13

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Device Handling

An image sensor is a MOS device which can be destroy ed by electro­static discharge (ESD). Therefore, the device should be handled
with care.

Always store the de vice with short-circuiting clamps or on conductive
foam. Alwa ys s witch off all electric signals when inserting or removing
the sensor into or from a camera (the ESD protection in the CCD
image sensor process is less effective than the ESD protection of
standard CMOS circuits).

Being a high quality optical device, it is important that the cover
glass remain undamaged. When handling the sensor , use fingercots.

VSFD

CR pulse

0

27

Ω

BAT74
Schottky!

Ω

15
BAT74
Schottky!

10k

Ω

100nF

-

+

BAT74

BAT74

BC
850C

0.5-1mA

BC
850C

0.5-1mA

0.5-1mA

BC
860C

1uF 100nF

2mA

100nF

100nF

When cleaning the glass we recommend using ethanol (or possibly
water). Use of other liquids is strongly discouraged:

• if the cleaning liquid evaporates too quickly, rubbing is likely to
cause ESD damage.

• the cover glass and its coating can be damaged by other liquids.

Rub the window carefully and slowly.
Dry rubbing of the window may cause electro-static charges or

scratches which can destroy the device.

keep short

VNS

SFD

VPS

VRD

<10mm! keep short!

10k

Ω

Ω

BFR
92A

output for
preprocessing

10mA

OUT

VCS

VOG

100 Ω

3.3k

Ω

100nF

10k

100nF

100nF

1k

Ω

<7pF!

Figure 12 - Application diagram to protect the FTT1010-M

1999 September 14

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Pin configuration

The FTT1010-M is mounted in a Pin Grid Array (PGA) package with
76 pins in a 15x13 grid of 40.00 x 40.00 mm2. The position of pin A1

The clock phases of quadrant W are internally connected to X, and
the clock phases of Y are connected to Z.

is marked with a gold dot on top of the package.

Symbol Name Pin # W Pin # X Pin # Y Pin # Z

VNS
VNS
VNS
VNS
VNS
VPS
SFD
SFS
VCS
OG
RD
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
SG
RG
OUT
NC

N substrate
N substrate
N substrate
N substrate
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain
Image Clock (Phase 1)
Image Clock (Phase 2)
Image Clock (Phase 3)
Image Clock (Phase 4)
Storage Clock (Phase 1)
Storage Clock (Phase 2)
Storage Clock (Phase 3)
Storage Clock (Phase 4)
Register Clock (Phase 1)
Register Clock (Phase 2)
Register Clock (Phase 3)
Summing Gate
Reset Gate
Output
Not connected

A12
D11
E11
E12

­C11
A13
A10
A11
B13
B12

-

-

-

­D13
C12
D12
C13

B9
B8
A8

B10

A9

B11

B7

A3
B2
D3
E2
E3
C3
A1
B5
A4
B1
B3

D1
C2
D2
C1
A6
A7
B6
A2
A5
B4

J2
F3

-

-

­G3
J1
J4
J3
H1
H2

-

-

-

-

F1
G2
F2
G1

-

-

-

­H5
H6
J6
H4
J5
H3
H7

F11
H12
J11

-

-

G11

J13

H9

J10
H13
H11

F13
G12

F12
G13

-

-

-

­J8
J7

H8

J12

J9

H10

SFD VNS VCS

J
H
G
F

E
D
C
B
A

SG

VNS

A2

A4

A3

A1

VNS VNS

B1 B3

B4

B2

OG RD OUT SG C1

SFD

VNS

RG C2

SFS

VPS

VNS

Z

W

B4

B1

VNS

VPS

VCS SFS RG C3

C1

C3 OG RD OUT

NC

TOP

IMAGE

STORAGE

FTT1010-M

NC

C2

C2

C2

C1

Y

X

B4 B1

SFS

C3 OGRDOUT

RG

SFSRGC3

Figure 13 - FTT1010-M pin configuration (top view)

VNS

VPS

VNS

VNS

VPS

VNS

VNS

12345678910111213

SFDVNSVCS

OGRDOUTSG

A4

A2

A1A3

J
H
G
F

E

B3

B1

B2

B4

D
C
B

SFDVNSVCS

SGC1

A

12345678910111213

1999 September 15

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FTT1010-M

Pack age inf ormation

Top cover glass to top chip 2.4 ± 0.25

Chip - bottom package 1.7 ± 0.15

SENSOR CRYSTAL

COVER GLASS

A ZONE

8.9

Chip - cover glass 1.3 ± 0.20

Cover glass 1.0 ± 0.05

Image sensor chip

0.33

±

23

INDEX
MARK
PIN 1

TOP VIEW

26

±

0.15
40 ± 0.40

STAND-OFF PIN

BOTTOM VIEW

(2.54)

0.40

±

40

0.10

±

20

0.15

±

1.27

0.46 ± 0.05

± 0.20

30.48

1.4 / 100

COVER GLASS

0.15

±

4.57

A is the center of the image area.
Position of A:
26 ± 0.15 to left edge of package
20 ± 0.10 to bottom of package

Angle of rotation: less than ± 1
Sensor flatness: < 7 µm (P-V)

Cover glass: Corning 7059
Thickness of cover glass: 1.00 ± 0.05
Refractive index: nd = 1.53
Single sided AR coating inside (430-660 nm)

0

35.56 ± 0.20

Figure 14 - Mechanical drawing of the PGA package of the FTT1010-M

1999 September 16

All drawing units are in mm

Order codes

The sensors can be ordered using the following codes:

FTT1010-M sensors

Description Quality Grade Order Code

FTT1010-M/TG
FTT1010-M/EG
FTT1010-M/IG
FTT1010-M/HG

You can contact the Image Sensors division of Philips
Semiconductors at the following address:

Philips Semiconductors
Image Sensors
Internal Postbox WAG-05
Prof. Holstlaan 4
5656 AA Eindhoven
The Netherlands

phone +31 - 40 - 27 44 400
fax +31 - 40 - 27 44 090

www.semiconductors.philips.com/imagers/

Test grade
Economy grade
Industrial grade
High grade

9922 157 35031
9922 157 35051
9922 157 35021
9922 157 35011

Philips
Semiconductors

Philips reserves the right to change any information contained herein without notice. All information furnished by Philips is believed to be accurate. © Philips Electronics N.V. 1999

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