INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT93
4-bit binary ripple counter
Product specification |
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December 1990 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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4-bit binary ripple counter |
74HC/HCT93 |
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FEATURES
·Various counting modes
·Asynchronous master reset
·Output capability: standard
·ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT93 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT93 are 4-bit binary ripple counters. The devices consist of four master-slave flip-flops internally connected to provide a
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
divide-by-two section and a divide-by-eight section. Each section
has a separate clock input (CP0 and
CP1) to initiate state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes.
A gated AND asynchronous master reset (MR1 and MR2) is provided which overrides both clocks and resets (clears) all flip-flops.
Since the output from the divide-by-two section is not internally connected to the succeeding stages,
the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be
connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8 and 16 are performed at the Q0, Q1, Q2 and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input
CP1.
Simultaneous frequency divisions of 2, 4 and 8 are available at the Q1, Q2 and Q3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLH |
propagation delay |
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0 to Q0 |
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12 |
15 |
ns |
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CP |
CL = 15 pF; VCC = 5 V |
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fmax |
maximum clock frequency |
100 |
77 |
MHz |
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CI |
input capacitance |
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3.5 |
3.5 |
pF |
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CPD |
power dissipation capacitance per package |
notes 1 and 2 |
22 |
22 |
pF |
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Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF; VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC - 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 |
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Philips Semiconductors |
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Product specification |
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4-bit binary ripple counter |
74HC/HCT93 |
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PIN DESCRIPTION |
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PIN NO. |
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SYMBOL |
NAME AND FUNCTION |
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1 |
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1 |
clock input 2nd, 3rd and 4th section (HIGH-to-LOW, edge-triggered) |
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CP |
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2, 3 |
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MR1, MR2 |
asynchronous master reset (active HIGH) |
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4, 6, 7, 13 |
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n.c. |
not connected |
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5 |
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VCC |
positive supply voltage |
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10 |
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GND |
ground (0 V) |
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12, 9, 8, 11 |
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Q0 to Q3 |
flip-flop outputs |
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14 |
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clock input 1st section (HIGH-to-LOW, edge-triggered) |
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CP |
0 |
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Fig.1 Pin configuration. |
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Fig.2 Logic symbol. |
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Fig.3 IEC logic symbol. |
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December 1990 |
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