Philips 74HCT9015U, 74HCT9015N, 74HCT9015D, 74HC9015U, 74HC9015PW Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT9015

Nine wide Schmitt trigger buffer/line driver

Product specification			December 1990
Supersedes data of March 1988
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
Nine wide Schmitt trigger buffer/line driver	74HC/HCT9015

FEATURES

·Schmitt trigger action on all data inputs

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. These inputs transform slowly changing input signals into sharply defined jitter-free output signals.

The “9015” is identical to the “9014” but has non-inverting inputs.

SYMBOL	PARAMETER	CONDITIONS		TYPICAL		UNIT
			HC		HCT
tPHL/ tPLH	propagation delay An to Yn	CL = 15 pF; VCC = 5 V	12		13	ns
CI	input capacitance		3.5		3.5	pF
CPD	power dissipation capacitance per buffer	notes 1 and 2	30		32	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

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Philips Semiconductors														Product specification
Nine wide Schmitt trigger buffer/line driver													74HC/HCT9015
PIN DESCRIPTION
PIN NO.		SYMBOL					NAME AND FUNCTION
1, 2, 3, 4, 5, 6, 7, 8, 9		A0 to A8					data inputs
10		GND					ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12, 11		Y0 to Y8					data outputs
20		VCC					positive supply voltage
		page	A	0				Y 0				page					19
		1	A	1				Y 1		19		1
		2								18		2			18
			A	2				Y 2
		3								17		3					17
			A	3				Y 3
		4								16		4				16
			A	4				Y 4
		5								15		5				15
			A	5				Y 5
		6								14		6				14
			A	6				Y 6
		7								13		7				13
			A	7				Y 7
		8								12		8				12
			A	8				Y 8
		9								11		9				11
							MBA016							MBA013
Fig.1 Pin configuration.		Fig.2			Logic symbol.							Fig.3		IEC logic symbol.

December 1990

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