Philips 74HCT7731N, 74HCT7731D, 74HC7731N, 74HC7731D Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT7731

Quad 64-bit static shift register

Product specification			September 1993
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
Quad 64-bit static shift register	74HC/HCT7731

FEATURES

∙Frequency range DC to 100 MHz.

∙Separate serial data inputs

∙Cascadable

∙Functionally compatible with HEF 4731

∙Includes recycling mode

∙Direct shift out

∙Output capability: Standard

∙ICC category: LSI.

APPLICATIONS

∙Data storage

∙Delay line.

GENERAL DESCRIPTION

The HC/HCT7731 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A.

The HC/HCT7731 are quad 64-bit static shift registers with a recycling mode. Each register has separate data inputs Da to Dd, clock inputs CPa to CPd and data outputs Qa to Qd. Data shifts one place towards the output, each LOW to HIGH transition of the clock pulse. Each recycling mode input controls two registers RECab for registers A and B and RECcd for registers C and D. When the REC input is HIGH, the device is in the recycling mode and data at the output is shifted back into the input of the register, so after 64 clock pulses the contents of a register is again in its original position. This enables the user to tap off data from any position. When the REC input is LOW external data can be shifted in.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.

	SYMBOL	PARAMETER	CONDITIONS	TYP.		UNIT
				HC	HCT
	tPHL/tPLH	propagation delay	CL = 15 pF;	15	20	ns
		CPa-d to Qa-d	VCC = 5 V
	fmax	maximum clock		100	100	MHz
		frequency
	CI	input capacitance		3.5	3.5	pF
	CPD	power dissipation	notes 1, 2	58	61	pF
		capacitance per register	and 3

Notes

1. CPD is used to determine the dynamic power dissipation (PD in μW):

PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC) where:

fi = input frequency in MHz. fo = output frequency in MHz.

VCC = supply voltage in V.

CL = output load capacitance in pF. Ipull-up = pull-up currents in μA.

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V.

3.See also power dissipation information.

ORDERING INFORMATION

EXTENDED TYPE		PACKAGE
NUMBER	PINS	PIN POSITION	MATERIAL	CODE
74HC/HCT7731N	16	DIL	plastic	SOT38Z
74HC/HCT7731D	16	SO16	plastic	SOT109A

September 1993

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	Philips Semiconductors							Product specification
	Quad 64-bit static shift register						74HC/HCT7731
	PINNING
	SYMBOL	PIN	DESCRIPTION
	Qa to Qd	1, 7, 9, 15	data outputs		handbook, halfpage
	CPa to CPd	2, 6, 10, 14	clock inputs		Q a	1		16	VCC
	Da to Dd	3, 5, 11, 13	data inputs		CP a				Q d
						2		15
	RECab, RECcd	4, 12	recycled enable input						CP d
					D a	3		14
	GND	8	ground (0 V)
									D d
					REC ab	4		13
	VCC	16	positive supply				7731
					D b	5		12	RECcd
									D c
					CP b	6		11
					Q b				CP c
						7		10
									Q c
					GND	8		9
							MBA341
					Fig.1		Pin configuration.

3	D a
				MUX			64 - BIT		Q a	1
2	CP a						STATIC SHIFT
							REGISTER
4	REC ab
5	D b
				MUX			64 - BIT		Q b	7
6	CP b						STATIC SHIFT
							REGISTER
11	Dc
				MUX			64 - BIT		Q c	9
10	CPc						STATIC SHIFT
							REGISTER
12	RECcd
13	D d
				MUX			64 - BIT		Qd	15
14	CP d						STATIC SHIFT
							REGISTER
								MBA342

Fig.2 Functional diagram.

September 1993

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