Philips 74HCT75N, 74HCT75DB, 74HCT75D, 74HC75U, 74HC75PW Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT75

Quad bistable transparent latch

Product specification			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
Quad bistable transparent latch	74HC/HCT75

FEATURES

·Complementary Q and Q outputs

·VCC and GND on the centre pins

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT75 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT75 have four bistable latches. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE1-2 and LE3-4). When LEn-n is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEn-n is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEn-n will be stored in the latches. The latched outputs remain stable as long as the LEn-n is LOW.

SYMBOL		PARAMETER				CONDITIONS	TYPICAL		UNIT
							HC	HCT
tPHL/ tPLH	propagation delay					CL = 15 pF; VCC = 5 V
							11	12	ns
	nD to nQ, nQ
	LEn-n to nQ, nQ						11	11	ns
CI	input capacitance						3.5	3.5	pF
CPD	power dissipation capacitance per latch					notes 1 and 2	42	42	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where: fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs CL = output load capacitance in pF

VCC = supply voltage in V

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC -1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

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Philips Semiconductors							Product specification
Quad bistable transparent latch							74HC/HCT75
PIN DESCRIPTION
PIN NO.	SYMBOL					NAME AND FUNCTION
1, 14, 11, 8						complementary latch outputs
	1Q		to 4Q
2, 3, 6, 7	1D to 4D					data inputs
4	LE3-4					latch enable input, latches 3 and 4 (active HIGH)
5	VCC					positive supply voltage
12	GND					ground (0 V)
13	LE1-2					latch enable input, latches 1 and 2 (active HIGH)
16, 15, 10, 9	1Q to 4Q					latch outputs

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

December 1990

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