Philips 74HCT74U, 74HCT74PW, 74HCT74NB, 74HCT74N, 74HCT74DB Datasheet
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DATA SH EET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Feb 23
INTEGRATED CIRCUITS
74HC/HCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
1998 Feb 23 2
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
FEATURES
• Output capability: standard
• ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT74 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (
SD) and reset (RD) inputs; also complementary Q and
Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC= 5 V
nCP to nQ, n
Q1415ns
n
S
D
to nQ, nQ1518ns
n
R
D
to nQ, nQ1618ns
f
max
maximum clock frequency 76 59 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per flip-flop notes 1 and 2 24 29 pF
1998 Feb 23 3
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
ORDERING INFORMATION
PIN DESCRIPTION
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
74HC(T)74N DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC(T)74D SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HCT74DB SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
74HCT74PW TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
PIN NO. SYMBOL NAME AND FUNCTION
1, 13 1
RD, 2R
D
asynchronous reset-direct input (active LOW)
2, 12 1D, 2D data inputs
3, 11 1CP, 2CP clock input (LOW-to-HIGH, edge-triggered)
4, 10 1
SD, 2S
D
asynchronous set-direct input (active LOW)
5, 9 1Q, 2Q true flip-flop outputs
6, 8 1
Q, 2Q complement flip-flop outputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
1998 Feb 23 4
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
Fig.4 Functional diagram.
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition
Q
n+1
= state after the next LOW-to-HIGH CP transition
INPUTS OUTPUTS
S
D
R
D
CP D Q Q
LHXXHL
HLXXLH
LLXXHH
INPUTS OUTPUTS
S
D
R
D
CP D Q
n+1
Q
n+1
HH↑LL H
HH↑HH L
Fig.5 Logic diagram (one flip-flop).
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