Philips 74HCT7273 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74HCT7273
Octal D-type flip-flop with reset;
positive edge-trigger; open drain
outputs
Product specification
File under Integrated Circuits, IC06
1999 Oct 01
Philips Semiconductors Product specification
Octal D-type flip-flopwith reset; positive
edge-trigger; open drain outputs
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
Exceeds 2000 V
MM EIA/JESD22-A115-A
Exceeds 200 V
• Ideal buffer for MOS
microprocessor or memory
• Eight positive edge-triggered
D-type flip-flops
• Common clock and master reset
• Output capability: standard (open
drain)
• ICC category: MSI.
DESCRIPTION
The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible
with Low power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no 7A.
The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common Clock (CP)andMaster Reset (MR) inputs
load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Qn) of the flip-flop.
ALOWlevelontheMRinputforcesalloutputsLOW,independentlyoftheclock
or data inputs.
The device is useful for applications requiring true outputs only and clock and
master reset inputs that are common to all storage elements.
The 74HCT7273 has open-drain N-outputs, which are clamped by a diode
connected to VCC. When a HIGH is clocked in the flip-flop, the output comes in
the high-impedance OFF-state. The output may now be pulled to any voltage
betweenGND and V
or HIGH-to-LOW level shifter. For digital operation and OR-tied output
applications, the device must have a pull-up resistor to establish a logic HIGH
level.
74HCT7273
.This allows the device to be used asa LOW-to-HIGH
Omax
QUICK REFERENCE DATA
Ground = 0 V; T
=25°C; tr=tf= 6.0 ns.
amb
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PZL/tPLZ
f
max
C
I
C
PD
propagation delay CL= 50 pF; VCC= 4.5 V
CP to Q
MR to Q
n
n
16 ns
23 ns
maximum clock frequency 56 MHz
input capacitance 3.5 pF
power dissipation capacitance CL= 50 pF; f = 1 MHz; notes 1 and 2 37 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
= input frequency in MHz;
f
i
2
× fi+ ∑ (CL× V
CC
2
× fo)+∑(V
CC
2
/RL) × duty factor LOW where:
0
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
RL= pull-up resistor in MΩ;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC− 1.5 V.
1999 Oct 01 2
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
FUNCTION TABLE
See note 1.
INPUTS OUTPUTS
OPERATING MODES
MR CP D
Reset (clear) L X X L
Load ‘1’ H ↑ hZ
Load ‘0’ H ↑ lL
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level.
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
X = don’t care;
↑ = LOW-to-HIGH CP transition.
74HCT7273
n
Q
n
ORDERING INFORMATION
OUTSIDENORTH
AMERICA
74HCT7273D 74HCT7273D −40 to +125 °C 20 SO plastic SOT163-1
74HCT7273N 74HCT7273N 20 DIP plastic SOT146-1
NORTH AMERICA
TEMPERATURE
RANGE
PINS PACKAGE MATERIAL CODE
PACKAGE
1999 Oct 01 3
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
PINNING
PIN SYMBOL DESCRIPTION
1
2, 5, 6, 9, 12, 15, 16, 19 Q
3, 4, 7, 8, 13, 14, 17, 18 D
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge triggered)
20 V
handbook, halfpage
MR
Q
D
D
Q
Q
D
D
Q
GND
1
2
0
3
0
4
1
5
1
6
2
7
2
8
3
9
3
10
MR asynchronous master reset (active LOW)
7273
to Q
0
to D
0
CC
MNA380
7
7
V
20
CC
Q
19
7
D
18
7
D
17
6
Q
16
6
Q
15
5
D
14
5
D
13
4
Q
12
4
CP
11
flip-flop outputs
data inputs
DC supply voltage
handbook, halfpage
11
1
D0D1D2D3D4D5D6D
CP
MR
Q0Q1Q2Q3Q4Q5Q6Q
74HCT7273
181714138743
7
7
191615129652
MNA381
Fig.1 Pin configuration.
1999 Oct 01 4
Fig.2 Logic symbol.
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
handbook, halfpage
11
C1
1
R
3
1D
4
7
8
13
14
17
18
74HCT7273
2
5
6
9
12
15
16
19
MNA382
handbook, full pagewidth
D
0
CP
11
MR
1
D
CP
FF1
R
Fig.3 IEC logic symbol.
181714138743
D
1
Q
D
D
FF2
CP
R
D
Q
0
D
2
Q
D
FF3
CP
R
D
Q
1
D
3
Q
D
FF4
CP
R
D
Q
2
D
4
Q
D
FF5
CP
R
D
Q
3
D
5
Q
D
FF6
CP
R
D
Q
4
D
6
Q
D
FF7
CP
R
D
Q
5
D
7
Q
D
Q
FF8
CP
R
D
Q
6
Q
7
191615129652
MNA383
Fig.4 Functional diagram.
1999 Oct 01 5
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1999 Oct 01 6
handbook, full pagewidth
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
CP
MR
D
0
D
FF1
CP
R
D
1
Q
D
D
FF2
CP
R
V
CC
D
2
Q
D
Q
0
D
FF3
CP
R
V
CC
D
3
Q
D
Q
1
D
FF4
CP
R
V
CC
D
4
Q
D
Q
2
D
FF5
CP
R
V
CC
D
5
Q
D
Q
3
D
FF6
CP
R
V
CC
D
6
Q
D
Q
4
D
FF7
CP
R
V
CC
D
7
Q
D
Q
5
D
Q
FF8
CP
R
D
V
CC
Q
6
MNA384
V
CC
Q
7
74HCT7273
Fig.5 Logic diagram.
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