Philips 74HCT7046AU, 74HCT7046AN, 74HCT7046AD, 74HC7046AU, 74HC7046ANB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT7046A

Phase-locked-loop with lock detector

Product specification			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
Phase-locked-loop with lock detector	74HC/HCT7046A

FEATURES

·Low power consumption

·Centre frequency up to 17 MHz (typ.) at VCC = 4.5 V

·Choice of two phase comparators: EXCLUSIVE-OR;

edge-triggered JK flip-flop;

·Excellent VCO frequency linearity

·VCO-inhibit control for ON/OFF keying and for low standby power consumption

·Minimal frequency drift

·Operation power supply voltage range:

VCO section 3.0 to 6.0 V digital section 2.0 to 6.0 V

·Zero voltage offset due to op-amp buffering

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT7046 are high-speed Si-gate CMOS devices and are specified in compliance with JEDEC standard no. 7.

The 74HC/HCT7046 are phase-locked-loop circuits that comprise a linear voltage-controlled oscillator (VCO) and two different phase comparators (PC1 and PC2) with a common signal input amplifier and a common comparator input.

A lock detector is provided and this gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (GND). The value of the CLD capacitor can be determined, using information supplied in Fig.32. The input signal can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input

amplifiers. With a passive low-pass filter, the “7046” forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

VCO

The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1 and GND) or two external resistors R1 and R2 (between R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required.

The high input impedance of the VCO simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEMOUT). In contrast to conventional techniques where the DEMOUT voltage is one threshold voltage lower than the VCO input voltage, here the DEMOUT voltage equals that of the

VCO input. If DEMOUT is used, a load resistor (RS) should be connected

from DEMOUT to GND; if unused,

DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator

input (COMPIN), or connected via a frequency-divider. The VCO output signal has a duty factor of 50% (maximum expected deviation 1%), if the VCO input is held at a constant DC level. A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption.

The only difference between the HC and HCT versions is the input level specification of the INH input. This input disables the VCO section. The comparators’ sections are identical, so that there is no difference in the

SIGIN (pin 14) or COMPIN (pin 3) inputs between the HC and HCT versions.

Phase comparators

The signal input (SIGIN) can be directly coupled to the self-biasing amplifier at pin 14, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings.

Phase comparator 1 (PC1)

This is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must have a 50% duty factor to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed,

is:

V		VCC	(f		–f		)
	DEMOUT	= ----------		SIGIN		COMPIN
		p

where VDEMOUT is the demodulator output at pin 10;

VDEMOUT = VPC1OUT (via low-pass filter).

The phase comparator gain is:

K		VCC	(V ¤ r) .
	p	= ----------
		p

The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10

(VDEMOUT), is the resultant of the phase differences of signals (SIGIN)

and the comparator input (COMPIN) as shown in Fig.6. The average of

VDEMOUT is equal to 1/2 VCC when there is no signal or noise at SIGIN

and with this input the VCO oscillates at the centre frequency (fo). Typical

December 1990

2

Philips Semiconductors	Product specification
Phase-locked-loop with lock detector	74HC/HCT7046A

waveforms for the PC1 loop locked at fo are shown in Fig.7.

The frequency capture range (2fc) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration retains lock even with very noisy input signals.

Typical behaviour of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO centre frequency.

Phase comparator 2 (PC2)

This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 comprises two D-type flip-flops, control-gating and a 3-state output stage. The circuit functions as an up-down counter (Fig.5) where SIGIN causes an up-count and COMPIN a down-count. The transfer function of PC2, assuming ripple (fr = fi) is suppressed,

is:

V		VCC	(f		–f		)
	DEMOUT	= ----------		SIGIN		COMPIN
		4p

where VDEMOUT is the demodulator output at pin 10;

VDEMOUT = VPC2OUT (via low-pass filter).

The phase comparator gain is:

K VCC (V ¤ r) . = ----------

p 4p

VDEMOUT is the resultant of the initial phase differences of SIGIN and

COMPIN as shown in Fig.8. Typical waveforms for the PC2 loop locked at fo are shown in Fig.9.

When the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (fDEMOUT). When the phase of SIGIN lags that of COMPIN, the n-type driver is held “ON”.

When the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the input signal cycle time, and for the remainder of the cycle both n and p- type drivers are “OFF” (3-state). If the SIGIN frequency is lower than the COMPIN frequency, then it is the n-type driver that is held “ON” for most of the cycle. Subsequently, the voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable point the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at pin 9 is a high impedance.

Thus, for PC2, no phase difference exists between SIGIN and COMPIN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both p and n-type drivers are “OFF” for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of

the low-pass filter. With no signal present at SIGIN the VCO adjusts, via PC2, to its lowest frequency.

APPLICATIONS

·FM modulation and demodulation

·Frequency synthesis and multiplication

·Frequency discrimination

·Tone decoding

·Data synchronization and conditioning

·Voltage-to-frequency conversion

·Motor-speed control

December 1990

3

Philips Semiconductors				Product specification
Phase-locked-loop with lock detector			74HC/HCT7046A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C;
SYMBOL	PARAMETER		CONDITIONS	TYPICAL		UNIT
				HC	HCT
fo	VCO centre frequency		C1 = 40 pF; R1 = 3 kW; VCC = 5 V	19	19	MHz
CI	input capacitance (pin 5)			3.5	3.5	pF
CPD	power dissipation capacitance per package		notes 1 and 2	24	24	pF

Notes

1.Applies to the phase comparator section only (VCO disabled).

For power dissipation of VCO and demodulator sections see Figs 20, 21 and 22.

2.CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

4

Philips Semiconductors			Product specification
Phase-locked-loop with lock detector			74HC/HCT7046A
PIN DESCRIPTION
PIN NO.	SYMBOL	NAME AND FUNCTION
1	LD	lock detector output (active HIGH)
2	PC1OUT	phase comparator 1 output
3	COMPIN	comparator input
4	VCOOUT	VCO output
5	INH	inhibit input
6	C1A	capacitor C1 connection A
7	C1B	capacitor C1 connection B
8	GND	ground (0 V)
9	VCOIN	VCO input
10	DEMOUT	demodulator output
11	R1	resistor R1 connection
12	R2	resistor R2 connection
13	PC2OUT	phase comparator 2 output
14	SIGIN	signal input
15	CLD	lock detector capacitor input
16	VCC	positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

December 1990

5

1990December

C1

-lockedPhase-

SemiconductorsPhilips

6

7

4

3

14

loop

C1A

C1B VCO OUT COMP IN

SIG IN

4046A

identical to 4046A

with

12

R2

PHASE

PC1 OUT

7046A

2

lock

COMPARATOR

R2

1

PHASE

PC2 OUT

13

VCO

PC2 OUT

COMPARATOR

13

detector

11 R1

PHASE

R3

2

COMPARATOR

PCPOUT

1

R1

2

R4

LOCK

DETECTOR

6

PHASE

PC3 OUT

15

C2

COMPARATOR

LD

1

3

INH

DEMOUT

VCO IN

CLD

5

10

9

15

MGA847

R S

CCLD

(a)

(b)

Fig.4 Functional diagram.

74HC/HCT7046A

specification Product

Philips Semiconductors	Product specification
Phase-locked-loop with lock detector	74HC/HCT7046A

Fig.5 Logic diagram.

Fig.6		Phase comparator 1: average output
		voltage versus input phase difference:
V			= V		VCC		–φ		)
	DEMOUT			PC1OUT	= ---------- ( φ	SIGIN		COMPIN
					π

φDEMOUT = φSIGIN –φCOMPIN

Fig.7 Typical waveforms for PLL using phase comparator 1, loop locked at fo.

December 1990

7

Philips Semiconductors	Product specification
Phase-locked-loop with lock detector	74HC/HCT7046A

Fig.8		Phase comparator 2: average output
		voltage versus input phase difference:
V			= V			VCC	( φ		–φ		)
	DEMOUT				PC2OUT	= ----------		SIGIN		COMPIN
						4π
φDEMOUT =						˙
				( φSIGIN –φCOMPIN) .

Fig.9 Typical waveforms for PLL using phase comparator 2, loop locked at fo.

December 1990

8

Philips Semiconductors

Product specification

Phase-locked-loop with lock detector

74HC/HCT7046A

RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT

SYMBOL

PARAMETER

74HC

74HCT

UNIT

CONDITIONS

min.

typ.

max.

min.

typ.

max.

VCC

DC supply voltage

3.0

5.0

6.0

4.5

5.0

5.5

V

VCC

DC supply voltage if VCO section is

2.0

5.0

6.0

4.5

5.0

5.5

V

not used

VI

DC input voltage range

0

VCC

0

VCC

V

VO

DC output voltage range

0

VCC

0

VCC

V

Tamb

operating ambient temperature range

−40

+85

−40

+85

°C

see DC and AC

Tamb

operating ambient temperature range

−40

+125

−40

+125

°C

CHARACTER-

ISTICS

tr, tf

input rise and fall times (pin 5)

1000

VCC = 2.0 V

6.0

500

6.0

500

ns

VCC = 4.5 V

400

VCC = 6.0 V

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Voltages are referenced to GND (ground = 0 V)

SYMBOL	PARAMETER	MIN.	MAX.	UNIT	CONDITIONS
VCC	DC supply voltage	−0.5	+7	V
±IIK	DC input diode current		20	mA	for VI < −0.5 V or VI > VCC + 0.5 V
±IOK	DC output diode current		20	mA	for VO < −0.5 V or VO > VCC + 0.5 V
±IO	DC output source or sink current		25	mA	for − 0.5 V < VO < VCC + 0.5 V
±ICC;	DC VCC or GND current		50	mA
±IGND
Tstg	storage temperature range	−65	+150	°C
Ptot	power dissipation per package				for temperature range: −40 to +125 °C
					74HC/HCT
	plastic DIL		750	mW	above +70 °C: derate linearly with 12 mW/K
	plastic mini-pack (SO)		500	mW	above +70 °C: derate linearly with 8 mW/K

December 1990

9

Philips Semiconductors

Product specification

Phase-locked-loop with lock detector

74HC/HCT7046A

DC CHARACTERISTICS FOR 74HC

Quiescent supply current

Voltages are referenced to GND (ground = 0 V)

Tamb (°C)

TEST CONDITIONS

SYMBOL

PARAMETER

74HC

UNIT

VCC

+25

−40 to +85

−40 to +125

OTHER

(V)

min.

typ.

max.

min.

max.

min.

max.

ICC

quiescent supply

8.0

80.0

160.0

μA

6.0

pins 3, 5, and 14 at

current

VCC; pin 9 at GND;

(VCO disabled)

II at pins 3 and 14

to be excluded

December 1990

10

Philips Semiconductors												Product specification
Phase-locked-loop with lock detector											74HC/HCT7046A
Phase comparator section
Voltages are referenced to GND (ground = 0 V)
					Tamb (°C)							TEST CONDITIONS
SYMBOL	PARAMETER					74HC				UNIT
												VCC	VI
			+25			−40 to +85		−40 to +125						OTHER
												(V)
		min.	typ.	max.		min.	max.	min.	max.
	DC coupled HIGH	1.5	1.2			1.5		1.5				2.0
VIH	level input voltage	3.15	2.4			3.15		3.15		V		4.5
	SIGIN, COMPIN	4.2	3.2			4.2		4.2				6.0
	DC coupled LOW level		0.8	0.5			0.5		0.5			2.0
VIL	input voltage		2.1	1.35			1.35		1.35	V		4.5
	SIGIN, COMPIN		2.8	1.8			1.8		1.8			6.0
	HIGH level output	1.9	2.0			1.9		1.9				2.0	VIH	−IO = 20 μA
VOH	voltage	4.4	4.5			4.4		4.4		V		4.5	or	−IO = 20 μA
	LD, PCnOUT	5.9	6.0			5.9		5.9				6.0	VIL	−IO = 20 μA
	HIGH level output	3.98	4.32			3.84		3.7				4.5	VIH	−IO = 4.0 mA
VOH	voltage									V			or
		5.48	5.81			5.34		5.2				6.0		−IO = 5.2 mA
	LD, PCnOUT												VIL
	LOW level output		0	0.1			0.1		0.1			2.0	VIH	IO = 20 μA
VOL	voltage		0	0.1			0.1		0.1	V		4.5	or	IO = 20 μA
	LD, PCnOUT		0	0.1			0.1		0.1			6.0	VIL	IO = 20 μA
VOL	LOW level output		0.15	0.26			0.33		0.4			4.5	VIH	IO = 4.0 mA
	voltage									V			or
			0.16	0.26			0.33		0.4			6.0		IO = 5.2 mA
	LD, PCnOUT												VIL
±II	input leakage current			3.0			4.0		5.0	μA		2.0	VCC
	SIGIN, COMPIN			7.0			9.0		11.0			3.0	or
				18.0			23.0		27.0			4.5	GND
				30.0			38.0		45.0			6.0
±IOZ	3-state			0.5			5.0		10.0	μA		6.0	VIH	VO = VCC
	OFF-state current												or	or GND
	PC2OUT												VIL
RI	input resistance		800							kΩ		3.0	VI at self-bias
	SIGIN, COMPIN		250									4.5	operating point;
			150									6.0	VI = 0.5 V; see
													Figs 10, 11 and 12

December 1990

11

Philips Semiconductors												Product specification
Phase-locked-loop with lock detector											74HC/HCT7046A
VCO section
Voltages are referenced to GND (ground = 0 V)
					Tamb (°C)						TEST CONDITIONS
SYM-	PARAMETER					74HC				UNIT
											VCC	VI
BOL			+25			−40 to +85		−40 to +125					OTHER
											(V)
		min.	typ.	max.		min.	max.	min.	max.
	HIGH level	2.1	1.7			2.1		2.1			3.0
VIH	input voltage	3.15	2.4			3.15		3.15		V	4.5
	INH	4.2	3.2			4.2		4.2			6.0
	LOW level		1.3	0.9			0.9		0.9		3.0
VIL	input voltage		2.1	1.35			1.35		1.35	V	4.5
	INH		2.8	1.8			1.8		1.8		6.0
	HIGH level	2.9	3.0			2.9		2.9			3.0	VIH	−IO = 20 μA
VOH	output voltage	4.4	4.5			4.4		4.4		V	4.5	or	−IO = 20 μA
	VCOOUT	5.9	6.0			5.9		5.9			6.0	VIL	−IO = 20 μA
	HIGH level	3.98	4.32			3.84		3.7			4.5	VIH	−IO = 4.0 mA
VOH	output voltage									V		or
		5.48	5.81			5.34		5.2			6.0		−IO = 5.2 mA
	VCOOUT											VIL
	LOW level		0	0.1			0.1		0.1		3.0	VIH	IO = 20 μA
VOL	output voltage		0	0.1			0.1		0.1	V	4.5	or	IO = 20 μA
	VCOOUT		0	0.1			0.1		0.1		6.0	VIL	IO = 20 μA
VOL	LOW level		0.15	0.26			0.33		0.4		4.5	VIH	IO = 4.0 mA
	output voltage									V		or
			0.16	0.26			0.33		0.4		6.0		IO = 5.2 mA
	VCOOUT											VIL
	LOW level output			0.40			0.47		0.54		4.5	VIH	IO = 4.0 mA
VOL	voltage C1A, C1B									V		or
				0.40			0.47		0.54		6.0		IO = 5.2 mA
	(test purposes only)											VIL
±II	input leakage current									μA		VCC
				0.1			1.0		1.0		6.0	or
	INH, VCOIN
												GND
		3.0		300							3.0
R1	resistor range	3.0		300						kΩ	4.5		note 1
		3.0		300							6.0
		3.0		300							3.0
R2	resistor range	3.0		300						kΩ	4.5		note 1
		3.0		300							6.0
		40		no							3.0
C1	capacitor range	40								pF	4.5
				limit
		40									6.0
		1.1		1.9							3.0		over the range
	operating voltage												specified for R1;
VVCOIN		1.1		3.4						V	4.5
	range at VCOIN												for linearity see
		1.1		4.9							6.0
													Figs 18 and 19.

Note

1.The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2 are/is > 10 kΩ.

December 1990

12