Philips 74HCT7046AU, 74HCT7046AN, 74HCT7046AD, 74HC7046AU, 74HC7046ANB Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT7046A

Phase-locked-loop with lock
detector

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

FEATURES

• Low power consumption

• Centre frequency up to 17 MHz

(typ.) at VCC= 4.5 V

• Choice of two phase comparators:
EXCLUSIVE-OR;
edge-triggered JK flip-flop;

• Excellent VCO frequency linearity

• VCO-inhibit control for ON/OFF

keying and for low standby power
consumption

• Minimal frequency drift

• Operation power supply voltage

range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V

• Zero voltage offset due to op-amp
buffering

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT7046 are high-speed
Si-gate CMOS devices and are
specified in compliance with JEDEC
standard no. 7.

The 74HC/HCT7046 are
phase-locked-loop circuits that
comprise a linear voltage-controlled
oscillator (VCO) and two different
phase comparators (PC1 and PC2)
with a common signal input amplifier
and a common comparator input.

A lock detector is provided and this
gives a HIGH level at pin 1 (LD) when
the PLL is locked. The lock detector
capacitor must be connected
between pin 15 (C

LD

) and pin 8
(GND). The value of the CLD capacitor
can be determined, using information
supplied in Fig.32. The input signal
can be directly coupled to large
voltage signals, or indirectly coupled
(with a series capacitor) to small
voltage signals. A self-bias input
circuit keeps small voltage signals
within the linear region of the input

amplifiers. With a passive low-pass
filter, the “7046” forms a second-order
loop PLL. The excellent VCO linearity
is achieved by the use of linear
op-amp techniques.

VCO

The VCO requires one external
capacitor C1 (between C1

A

and C1B)
and one external resistor R1
(between R1 and GND) or two
external resistors R1 and R2
(between R1 and GND, and R2 and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required.

The high input impedance of the VCO
simplifies the design of low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEM

OUT

). In contrast to conventional

techniques where the DEM

OUT

voltage is one threshold voltage lower
than the VCO input voltage, here the
DEM

OUT

voltage equals that of the

VCO input. If DEM

OUT

is used, a load
resistor (RS) should be connected
from DEM

OUT

to GND; if unused,

DEM

OUT

should be left open. The

VCO output (VCO

OUT

) can be
connected directly to the comparator
input (COMPIN), or connected via a
frequency-divider. The VCO output
signal has a duty factor of 50%
(maximum expected deviation 1%), if
the VCO input is held at a constant
DC level. A LOW level at the inhibit
input (INH) enables the VCO and
demodulator, while a HIGH level turns
both off to minimize standby power
consumption.

The only difference between the HC
and HCT versions is the input level
specification of the INH input. This
input disables the VCO section. The
comparators’ sections are identical,
so that there is no difference in the

SIG

IN

(pin 14) or COMPIN (pin 3)
inputs between the HC and HCT
versions.

Phase comparators

The signal input (SIG

IN

) can be
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.

Phase comparator 1 (PC1)

This is an EXCLUSIVE-OR network.
The signal and comparator input
frequencies (fi) must have a 50% duty
factor to obtain the maximum locking
range. The transfer characteristic of
PC1, assuming ripple (f

r

=2fi) is
suppressed,
is:

where V

DEMOUT

is the demodulator

output at pin 10;
V

DEMOUT=VPC1OUT

(via low-pass

filter).
The phase comparator gain

is:

The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(V

DEMOUT

), is the resultant of the
phase differences of signals (SIGIN)
and the comparator input (COMPIN)
as shown in Fig.6. The average of
V

DEMOUT

is equal to 1/2 VCC when

there is no signal or noise at SIG

IN

and with this input the VCO oscillates
at the centre frequency (fo). Typical

V

DEMOUT

V

CC

π

---------- -

φ

SIGINφCOMPIN

–()=

K

p

V

CC

π

---------- -

Vr⁄().=

December 1990 3

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

waveforms for the PC1 loop locked at
fo are shown in Fig.7.

The frequency capture range (2fc) is
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2fL) is defined
as the frequency range of input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.

With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration retains lock
even with very noisy input signals.
Typical behaviour of this type of
phase comparator is that it can lock to
input frequencies close to the
harmonics of the VCO centre
frequency.

Phase comparator 2 (PC2)

This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIGIN and COMPIN are not important.
PC2 comprises two D-type flip-flops,
control-gating and a 3-state output
stage. The circuit functions as an
up-down counter (Fig.5) where SIG

IN

causes an up-count and COMPIN a
down-count. The transfer function of
PC2, assuming ripple (f

r=fi

) is
suppressed,
is:

where V

DEMOUT

is the demodulator
output at pin 10;
V

DEMOUT=VPC2OUT

(via low-pass

filter).

V

DEMOUT

V

CC

4π

---------- -

φ

SIGINφCOMPIN

–()=

The phase comparator gain is:

V

DEMOUT

is the resultant of the initial

phase differences of SIG

IN

and

COMP

IN

as shown in Fig.8. Typical
waveforms for the PC2 loop locked at
f

o

are shown in Fig.9.

When the frequencies of SIG

IN

and

COMP

IN

are equal but the phase of
SIG

IN

leads that of COMPIN, the

p-type output driver at PC2

OUT

is held
“ON” for a time corresponding to the
phase difference (φ

DEMOUT

). When

the phase of SIG

IN

lags that of

COMP

IN

, the n-type driver is held

“ON”.
When the frequency of SIG

IN

is higher
than that of COMPIN, the p-type
output driver is held “ON” for most of
the input signal cycle time, and for
the remainder of the cycle both n and
p- type drivers are “OFF” (3-state). If
the SIGINfrequency is lower than the
COMPIN frequency, then it is the
n-type driver that is held “ON” for
most of the cycle. Subsequently, the
voltage at the capacitor (C2) of the
low-pass filter connected to PC2

OUT

varies until the signal and comparator
inputs are equal in both phase and
frequency. At this stable point the
voltage on C2 remains constant as
the PC2 output is in 3-state and the
VCO input at pin 9 is a high
impedance.

Thus, for PC2, no phase difference
exists between SIGIN and COMP

IN

over the full frequency range of the
VCO. Moreover, the power
dissipation due to the low-pass filter is
reduced because both p and n-type
drivers are “OFF” for most of the
signal input cycle. It should be noted
that the PLL lock range for this type of
phase comparator is equal to the
capture range and is independent of

K

p

V

CC

4π

---------- -

Vr⁄().=

the low-pass filter. With no signal
present at SIG

IN

the VCO adjusts, via

PC2, to its lowest frequency.

APPLICATIONS

• FM modulation and demodulation

• Frequency synthesis and

multiplication

• Frequency discrimination

• Tone decoding

• Data synchronization and

conditioning

• Voltage-to-frequency conversion

• Motor-speed control

December 1990 4

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C;

Notes

1. Applies to the phase comparator section only (VCO disabled).
For power dissipation of VCO and demodulator sections see Figs 20, 21 and 22.

2. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+∑(CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

f

o

VCO centre frequency C1 = 40 pF; R1 = 3 kΩ; VCC= 5 V 19 19 MHz

C

I

input capacitance (pin 5) 3.5 3.5 pF

C

PD

power dissipation capacitance per package notes 1 and 2 24 24 pF

December 1990 5

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 LD lock detector output (active HIGH)
2 PC1

OUT

phase comparator 1 output

3 COMP

IN

comparator input

4 VCO

OUT

VCO output
5 INH inhibit input
6C1

A

capacitor C1 connection A
7C1

B

capacitor C1 connection B
8 GND ground (0 V)
9 VCO

IN

VCO input
10 DEM

OUT

demodulator output
11 R

1

resistor R1 connection
12 R

2

resistor R2 connection
13 PC2

OUT

phase comparator 2 output
14 SIG

IN

signal input
15 C

LD

lock detector capacitor input
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 6

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

Fig.4 Functional diagram.

MGA847

PHASE

COMPARATOR

2

LOCK

DETECTOR

PC2

OUT

LD

13

1

identical to 4046A

C

LD

C

CLD

15

7046A

PHASE

COMPARATOR

2

PC2

OUT 13

PHASE

COMPARATOR

3

PC3

OUT 15

PHASE

COMPARATOR

1

PC1

OUT

2

PCP

OUT

1

SIG

IN

COMP

IN

V

CO OUT

C1

A

C1

B

DEM

OUTINH

VCO

IN

R

2

R

1

R2

12

11

314476

5109

(a)

(b)

C1

4046A

VCO

R

S

R1

R4

R3

C2

December 1990 7

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

Fig.5 Logic diagram.

Fig.6 Phase comparator 1: average output

voltage versus input phase difference:

V

DEMOUT

V

PC1OUT

V

CC

π

---------- -

φ

SIGINφCOMPIN

–()==

φ

DEMOUTφSIGINφCOMPIN

–=

Fig.7 Typical waveforms for PLL using phase

comparator 1, loop locked at fo.

December 1990 8

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

Fig.8 Phase comparator 2: average output

voltage versus input phase difference:

V

DEMOUT

V

PC2OUT

=

V

CC

4π

---------- -

φ

SIGINφCOMPIN

–()=

φ

DEMOUT

φ

SIGINφCOMPIN

–()

˙

.=

Fig.9 Typical waveforms for PLL using phase

comparator 2, loop locked at f

o.

December 1990 9

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

74HC 74HCT

UNIT CONDITIONS

min. typ. max. min. typ. max.

V

CC

DC supply voltage 3.0 5.0 6.0 4.5 5.0 5.5 V

V

CC

DC supply voltage if VCO section is
not used

2.0 5.0 6.0 4.5 5.0 5.5 V

V

I

DC input voltage range 0 V

CC

0V

CC

V

V

O

DC output voltage range 0 V

CC

0V

CC

V

T

amb

operating ambient temperature range −40 +85 −40 +85 °C see DC and AC

CHARACTER­ISTICS

T

amb

operating ambient temperature range −40 +125 −40 +125 °C

tr, t

f

input rise and fall times (pin 5)

6.0

1000
500
400

6.0 500 ns

VCC= 2.0 V
VCC= 4.5 V
VCC= 6.0 V

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

V

CC

DC supply voltage −0.5 +7V

±I

IK

DC input diode current 20 mA for VI<−0.5 V or VI> VCC+ 0.5 V

±I

OK

DC output diode current 20 mA for VO<−0.5 V or VO> VCC+ 0.5 V

±I

O

DC output source or sink current 25 mA for − 0.5 V < VO< VCC+ 0.5 V

±I

CC

;

±I

GND

DC VCC or GND current

50 mA

T

stg

storage temperature range −65 +150 °C

P

tot

power dissipation per package

plastic DIL 750 mW

for temperature range: −40 to +125 °C
74HC/HCT
above +70 °C: derate linearly with 12 mW/K

plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K

December 1990 10

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

DC CHARACTERISTICS FOR 74HC
Quiescent supply current

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

T

amb

(°C)

UNIT

TEST CONDITIONS

74HC

V

CC

(V)

OTHER+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

I

CC

quiescent supply
current

(VCO disabled)

8.0 80.0 160.0 µA 6.0 pins 3, 5, and 14 at
VCC; pin 9 at GND;
II at pins 3 and 14
to be excluded

December 1990 11

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

Phase comparator section

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

T

amb

(°C)

UNIT

TEST CONDITIONS

74HC

V

CC

(V)

V

I

OTHER+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

V

IH

DC coupled HIGH
level input voltage

SIGIN, COMP

IN

1.5

3.15

4.2

1.2

2.4

3.2

1.5

3.15

4.2

1.5

3.15

4.2

V

2.0

4.5

6.0

V

IL

DC coupled LOW level
input voltage

SIGIN, COMP

IN

0.8

2.1

2.8

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

V

2.0

4.5

6.0

V

OH

HIGH level output

voltage

LD, PC

nOUT

1.9

4.4

5.9

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

V

2.0

4.5

6.0

V

IH

or
V

IL

−IO=20µA

−IO=20µA

−IO=20µA

V

OH

HIGH level output

voltage

LD, PC

nOUT

3.98

5.48

4.32

5.81

3.84

5.34

3.7

5.2

V

4.5

6.0

V

IH

or
V

IL

−IO= 4.0 mA

−I

O

= 5.2 mA

V

OL

LOW level output
voltage

LD, PC

nOUT

0
0
0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

2.0

4.5

6.0

V

IH

or
V

IL

IO=20µA
IO=20µA
IO=20µA

V

OL

LOW level output
voltage

LD, PC

nOUT

0.15

0.16

0.26

0.26

0.33

0.33

0.4

0.4

V

4.5

6.0

V

IH

or
V

IL

IO= 4.0 mA
I

O

= 5.2 mA

±I

I

input leakage current

SIGIN, COMP

IN

3.0

7.0

18.0

30.0

4.0

9.0

23.0

38.0

5.0

11.0

27.0

45.0

µA 2.0

3.0

4.5

6.0

V

CC

or

GND

±I

OZ

3-state

OFF-state current
PC2

OUT

0.5 5.0 10.0 µA 6.0 V

IH

or
V

IL

VO=V

CC

or GND

R

I

input resistance

SIGIN, COMP

IN

800
250
150

kΩ 3.0

4.5

6.0

VI at self-bias
operating point;
∆V

I

= 0.5 V; see

Figs 10, 11 and 12

December 1990 12

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

VCO section

Voltages are referenced to GND (ground = 0 V)

Note

1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2
are/is > 10 kΩ.

SYM-

BOL

PARAMETER

T

amb

(°C)

UNIT

TEST CONDITIONS

74HC

V

CC

(V)

V

I

OTHER+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

V

IH

HIGH level

input voltage
INH

2.1

3.15

4.2

1.7

2.4

3.2

2.1

3.15

4.2

2.1

3.15

4.2

V

3.0

4.5

6.0

V

IL

LOW level

input voltage
INH

1.3

2.1

2.8

0.9

1.35

1.8

0.9

1.35

1.8

0.9

1.35

1.8

V

3.0

4.5

6.0

V

OH

HIGH level

output voltage
VCO

OUT

2.9

4.4

5.9

3.0

4.5

6.0

2.9

4.4

5.9

2.9

4.4

5.9

V

3.0

4.5

6.0

V

IH

or
V

IL

−IO=20µA

−IO=20µA

−IO=20µA

V

OH

HIGH level

output voltage
VCO

OUT

3.98

5.48

4.32

5.81

3.84

5.34

3.7

5.2

V

4.5

6.0

V

IH

or
V

IL

−IO= 4.0 mA

−IO= 5.2 mA

V

OL

LOW level

output voltage
VCO

OUT

0
0
0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

3.0

4.5

6.0

V

IH

or
V

IL

IO=20µA
IO=20µA
IO=20µA

V

OL

LOW level

output voltage
VCO

OUT

0.15

0.16

0.26

0.26

0.33

0.33

0.4

0.4

V

4.5

6.0

V

IH

or
V

IL

IO= 4.0 mA
IO= 5.2 mA

V

OL

LOW level output

voltage C1A,C1

B

(test purposes only)

0.40

0.40

0.47

0.47

0.54

0.54

V

4.5

6.0

V

IH

or
V

IL

IO= 4.0 mA
IO= 5.2 mA

±I

I

input leakage current

INH, VCO

IN

0.1 1.0 1.0 µA 6.0

V

CC

or

GND

R1 resistor range

3.0

3.0

3.0

300
300
300

kΩ

3.0

4.5

6.0

note 1

R2 resistor range

3.0

3.0

3.0

300
300
300

kΩ

3.0

4.5

6.0

note 1

C1 capacitor range

40
40
40

no
limit

pF

3.0

4.5

6.0

V

VCOIN

operating voltage

range at VCO

IN

1.1

1.1

1.1

1.9

3.4

4.9

V

3.0

4.5

6.0

over the range
specified for R1;
for linearity see
Figs 18 and 19.