Philips 74hct373 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT373
Octal D-type transparent latch;
3-state
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT373
FEATURES
• 3-state non-inverting outputs for bus oriented
applications
• Common 3-state output enable input
• Functionally identical to the “563”, “573” and “533”
• Output capability: bus driver
• ICC category: MSI
input and an output enable (
latches.
The “373” consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the D
inputs enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
GENERAL DESCRIPTION
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
The 74HC/HCT373 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
standard no. 7A.
The “373” is functionally identical to the “533”, “563” and
The 74HC/HCT373 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
“573”, but the “563” and “533” have inverted outputs and
the “563” and “573” have a different pin arrangement.
outputs for bus oriented applications. A latch enable (LE)
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
C
C
I
PD
/ t
PLH
propagation delay CL= 15 pF; VCC=5V
D
to Q
n
n
LE to Q
n
input capacitance 3.5 3.5 pF
power dissipation capacitance per latch notes 1 and 2 45 41 pF
OE) input are common to all
n
TYPICAL
UNIT
HC HCT
12 14 ns
15 13 ns
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to VCC. For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
September 1993 2
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT373
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2, 5, 6, 9, 12, 15, 16, 19 Q
3, 4, 7, 8, 13, 14, 17, 18 D
10 GND ground (0 V)
11 LE latch enable input (active HIGH)
20 V
OE 3-state output enable input (active LOW)
to Q
0
to D
0
CC
7
7
3-state latch outputs
data inputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
September 1993 3
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