Philips 74HCT173U, 74HCT173NB, 74HCT173N, 74HCT173DB, 74HCT173D Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT173

Quad D-type flip-flop; positive-edge
trigger; 3-state

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

FEATURES

• Gated input enable for hold (do nothing) mode

• Gated output enable control

• Edge-triggered D-type register

• Asynchronous master reset

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q

0

to Q3)

and master reset (MR).
When the two data enable inputs (E1 andE2) are LOW, the

data on the Dn inputs is loaded into the register

synchronously with the LOW-to-HIGH clock (CP)
transition. When one or both En inputs are HIGH one
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.

The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.

The 3-state output buffers are controlled by a 2-input NOR
gate. When both output enable inputs (OE1 and OE2) are
LOW, the data in the register is presented to the Q

n

outputs. When one or both OEn inputs are HIGH, the
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OEn transition does not affect the
clock and reset operations.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf=6ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC−1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay

CP to Q

n

MR to Q

n

CL= 15 pF; VCC=5V

17
13

17
17

ns
ns

f

max

maximum clock frequency 88 88 MHz

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation
capacitance per flip-flop

notes 1 and 2 20 20 pF

December 1990 3

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 2

OE1, OE

2

output enable input (active LOW)

3, 4, 5, 6 Q

0

to Q

3

3-state flip-flop outputs
7 CP clock input (LOW-to-HIGH, edge-triggered)
8 GND ground (0 V)
9, 10

E1, E

2

data enable inputs (active LOW)
14, 13, 12, 11 D

0

to D

3

data inputs
15 MR asynchronous master reset (active HIGH)
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.