Philips 74HCT164PW, 74HCT164N, 74HCT164DB, 74HCT164D, 74HC164U Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT164

8-bit serial-in/parallel-out shift register

Product specification			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
8-bit serial-in/parallel-out shift register	74HC/HCT164

FEATURES

·Gated serial data inputs

·Asynchronous master reset

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT164 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT164 are 8-bit edge-triggered shift registers with serial data entry and an output from each of the eight stages.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

Data is entered serially through one of two inputs (Dsa or Dsb); either input can be used as an active HIGH enable for data entry through the other input.

Both inputs must be connected together or an unused input must be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND of the two data inputs (Dsa,Dsb) that existed one set-up time prior to the rising clock edge.

A LOW level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.

SYMBOL			PARAMETER	CONDITIONS		TYPICAL		UNIT
					HC		HCT
tPHL/ tPLH	propagation delay			CL = 15 pF; VCC = 5 V
		CP to Qn			12		14	ns
		MR	to Qn		11		16	ns
fmax	maximum clock frequency				78		61	MHz
CI	input capacitance				3.5		3.5	pF
CPD	power dissipation capacitance per			notes 1 and 2	40		40	pF
	package

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

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Philips Semiconductors					Product specification
8-bit serial-in/parallel-out shift register					74HC/HCT164
PIN DESCRIPTION
PIN NO.		SYMBOL		NAME AND FUNCTION
1, 2		Dsa, Dsb		data inputs
3, 4, 5, 6, 10, 11, 12, 13		Q0 to Q7		outputs
7		GND		ground (0 V)
8		CP		clock input (LOW-to-HIGH, edge-triggered)
9				master reset input (active LOW)
		MR
14		VCC		positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

December 1990

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