Philips 74HCT9114U, 74HCT9114N, 74HCT9114D, 74HC9114U, 74HC9114N Datasheet
...
DATA SH EET
Product specification
Supersedes data of March 1988
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT9114
Nine wide Schmitt trigger buffer;
open drain outputs; inverting
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Nine wide Schmitt trigger buffer;
open drain outputs; inverting
74HC/HCT9114
FEATURES
• Schmitt trigger action on all data inputs
• Output capability: standard (open drain)
• ICCcategory: MSI
GENERAL DESCRIPTION
The 74HC/HCT9114 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT9114 are nine wide Schmitt trigger
inverting buffer with open drain outputs and Schmitt trigger
inputs.
The Schmitt trigger action in the data inputs transform
slowly changing input signals into sharply defined
jitter-free output signals.
The 74HC/HCT9114 have open-drain N-transistor
outputs, which are not clamped by a diode connected to
V
CC
. In the OFF-state, i.e. when one input is LOW, the
output may be pulled to any voltage between GND and
V
Omax
. This allows the device to be used as a
LOW-to-HIGH or HIGH-to-LOW level shifter. For digital
operation and OR-tied output applications, these devices
must have a pull-up resistor to establish a logic HIGH level.
The “9114” is identical to the “9115” but has inverting
outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD=CPD× V
CC
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLZ
propagation delay Anto Y
n
CL= 15 pF; VCC= 5 V 12 13 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per buffer notes 1 and 2 5 5 pF
December 1990 3
Philips Semiconductors Product specification
Nine wide Schmitt trigger buffer;
open drain outputs; inverting
74HC/HCT9114
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3, 4, 5, 6, 7, 8, 9 A
0
to A
8
data inputs
10 GND ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12, 11
Y0to Y
8
data outputs
20 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic diagram.
fpage
MBA015
1
2
3
4
5
6
7
8
9
A
8
A
0
A
3
A
1
A
5
A
4
A
2
A
6
A
7
Y
8
Y
0
Y
3
Y
1
Y
5
Y
4
Y
2
Y
6
Y
7
19
18
12
14
15
11
13
16
17
Fig.3 IEC logic diagram.
lfpage
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
MBA014
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