Philips 74HCT9015U, 74HCT9015N, 74HCT9015D, 74HC9015U, 74HC9015PW Datasheet
...
DATA SH EET
Product specification
Supersedes data of March 1988
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT9015
Nine wide Schmitt trigger buffer/line
driver
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Nine wide Schmitt trigger buffer/line driver 74HC/HCT9015
FEATURES
• Schmitt trigger action on all data inputs
• Output capability: standard
• ICCcategory: MSI
GENERAL DESCRIPTION
The 74HC/HCT9015 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT9015 are nine wide Schmitt trigger
buffer/line drivers with Schmitt trigger inputs. These inputs
transform slowly changing input signals into sharply
defined jitter-free output signals.
The “9015” is identical to the “9014” but has non-inverting
inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD=CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay Anto Y
n
CL= 15 pF; VCC= 5 V 12 13 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per buffer notes 1 and 2 30 32 pF
December 1990 3
Philips Semiconductors Product specification
Nine wide Schmitt trigger buffer/line driver 74HC/HCT9015
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3, 4, 5, 6, 7, 8, 9 A
0
to A
8
data inputs
10 GND ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12, 11 Y
0
to Y
8
data outputs
20 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol.
page
MBA016
1
2
3
4
5
6
7
8
9
A
8
A
0
A
3
A
1
A
5
A
4
A
2
A
6
A
7
Y
8
Y
0
Y
3
Y
1
Y
5
Y
4
Y
2
Y
6
Y
7
19
18
12
14
15
11
13
16
17
Fig.3 IEC logic symbol.
age
3
4
5
6
7
8
9
11
12
13
14
15
16
17
1
218
19
MBA013
Loading...