Philips 74ABT374APW, 74ABT374AN, 74ABT374ADB, 74ABT374AD Datasheet

Philips Semiconductors	Product specification

Octal D-type flip-flop; positive-edge trigger

74ABT374A

(3-State)

FEATURES

•8-bit positive edge triggered register

•3-State output buffers

•Output capability: +64mA/±32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

•Power-up 3-State

•Power-up reset

•Live insertion/extraction permitted

QUICK REFERENCE DATA

DESCRIPTION

The 74ABT374A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT374A is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates.

The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the clock operation.

When OE is Low, the stored data appears at the outputs. When OE is High, the outputs are in the High-impedance ªOFFº state, which means they will neither drive nor load the bus.

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	3.4	ns
	tPHL	CP to Qn		3.8
	CIN	Input capacitance	VI = 0V or VCC	4	pF
	COUT	Output capacitance	Outputs disabled; VO = 0V or VCC	7	pF
	ICCZ	Total supply current	Outputs disabled; VCC =5.5V	110	μA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
20-Pin Plastic DIP	±40°C to +85°C	74ABT374A N	74ABT374A N	SOT146-1
20-Pin plastic SO	±40°C to +85°C	74ABT374A D	74ABT374A D	SOT163-1
20-Pin Plastic SSOP Type II	±40°C to +85°C	74ABT374A DB	74ABT374A DB	SOT339-1
20-Pin Plastic TSSOP Type I	±40°C to +85°C	74ABT374A PW	74ABT374APW DH	SOT360-1

PIN CONFIGURATION											PIN DESCRIPTION
											PIN	SYMBOL			FUNCTION
											NUMBER
											1				Output enable input (active-Low)
	OE		1				20	VCC					OE
Q0								Q7			3, 4, 7, 8,
			2				19
								D7			13, 14, 17,	D0-D7			Data inputs
	D0		3				18				18
	D1							D6
			4				17				2, 5, 6, 9,
Q1								Q6
			5				16				12, 15, 16,	Q0-Q7			Data outputs
	Q2							Q5			19
			6				15
	D2							D5			11		CP		Clock pulse input (active rising edge)
			7				14
	D3							D4
			8				13				10	GND			Ground (0V)
	Q3							Q4
			9				12				20	VCC			Positive supply voltage
GND
			10				11	CP	SA00110

1995 Sep 06

1

853-1448 15704

Philips Semiconductors	Product specification

Octal D-type flip-flop; positive-edge trigger

74ABT374A

(3-State)

LOGIC SYMBOL

LOGIC SYMBOL (IEEE/IEC)

3

4

7

8

13

14

17

18

1

EN

11

C1

D0

D1

D2

D3

D4

D5

D6

D7

11

CP

3

2

1

OE

1D

4

5

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

7

6

8

9

13

12

2

5

6

9

12

15

16

19

14

15

17

16

SA00111

18

19

SA00112

FUNCTION TABLE

INPUTS

INTERNAL

OUTPUTS

OPERATING MODE

CP

Dn

REGISTER

Q0 ± Q7

OE

L

↑

l

L

L

Latch and read register

L

↑

h

H

H

L

↑

X

NC

NC

Hold

H

↑

X

NC

Z

Disable outputs

H

↑

Dn

Dn

Z

H

=

High voltage level

h

=

High voltage level one set-up time prior to the Low-to-High clock transition

L

=

Low voltage level

l

=

Low voltage level one set-up time prior to the Low-to-High clock transition

NC=

No change

X

=

Don't care

Z

=

High impedance ªoffº state

↑= Low-to-High clock transition

↑= not a Low-to-High clock transition

LOGIC DIAGRAM

D0

D1

D2

D3

D4

D5

D6

D7

3

4

7

8

13

14

17

18

D

D

D

D

D

D

D

D

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

11

CP

1

OE

2

5

6

9

12

15

16

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

SA00113

1995 Sep 06

2