Philips 74ABT373APW, 74ABT373AN, 74ABT373ADB, 74ABT373AD Datasheet

INTEGRATED CIRCUITS

74ABT373A

Octal transparent latch (3-State)

Product specification 1995 Feb 17
IC23 Data Handbook

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Philips Semiconductors Product specification

74ABT373AOctal transparent latch (3-State)

FEA TURES

•8-bit transparent latch

•3-State output buffers

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power-up 3-State

•Power-up reset

•Live insertion/extraction permitted

QUICK REFERENCE DATA

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

IN

Propagation delay
Dn to Qn

Input capacitance VI = 0V or V
Output capacitance Outputs disabled; VO = 0V or V
Total supply current Outputs disabled; VCC =5.5V 100 µA

DESCRIPTION

The 74ABT373A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.

The 74ABT373A device is an octal transparent latch coupled to
eight 3-State output buffers. The two sections of the device are
controlled independently by Enable (E) and Output Enable (OE
control gates.

The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.

The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE
independent of the latch operation.

When OE
outputs. When OE
“OFF” state, which means they will neither drive nor load the bus.

CONDITIONS
= 25°C; GND = 0V

T

amb

CL = 50pF; VCC = 5V

CC

) controls all eight 3-State buffers

is Low, the latched or transparent data appears at the

is High, the outputs are in the High-impedance

TYPICAL UNIT

3.2

3.6

ns

4 pF

CC

7 pF

)

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

20-Pin Plastic DIP –40°C to +85°C 74ABT373A N 74ABT373A N SOT146-1
20-Pin plastic SO –40°C to +85°C 74ABT373A D 74ABT373A D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74ABT373A DB 74ABTD373A B SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT373A PW 7ABT373APW DH SOT360-1

PIN CONFIGURATION

1

OE

2

Q0

3

D0

4

D1

5

Q1

6

Q2

7

D2

8

D3

9

Q3 Q4

10 11

GND

20

V

CC

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13
12

E

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE Output enable input (active-Low)

3, 4, 7, 8, 13,

14, 17, 18

2, 5, 6, 9, 12,

15, 16, 19

11 E Enable input (active-High)
10 GND Ground (0V)
20 V

D0-D7 Data inputs

Q0-Q7 Data outputs

Positive supply voltage

CC

SA00059

1995 Feb 17 853-1454 14852

2

Philips Semiconductors Product specification

OPERATING

74ABT373AOctal transparent latch (3-State)

LOGIC SYMBOL

3 4 7 8 13 14 1817

D0 D1 D2 D3 D4 D5 D6 D7

11

E

1

OE

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

SA00060

FUNCTION TABLE

INPUTS

OE E Dn

LLHHL

LL↓↓l

H

h

INTERNAL
REGISTER

L

H

L

H

L L X NC NC Hold

HHLHX

Dn

NC

Dn

H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E

transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E

transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low E transition

OUTPUTS

Q0 – Q7

L

H

L

H

Z
Z

OPERATING

MODE

Enable and read
register

Latch and read
register

Disable outputs

LOGIC SYMBOL (IEEE/IEC)

1

11

32
45
76

89

13 12
14 15
17 16
18 19

EN
C1

1D

SA00061

LOGIC DIAGRAM

1995 Feb 17

OE

D0

3 4 7 8 13 14 17 18

D

E Q

11

E

1

D1

D

EQ

2 5 6 9 12 15 16 19

Q0

D2

D

EQ

Q1 Q2 Q3 Q4 Q5 Q6 Q7

D3

D

EQ

D4

D

EQ

D5

D

EQ

D6

D

EQ

D7

D

EQ

SA00062

3

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

74ABT373AOctal transparent latch (3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

CC

I

IK

V

I

I

OK

V

OUT

I

OUT

T

stg

DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
DC output current output in Low state 128 mA
Storage temperature range –65 to 150 °C

PARAMETER CONDITIONS RATING UNIT

3

3

1, 2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

LIMITS

Min Max

V

CC

V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 5 ns/V

T

amb

DC supply voltage 4.5 5.5 V
Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

High-level output current –32 mA
Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

CC

V

1995 Feb 17

4