Orban 9200 User Manual
OPTIMOD-AM Digital TECHNICAL DATA
Section 6
Technical Data
page contents
6-2 Specifications
6-5 Circuit Description
6-5 Overview
6-5 16.384MHz Oscillator and System Clocking
6-7 Control Circuits
6-9 User Control Interface and LED Display Circuits
6-10 Input Circuits
6-13 Output Circuits
6-15 DSP Circuits
6-17 Power Supply
6-1
6-19 Parts List
6-20 Obtaining Spare Parts
6-27 Vendor Codes
6-28 Schematics, Assembly Drawings
6-47 Abbreviations
6-2
TECHNICAL DATA Orban 9200
page
Specifications
It is impossible to characterize the listening quality of even the simplest limiter or compressor on the basis of the us ual sp ecific ations, b ecause su ch spec ificatio ns canno t adequate ly
describe the crucial dynamic processes that occur under program conditions. Therefore, the
only way to meaningfully evaluate the sound of an audio processor is by subjective listening
tests.
Certain spec ific atio ns are presented here to a ss ur e the eng ine er th at the y ar e re as on able, to
help plan the installation, and to help make certain comparisons with other processing
equipment. Some specifications are for features that are only available on the 9200.
Installation
Analog Audio Input
Configuration: One monophonic input.
Impedance: E lectronically balanced 600Ω or >3.6kΩ load impedance, jumper-selectable.
Dynamic Range: >90dB.
Common Mode Rejection: ≥ 70dB at 50-60Hz. ≥ 45dB at 60Hz-9.5kHz.
Sensitivity: −20dBu to +20dBu to p roduce 10d B gain redu ction at 1kHz, software- a nd jumper-
adjustable.
Maximum Input Level: +27dBu.
Connector: XLR-type, female, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 (+) and 3
electro ni cally bala nc ed, floati ng and symmet rical.
A/D Conversion: 18-bit.
Filtering: RFI-filtered.
Analog Audio Output
Configuration: Two mon aural outp uts fo r use with two tra nsmitt ers, with se parate le vel co ntrol
and output amp li fiers.
Source Impedance: 365Ω, ± 5%, electronically balanced to groun d.
Load Impe dance: 600Ω or greater, balanced or unb al an ce d. Termination not req ui red.
Output Level (100% peak mo du la tio n): Adjustable from 0dBu to +20dBu into 600Ω or
greater load, wit h fro nt -panel independen t mu lt i-turn potentiomet ers.
Output Noise Level: <−75dB (Bypass mode, refe renced to 100% mo du lation).
Distortion: ≤0.05% THD (Bypass mode).
Connector: XLR-type, male, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 and 3 electroni-
cally balanced. Positive vo lt age on Pin 2 correlat es to positive modul at io n.
D/A Conversi on : 18-bit.
Filtering: RFI-filtered.
OPTIMOD-AM Digital TECHNICAL DATA
Digital Audio Input (Digital I/O option inst alled)
Configuration: Two-channel per AES/EBU-standard. 20-bit resolution. Software selection of
left, right, or sum as input source.
Sample rate: 32, 44.1 or 48kH, automatic al ly-selected.
Connector: XLR-type, female, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 and 3 trans-
former balanced and floating.
Input Reference Level: Software-adjusta bl e from −30dBFS to −20dBFS.
J.17 De-emphasis: Software-selectable.
Digital Audio Output (Digital I/O option installed)
Configuration: Two-channel AES/EBU-standard. 20-bit resolution. Both channels carry the
same audio data . St at us bi ts pe r AES3-1992 standard “single-channe l mod e. ”
Sample rate: 32kHz, 44.1kHz, or 48kHz, software-selectable.
Sync: Software-selectabl e for internal or external. I n external, d igital out put is syn chronous with
digital in put.
Connector: XLR-type, male, EMI-su ppressed. Pin 1 Cha ssis Ground, Pins 2 an d 3 transfor mer
balanced and floa ting.
6-3
Output Level (100% pea k modu la tion) 0dBFS to −20dBFS, software-adjustable.
Remote Control Interf ace
Configuration: Eight opto-isolated inputs.
Voltage: 6-24V AC or DC, momentary or continuous, optically-isolated. 9VDC provided to
facilitate use wit h contact cl osure.
Connector: DB-25 male. EMI-suppresse d.
Control: User-programmable, for any eight of User Presets, Factory Presets, Day, Night,
Bypass, Sine, Wave Test, Analog Input, Digital Input (if Digital I/O Option installed).
Power
Voltage: 90-120VAC, 100-132VAC or 200-264VAC, 50-60Hz; 40VA.
Connector: IEC; detachable 3-wire po wer cord supplied. AC is E MI-su pp ressed.
Ground: Circuit ground is independent of chassis ground; can be isolated or connected with a
rear panel switch.
Safety Standards: UL, CE, CSA.
6-4
TECHNICAL DATA Orban 9200
Environmental
Operating Temperature Range: 32° to 122°F/0° to 50°C at nominal operating voltages.
Humidity: 0-95% RH, non-condensing.
Dimensions (W x H x D): 19“ x 3.5” x 14.25“/48.3cm x 8.9cm x 36.2cm. Two rack units high.
Weight: 14 lbs/6. 4k g.
Shipping Weight: 18.5 lbs/8.4kg.
Warranty
One Yea r, Parts an d L ab or: Subject to the limitations set forth in Orban’s Standard Warranty
Agreement.
Specifications are subject to change without notice.
6-6
TECHNICAL DATA Orban 9200
Component-Level Description:
The 16.384MHz digital output from crystal oscillator Y602 is buffered by
IC606-D, which feeds the master cloc k (MCLK) inpu ts of both the input a nd the
output SRC chips IC603 and IC615 (on digital I/O option board). The
16.384MHz clock a lso feed s flip-flop I C604, which divides b y two to pr oduce an
8.192MHz clock. The 8.192MHz clock is buffered by IC606-C, which feeds
digital multiplexer ch ip IC610, which in turn routes the 8. 19 2MHz to AES/EBU
digital audio transmitter chip IC616 when an internally generated 32kHz output
sample rate is selected. The 8.192 MHz cloc k is also sent to an 8-bit syn chro nous
counter impleme nted in programmable logic array (PL A) IC613.
This counter divides down to obtain the lower frequency system clocks. All
outputs of the PLA h ave their transitions coincident with the rising edge of the
8.192MHz clock. The 8.192MHz clock is inverted by buffers IC605-A, -B to
provide clock s
with the transitions of the lower frequency clocks.
clock of the inter-DSP communication links following buffers IC710-B, -D.
8.192MHZB feeds the A/D input clock (256 x sample rate), and the output D/A
master clock .
8.192MHZA and 8 .1 92MHZB that have falling ed ge s c oincident
8.192MHZA feeds the bit
The 2.048MHz clock output from IC613 feeds the PLL circuit made up of PLA
IC618, 74HC4046 phase detector/VCO IC619 and associated components. The
PLA f irst buffers the 2.048MHz signal, providing a clean 2. 048MHz output at pin
12 used as the reference input to the PLL phase detector (IC619 pin 14). Of the
three detecto rs inclu de d in the 7 4HC40 46, the p hase fre quen cy dete cto r (PFD) is
used by the 9200. The output of the phase detector (pin 13) feeds the loop filter
made up of resistors R607, R608 and capacitor C605 that provide a single pole
low-pass filter forming a second order loop. Pin 9 of IC619 is the input control
voltage to the VCO. Resistor R614 eliminates subharmonic frequency modulation of the VCO caused by parasitic cap acitance. Resistors R605 and R606 set the
PLL’s lock-in frequency range. A divide-by-nine counter is placed between the
VCO output and the phase dete ctor comparator input. This plac es the VCO output
at 18.432MHz. The divide-by-nine is implemented by the PLA IC618 between
pins 2 and 15. A 6.144MHz clock is derived at the cou nter’ s divide-b y-three p oint
and is provided at pin 17 of the PLA. The PLA provides a buffered 18.432MHz
output at pin 14 w hich feeds Z-180 mic roprocessor IC100.
Inverter IC605- C provide s the
buffer IC606- B, the
IC614-A, -D provide buffered clocks 2.048MHZA and 2.048MHZB for driving
the EXTAL inputs (pin 27) of the DSP ch ips. Each buffer d rives four DSP c hips.
The 128kHz clock output of IC613 (pin 14) is used for the inter-DSP word clock.
The 128kHz, 64kHz and 32kHz clocks are all used in the LCD backlight drive
circuit. The 32kHz clock is also used for th e input word clock of b oth the output
sample-rate converter (SRC) and the output D/A. The 32kHz clock is used to
generate DSP interrupt request signals (IRQBA, IRQBB) required for process
timing and interchip synchronization. The circuit consisting of flip-flop IC612
and IC614-B, -C is required to ensure that the first falling edges of all IRQB
2.048MHZC bit clock for the output SRC, IC615.
2.048MHZD bit clock fo r the o utput D/A and, via
OPTIMOD-AM Digital
signals are coincide nt. This synchro nization occurs e very time the u nit is powered
up and when there is a proc essing a lgorithm c hange. It is contr olled by the Z -180
via pin 2 of latch IC611. The 32kHz clock is also used, along with IC313, in the
A/D clock synchronizing circ uit. This circuit makes th e IRQB and the L/R clo cks,
both operating at 32kHz, phase synchronous. This ensures that the process-tooutput buff er tran sfer inter nal to the DSP doesn’ t ov erlap the output buf fer -to-p eripheral transfer. The
pin 19) is internally divided down to produce a 32kHz word clock at IC312 pin
13 and a 2.048MHz bit clock at pin 14. These clocks are used to control the
A/D-to-DSP seria l in ter fa ce and the input SRC-to-DSP serial interfa ce .
AC terminations are used on various clocks throughout the board to improve
signal integrity for sensitive devices.
8.192MHZB clock that feeds the A/D input clock (IC312
TECHNICAL DATA
Control Circuits
The control circuits process and execute user-initiated requests to the system. The source of
these requests is the front panel buttons, the rear panel RS-232 port, and the remote contact
closures. These changes affect hardware function and/or DSP processing. The control
circuits also send information to the LCD display, LED status, and LED meter circuits. A
RAM chip stores code segmen ts. For quick access, an EEPROM chip sto res dynamic system
state information. A ROM chip contains the executable form of 9200 DSP and Control
software.
6-7
1. Microprocessor and Power Monitoring Circui t
A Z-180 microprocessor executes software code required to control the functionality of the
9200. The EXTAL pin of the Z- 180 receives an 18.432MHz clo ck signal from the c lock
divider/PLL circuit and is internally divided down to 9.216MHz to provide the Z-180 system
clock frequency. ROM contains control software for the Z-180. User system setup and other
dynamic system state in formation that mus t survive power down is stor ed in non-volatile
EEPROM. Power monitoring circu itry preve nts data c orru ptio n b y p lacing an d h old ing the
Z-180 in reset if AC mains power is insufficient.
The Z-180 communicates to the DSP through the synchronous serial data host port. When
the DSP requires executable code, the Z -180 reads it from the ROM and sends it to the DSP.
The Z-180 sends parameter contr ol dat a to the DSP and receive s stat u s data fr om the DSP.
If status from DSP is irregular, the Z-180 will place the 9200 hardware and DSP in a reset
state and execute initialization procedures.
Component-Level Description:
The Z-180 is IC10 0. Watchdog timer/voltage mon itor IC1 22 provid es the system
reset function. IC122 pin 7 monitors pulses generated every 1 second by the
Z-180. If the Z-180 is not operating correctly to provide the pulses, IC122 will
reset the Z-180. IC12 2 also mo nitors the voltag e o n the +5V source that supplies
power to the 9200 digital electronics. When the +5V line is above the minimum
operating voltage of +4.75V, R103 will pull
to exit the reset condition. When the +5V line is below the minimum operating
RESET high which allows th e Z-180
6-8
TECHNICAL DATA Orban 9200
voltage, the open -collector ou tput of IC122 pulls Z-18 0’ s RESET low wh ich puts
the Z-180 into the reset condition, thereby preventing the Z-180 and the 9200
electronics from executing incorrectly due to low +5V line voltage.
Z-180 IC100 pins 55, 56, and 57 comprise the host serial data communication
port. The Z-180 uses this port to communicate with the DSP IC700-IC707 via
host port interface pins 26, 35, and 41; and with EEPROM IC107 via pins 2, 5,
and 6. Communication is SPI type with Z-180 as master and DSP as slave.
2. RAM, ROM and EEPROM
A RAM chip provides temporary storage for Z-180 data and program code segments. A
ROM chip provides permane nt storage of the executable control software and the executable
DSP software. System state in formation tha t must be main tained whi le the 920 0 is po wered
down is stored in a EEPROM. Th e E EPROM do es no t los e d ata when th e 9 20 0 is po wer ed
down.
Component-Level Description:
IC104 decodes Z-180 memory addresses to access instructions to execute from
ROM IC105 and to read or write data from 32KB RAM IC10 6. EEPROM I C107
is selected by latch IC611 pin 6.
3. Data Latches, Tri-State Data Buffers and Address Decoders
Digital logic decodes Z-180 I/O addresses, allowing the Z-180 to access RAM, ROM and
EEPROM. The logic provides Z-180 data bus allocation by using latches and tri-state data
buffers to allow other 9200 hardware to communicate to the Z-180. To control other
hardware, the Z-180’s data bus state is latched at the appropriate time, and the latched
control signals are provided to other hardware. For the Z-180 to read information from other
hardware, the Z-180’s data bus is connected at appropriate times to other hardware’s source
signals throug h tri-state data buffers (e.g. IC120).
Component-Level Description:
Decoder IC104 allows the Z-180 to access ROM IC105 and RAM IC106.
Decoders IC101, IC102, and IC103 allow the Z-180 to access all other 9200
hardware. The decoded outputs from IC101, IC102, and IC103 are used to latch
the state of the Z-180 data bus at appropriate times with data latches IC1, IC2,
IC3 IC4, IC5, IC6, IC303, IC609, IC611, IC708, and IC709, and to allocate the
Z-180 data bus at approp riate times to various per ipherals via tri-sta te data buffe rs
IC120, IC8, and IC601. IC120 buffers or tri-states status information from the
remote contact clo sure cir cuitry onto th e Z-1 80 data b us. IC8 bu f fers o r tri- states
information from the user control interface onto the Z-180 data bus. IC601 (on
digital I/O option board) buffers or tri-states status information from AES/EBU
Receiver IC600 onto the Z-180 data bus.
OPTIMOD-AM Digital
TECHNICAL DATA
User Control Interface and LED Display Circuits
The user contr ol interf ace enables the us er to c ontrol the function ality of the 9200 un it. A
rear pane l remote interface conn ector enables remote co ntrol of certain functions. Front
panel pushbutton sw itches select between various operationa l modes and functions. Da ta
latches detect and store the commands entered with these switches. Front panel status LEDs
indicate the control status of the unit, and meter LEDs indicate signal levels and processing
activity within the unit.
1. Remote and RS-232 Interfaces
A remote interface connector and circuitry enables remote control of certain operating
modes; the 9200 has eight remote contact closure inputs.
A valid remote signal is a momentary pulse of current flowing through the particular remote
signal pins. Cur rent must flow con sistently for 50 msec for the signa l to be interpreted a s
valid. Generally, the 9200 will respond to the most recent control operation whether it came
from the front panel, remote interface, or RS-232.
6-9
Component-Level Description:
J101 is a 25-pin D-connector that c onne cts the remote contro l inp ut sign als. T he
connector incorporates a ferrite block to filter out RFI from the signals. The
associated opto-isolato rs (e.g. IC1 10) isolate the inputs f rom the detector circuitry
on the 9200. The associa ted diodes (e.g. CR102) pr ev en t the opto-isolators fr om
breaking down un der a reverse bias. The outputs of the opto-isolator s are inv erted
and buffere d (e.g. by IC1 18 -A) and latched by tri-state da ta bu ffer IC120. When
REMOTE signal provided to IC120 pin 19 is brought low, IC120 places remote
signals on the Z-180 data bu s. The RS-232 inte rfac e is comprised of J100, IC121
and IC123. J100 is a 9-pin D-connector. IC121 and IC123 interface the RS-232
signals with the Z-180 micropro ce ssor.
2. Switch Matrix and LED Indicators
Eleven front panel pushbutton switches are arranged in a matrix, configured as three
columns and four rows. These switches are the primary element of the physical user
interface to the 9 200 contro l software. The host microproc essor contr ols the syste m setup
and function of the DSP accordin g to the switch/rotary encoder entered co mmands, the AES
Status bits from the Digital Input signal, the RS-232, and the remote control interface status;
and updates the LED control status indicators accordingly.
Component-Level Description:
S1-S11 are the front panel pushbutton switches. CR11-CR15 are the front panel
LED control status indicator s. V ia decoder IC102, th e host microprocessor Z-1 80
periodically sele cts data latch I C3 (on th e displa y boar d) to d rive one of the thr ee
columns in the switch matrix low, then commands tri-state data buffer IC8 (also
on the display board) to read its inputs to determine if any new information is
6-10
TECHNICAL DATA Orban 9200
being received from one or more of the switches in that column. If no switches
are closed, pull- up resistor s R25-R28 pull the buf fer in puts to +5V. The buffer, in
turn, de-bounces the signals and places the appropriate word on the data bus for
the Z-180 to re ad. T he Z-18 0 tran smi ts the upd ate d inf orma tion to data la tch I C3
which directly drives the LED Control Status Indicators.
3. LED Meter Circuits
The meter LEDs are arranged in a 6x16 matrix, in rows and columns. Each row of LEDs in
the matrix has a 1/6 duty cycle ON time. The rows are multiplexed at a fast rate so that the
meters appear continuously illuminated. Via the serial port, the DSP sends meter data values
to the Z-180, w hich s ends th e app ropr iate LED contr ol word s (8 b its at a time ) to the data
latches that drive the LEDs directly.
Component-Level Description:
The meter LED matrix consists of nine 10-segment LED bargraph assemblies
(CR1-CR9) and one discrete LED (CR10). Row selector latches IC4, IC5, and
IC6 are controlled by the Z-180, and alternately sink current through the LEDs
selected by column sele ctor latches IC1 a nd IC2, which a re also contro lled by the
Z-180. IC1 and IC2 drive the selected row of LEDs through current limiting
resistor packs RP1 and RP2.
Input Circuits
This circuitry interfaces the analog and digital audio to the DSP. The analog input stages
scale and buff er the input au dio level to match it to the ana log-to-d igital (A/D) co nverter.
The A/D converts the analog input audio to digital audio. The digital input receiver accepts
AES/EBU-format digital audio signals from the digital input connector, an d transmits them
to the input sample rate converter (SRC). The digital audio from the A/D and SRC is
transmitted to the DSP.
1. Analog Input Stages
The RF-filter ed an alo g inp ut sig na l is app lied to a r es isto r loa d and a resistor pad. The pa d
and load are enabled or disabled by jumper s that are po sitioned by hand. The loaded and
padded signal is ap plied to a floa ting-balanced amplifier that has an adjustable ( digitallycontrolled) gain . The gain is se t by FET transistors and analog switches. The sta te of the
FETs and switches is set by the outputs of a latch. The control circu its control the gain
according to what the user specifies from the front panel controls by writing data to the latch.
The gain amplif ier output feed s a circuit that sc ales, balances, and removes DC fro m the
signal. This circ uit feeds an RC low-pass filter which applies the bala nced signal to the
analog-to-digital (A/D) converter.
Component-Level Description:
The balanced audio input signal is applied to the filter /load/pad network made up
of L300, L301, L3 02, L 303, R300 -R30 5, R3 16-R31 9, a nd C32 3- C326 . J3 01 is a
OPTIMOD-AM Digital TECHNICAL DATA
jumper that r emov es or inser ts the o ptiona l 600 Ω termin ation loa d (R300) on the
input signal. J302 and J303 are the jumpers that remove or insert the resistive
divider (R301-R303) that pads the input signal before it is applied to IC300, a
differential amplifier. R306, R307, R310-R313, FETs Q300-Q301, and quad
analog switch IC307 make up the circuit that sets the gain of IC300. The FETs,
along with IC307, are used as switches to chan ge the resistive paths in the circ uit.
The state of the FET switches is set by the outputs of digital latch IC303. The
latch outputs feed IC306 , a quad com para tor, which outp uts 0V to tur n on a FET
and −15V to turn off a FET. The control circuit writes dir ectly to I C307 to con trol
the state of the switches on IC307. IC300 feeds IC302 and associated components. This stage balances the signal to drive the analog-to-digital (A/D) converter . IC301-B and associate d component s comprise a servo amp to pre vent DC
from passing to the DSP. R334, R337, C302, and C303 make a simple RC filter
necessary to filter high frequency energy that would otherwise cause aliasing
distortion in the A/D converter.
2. Analog-to-Digital (A/D) Converter
The A/D is an 18-bit sigma-delta converter , impleme nte d on a dual- ch ip in teg ra ted circu it.
The A/D oversample s the audio a t 2.048MHz. It a pplies noise sh aping, then it filte rs and
decimates to a 32kH z sample rate. The samples are outpu t in two’s complement, 32-bit
word, two-word frame serial format, MSbit first, and transmitted to the DSP. The 32kHz
frame clock a nd 2. 048MH z bit clo ck fr om the A /D fun ction a s maste r cloc ks fo r the 9200
input to the DSP. For more information on 92 00 input clocking, please refer to “16.384MHz
Oscillator and System Clocking.”
6-11
Component-Level Description:
The balanced analo g input is app lied to pins 3( +) and 4(−), and also to pins 26(+)
and 25(−) of the A/D (IC312). The maximum dif fer ential signal that the A/D can
accept is ±7.36Vpea k. The A/D samples these inputs simultaneously at 64 times
the 9200 sample rate of 32kHz. ICLKD, the master clock input of the A/D (pin
19), is fed an 8.192MHz clock providing the 2.048MHz input sample rate
required. The bit clock SCLK (pin 14) of the A/D is inverted by IC605-F. This
signal, along with the data SDATA (pin 15) and word clock L/
buffered by IC314-A, -B, -C, and -D, and fed to the serial port of the first DSP
chip (IC700). IC3 14 red uces the drive requir emen t of the on-bo ard drive rs on the
A/D and ensures that there are no overshoots or undershoots as a result of
transmission line reflections that may degrade the performance of the A/D.
R (pin 13), are
3. Digital Input Receiver and Sample Rate Converte r (SRC)
The digital input r eceiver (on d igital I/O option b oard) acc epts digital au dio signals usin g
the AES/EBU interface format (AES3-1992) . T he receive r and input samp le rate co nverter
(SRC) together wi ll a ccep t a nd sam p le- rat e co nv ert a ny o f t he “ sta nd ard” 3 2k Hz, 4 4. 1k Hz,
48kHz rates in addition to any digital audio sample rate within the rang e of 25kHz and
55kHz. The audio signa l receive d is deco ded b y the AES re ceiver and sent to the SRC. The
SRC converts the input sample rate to the 32kHz 9200-D system sample rate. Via a
6-12
TECHNICAL DATA Orban 9200
synchronous serial interface, the SRC sends the 32kHz sample rate audio to the DSP for
processing.
Component-Level Description:
The differential digital input signal is received through a shielded 1:1 pulse
transformer (T600). T600 has very low inter-winding capacitance, providing a
high level of isolatio n for hig h fre quency com mon mode in ter fere nc e. I C600 is a
dedicated AES/EBU digital audio receiver integrated circuit. It contains a phase
locked loop that recovers the clock and the synchronization information present
in the AES/EBU signal. A Schmitt trigger at the input pro vid es 5 0mV of hy ste resis for added noise immunity. R600 provides a 110Ω input impedance per the
AES/EBU specification.
The Z-180 provides the active high reset signal (AES_RST) to IC600 mode
control pins 17, 18, 23 and 24, via latch IC609 pin 6. This is used when the
9200-D is asked to respond to analog audio input. When in the reset state, the
receiver holds all outputs inactive (except MCK pin 19).
IC600 pins 2 through 6 and pin 27 are an output latch that provides AES/EBU
status information, selected by the STATSEL line. The information on this latch
is provided to the Z- 180 data bus via tr i-state data buf fer I C601. STA TSE L signal
from IC609 pin 12 is applied to IC600 pin 16. When STATSEL is high, pins 2
through 6 and pin 27 contain information about the channel status bits. When
STATSEL is low, pins 2 thr ough 6 a nd pin 27 con tain in put sam ple rate and err or
information. The Z-180 reads these to determine if a valid AES/EBU signal and
sample rate is present. CHSEL is used to select whether channel A or channel B
status bits are present on IC600’s output latch. When ST ATSEL is low , channel A
status is made available, and when STATSEL is high, channel B is made available.
Received AES audio is tr ansmitted from the AES r eceiver to the in put sample rate
converter (SRC IC603). The AES receiver is master and the SRC is slave. The
AES receiver ou tput s data on pin 26, th e bit clo ck on pin 12, and the fr ame clo ck
on pin 11. These signals are sent to the SRC serial input interface pins 3, 4, and
6 respectively.
The MCK clock output at pin 19 of the AES receiver chip has a frequency 256
times the input sample rate of th e receiv ed sig nal. This is use d to drive the outpu t
AES/EBU transmitter when an output sa mple rate that is synchro nous to the input
sample rate (extern al sync ) i s requ ire d.
The crystal oscillator (Y602) provide s the SRC a maste r clock of 16.384MHz on
pin 2. This MCLK frequency allows the input SRC to operate with input sample
rates in the range of 8.192kHz (MCLK/20 00) to 57kHz (MCLK/286). S RC_RST
is an active low reset sign al tied to pin 13 of the SR C. This signal is con trolled by
the Z-180 via pin 2 of latch IC609.
The MSDLY_I, BKPOL_I, and TRGLR_I pins of the SRC chip configure the
chip to interface with the AES/EBU receiver chip. Pin 1 of the SRC (GPDLYS)
is tied high to minimize the chip’s group delay to approximately 700µs as
OPTIMOD-AM Digital TECHNICAL DATA
opposed to approximate ly 3ms, g iving up som e toler ance to var iatio ns in sample
rates. Pin 28 (SETLSLW) is tied high to cause the SRC to settle slowly to changes
in sample rates, resulting in the be st re jec tion of sample rate jitter.
The sample rate converted output of the input SRC feeds the first DSP chip
(IC700). The SRC output port and the DSP input port ar e both slaves, with clocks
supplied by the input A/D conve rter ( IC312) . The SRC gene rates DIG_ IN (da ta)
on pin 23, and receives the bit clock and the word clock on pins 26 and 24
respectively.
Output Circuits
This circuitry interfaces the DSP to the analog and digital audio outputs. The digital audio
from the DSP is transmitted to the digital-to-analog converter (D/A) and output sample rate
converter (SRC). The digital-to-analog (D/A) converter converts the digital audio words
generated by the DSP to analog ou tput aud io. T he analog output stage s scale a nd bu ffer the
D/A output signal to drive the analog output XLR connectors with a low impedance
balanced output. The digital output transmitter acc epts the digital audio words from the
output sample rate converter (SRC) and transmits them in AES/EBU-format digital audio
signals on the digital output connector.
6-13
1. Digital-to-Analog (D/A) Converter
The D/A is a single chip, two-channel, 18-bit delta-sigma converter.
For information on 9200 system clocking, please refer to “16.384MHz Oscillator and
System Clocking.”
Component-Level Description:
IC400 is the digital-to- an alo g ( D/A) c on ve rte r f or the two analog output sig na l s.
The synchronous serial input interface consists of the bit clock, data and latch
enable pins that are c onfigured for th e interface to DSP IC-707 via DIF0 and DIF1
pins. The processed digital output (ANLG_OUT) is provided by DSP IC707 on
its SAI output port SDO2 (pin 45), and is rece ive d by the D/A on pin 18.
A 2.048MHz bit clock is provided from the system clock circ uitry to both the final
DSP and the D/A chips. The DSP output data format is 32 bits per word, two
words per frame. DSP chip IC707 rec eives a 3 2kHz fr ame clo ck at its WST inpu t
(pin 50) that sets the word transfer rate to two words pe r 32kHz p eriod . The D/A
receives a 32kHz clock at its LRCK input (pin 20). LRCK delineates the two
samples per frame that are fed to the D/A to create the 9200’s two independent
analog output signals. The DSP output samples are formatted to ensure that the
D/A uses samp les that re pr esen t the sim ulta ne ou sly sampled analog input.
2. Analog Output Stages
The two analog signals e merging from the digita l-to-ana log (D/A) converter are eac h RC
low-pass filter ed and applied to an attenuator /gain amplifier, which is a djusted via front
6-14
TECHNICAL DATA Orban 9200
panel potentiometers. The ba lanced line d river outp uts are a pplied to the RF-filtered a nalog
output connectors.
Component-Level Description:
The signal emerging from the digital-to-analog (D/A) converter pin 2 is RC
low-pass filtered by R40 2 and C4 07 to r em ov e h igh fr eq ue nc y im ag es. I t i s then
applied to an attenuator/gain amplifier formed by VR500, IC403 and associated
components. This stage is a balanced line driver.
IC402-A, R430, R435 and C423 comprise a servo a mplifier which cente rs around
ground the DC level at output conne ctor J400.
The balanced audio output signal is applied to the RF filter network made up of
R409-R414, C4 1 1, C41 2, C420 , C421, L400, L 401, L402, a nd L4 03, a nd then to
XLR connector J400.
The circuitry corre sponding to the second output ch annel is functiona lly identical
to that just described.
3. Digital Sample Rate Converter (SRC) and Output Transmitter
An output samp le rate conv erter (SRC) ch ip (on dig it al I/O o pti on board) is use d to conv ert
the 32kHz 9200-D system sample rate to any of the standard 32kHz, 44.1kHz or 48kHz
rates. A digital audio interface transmitter chip is used to encode digital audio signals using
the AES/EBU interface format (AES3-1992). A synchro nous serial interface is used for al l
inter-chip communication.
Component-Level Description:
The processed dig ital ou tpu t ( DIG_ OUT) provided a t th e SAI output port SDO0
(pin 47) of DSP IC70 7 is rec eived by asyn chrono us sample rate con verte r (SRC)
IC615 pin 3. A 2.048MHz bit clock is provided from the system clock circuitry
to both the final DSP an d the SRC chips. DSP chip IC707 rec eives a 32kHz fra me
clock at its WST input (pin 50) that sets the word transfer rate to two words per
32kHz period. The SRC receives a 32kHz clo ck a t its L /
delineates the samples of the two channels used by the SRC (both channels
receive the same signal). The DSP output samples are formatted to en sure that the
SRC uses samples that represent the simultaneously sampled analo g input.
The crystal oscillator (Y602) provide s the SRC a maste r clock of 16.384MHz on
pin 2. This MCLK frequency allows the output SRC to operate with an output
sample rate in the range between 30kHz and 57kHz. SRC_RST is an active low
reset signal tied to pin 13 of the SRC. This signal comes from multiplexer chip
IC610 and is controlled by the Z-180 via either pin 2 of latch IC609 or pin 8 of
IC605-D.
R_I input (pin 6). L/ R_I
The MSDLY_I, BKPOL_I, and TRGLR_I pins of the SRC chip configure the
chip for to interface with the last DSP chip (IC70 7). Pin 1 of th e SRC (GPDLYS)
is tied high to minimize the chip’s group delay to approximately 700µs as
OPTIMOD-AM Digital TECHNICAL DATA
opposed to approximate ly 3ms, g iving up som e toler ance to var iatio ns in sample
rates. Pin 28 (SETLSLW) is tied high to cause the OSRC to settle slowly to
changes in sample rates, re sulting in the be st re jec tion of sample rate jitter.
The output side of the sample rate converter is tied directly to IC616, an
AES/EBU digital audio transmitter integrated cir cuit. This interface use s the AES
transmitter chip as master . The tra nsmitter chip encode s the audio data it receiv es
to the AES/EBU interface standard, and transmits it.
The SRC output sample rate and the sample rate that the AES/EBU transmitter
transmits with is based on the MCK clock provided to pin 5 of IC616 . This clock
is received via digital multip lexer chip IC610 whic h is used to sele ct o ne of four
available clocks. Three free running clocks provide the standard sample rates of
32kHz, 44.1kHz an d 48kHz wh en a n internal sync is r equested. These clocks r un
at a frequency that is 128 or 25 6 times the sample r ate th ey r ep re se nt. T he y ha ve
a frequency stability of ±100PPM. The fourth clock is the EXTMCK clock that
is recovered from the AE S/EBU receive r chip. T his clock ha s a freque ncy of 256
times the input sample rate of th e receiv ed sig nal. This is use d to drive the outpu t
AES/EBU transmitter when an outpu t sample rate i s required tha t is synchronous
to the input sample rate (external sync).
6-15
The inter-chip serial data format, the input MCK multiplication factor, and the
output channel status data are controlled by the Z-180 via internal control
registers and data memory a ccessed through the p arallel port mad e up of the 5-bit
address bus (pins 9-13), the 8-bit data bus (pins 1-4, 21-24) and the
RD/
WR control pins (pins 14 an d 16 ) of IC616 .
The on-chip RS422 lin e driver provide d by IC616 i s a low skew, low impedance,
differential output capable of driving a 110Ω transmission line with a 4Vp-p
signal. Shielded 1:1 pulse transformer T601 transmits the differential digital
output signal to XLR connector J601. T601 has very low inter-winding capacitance, providing a high level of isolation from high frequency common mode
interference.
CS and
DSP Circuits
The DSP circuits consist of eight gene ral purpose DSP chips that execute DSP so ftware code
to implement digital signal processing algorithms. The algorithms filter, compress, and limit
the audio signal. The eight DSP chips, operating at 25 million instructions per second
(MIPS) for a to tal of 200MI PS, prov ide th e nece ssary signa l proce ssing . A 32k Hz samp ling
rate is used. Two of the on-boa rd seria l audi o inte rface (SAI) perip herals o n each DSP c hip
are used to transfer data chip-to-chip at a 16.384Mbit/s rate maintaining a 24-bit word
length. The DSP chips are cascaded, processing the audio serially. The first chip receives
the analog input via the A/D chip and the digital input via the SRC chip. Input source
selection is performed seamlessly, internal to the DSP chip.
During system initialization (which normally occurs when power is first applied to the
9200), and when processing algorithms are changed, the Z-180 downloads the DSP executable code stored in the ROM, via th e serial ho st inter face (SHI ) por t of each DSP ch ip.
Once a DSP chip begins exe cuting its program, exec ution is continuous . The Z-180 provid es
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