OPTi ChromaCast 82C205 Preliminary Programmer’s Manual
®
ChromaCastChromaCast
82C205
LCD Monitor Controller
Preliminary Programmer’s Guide
CONFIDENTIAL
Revision 1.0
915-2000-084
11/22/99
Copyright
Copyright © 1999 OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted,
transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by
any means, electronic, mechanical, magnetic, optical, manual, or otherwise, without the prior written permission of
OPTi Inc., 1440 McCarthy Blvd. Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and
especially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc.
reserves the right to revise the design and associated documentation and to make changes from time to time in the content
without obligation of OPTi Inc. to notify any person of such revisions or changes.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property
of their respective holders.
OPTi Inc.
1440 McCarthy Blvd.
Milpitas, CA 95035
Tel: (408) 486-8000
Fax: (408) 486-8001WWW:
http://www.opti.com
Programmer's Guide
®
ChromaCast 82C205
Table of Contents
INTRODUCTION........................................................................................................................................................1
NOMENCLATURE.....................................................................................................................................................2
CHOOSING CHROMACAST 82C205 HARDWARE CONFIGURATION .................................................................3
CONFIGURING CHROMACAST 82C205 FOR A SPECIFIC PANEL......................................................................3
DISPLAY CRTC PROGRAMMING..............................................................................................................................4
Pixel Clock Frequency (in MHz):...................................................................................................................4
Horizontal Sync Polarity: ...............................................................................................................................4
Horizontal Sync Width (in units of pixel clock)...............................................................................................5
Horizontal Display Start (in units of pixel clock) ............................................................................................5
Horizontal Display End (in units of pixel clock)..............................................................................................5
Horizontal Total (in units of pixel clock).........................................................................................................6
Vertical Sync Polarity.....................................................................................................................................6
Vertical Sync Width (in units of video lines) ..................................................................................................6
Vertical Display Start (in units of video lines)................................................................................................6
Vertical Display End (in units of video lines) .................................................................................................7
Vertical Total (in units of video lines).............................................................................................................7
Panel Window Default Settings.....................................................................................................................7
DISPLAY TIMING WAVEFORMS.................................................................................................................................8
Vertical Timing for TFT Panel........................................................................................................................8
Horizontal Timing for TFT Panel....................................................................................................................9
Detail of Pixel Clock Timing...........................................................................................................................9
VGA VIDEO INPUT INTERFACE ............................................................................................................................11
CALCULATING THE HORIZONTAL SYNC FREQUENCY (F
CALCULATING THE REFRESH RATE OR VERTICAL SYNC FREQUENCY (F
DETERMINING THE RESOLUTION OF THE INCOMING VGA........................................................................................12
DETERMINING THE FREQUENCY OF THE PIXEL CLOCK USED BY THE VGA ...............................................................12
DETERMINING THE POLARITY OF THE HORIZONTAL AND VERTICAL INCOMING SYNCS..................................................12
CAPTURE CRTC PROGRAMMING ..........................................................................................................................12
HORIZONTAL SYNC WIDTH (IN UNITS OF VCLK1)...................................................................................................13
)OF THE INCOMING VGA...............................................11
HSYNC
) OF THE INCOMING VGA.....................11
VSYNC
HORIZONTAL DISPLAY START (IN UNITS OF PIXEL CLOCK)........................................................................................13
HORIZONTAL DISPLAY END (IN UNITS OF PIXEL CLOCK)...........................................................................................13
HORIZONTAL TOTAL (IN UNITS OF PIXEL CLOCK) .....................................................................................................13
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VERTICAL SYNC WIDTH (IN UNITS OF VIDEO LINES).................................................................................................13
VERTICAL DISPLAY START (IN UNITS OF VIDEO LINES).............................................................................................14
VERTICAL DISPLAY END (IN UNITS OF VIDEO LINES) ................................................................................................14
VERTICAL TOTAL (IN UNITS OF VIDEO LINES)...........................................................................................................14
PROGRAM THE CAPTURE CRTC TO SYNCHRONIZE TO EXTERNAL SYNCS ...............................................................15
DITHER.....................................................................................................................................................................17
SCALING ..............................................................................................................................................................17
Setting the Input Resolution for the Scaler..................................................................................................17
Setting the Output Resolution......................................................................................................................18
Setting the Scaling Ratios ...........................................................................................................................18
Horizontal Ratio:..........................................................................................................................................19
FINE TUNING THE SCALERS...................................................................................................................................19
USING THE ANTI-ALIAS FILTER..............................................................................................................................20
“CENTERING”.........................................................................................................................................................21
HOW THE DISPLAY WINDOW AFFECTS THE SCALER ...............................................................................................21
SETTING THE PANEL WINDOW REGISTER WITHOUT “CENTERING” ...........................................................................21
CONTRAST AND BRIGHTNESS ADJUSTMENT ..................................................................................................23
DIGITAL CONTRAST ..............................................................................................................................................23
DIGITAL BRIGHTNESS............................................................................................................................................23
THE ON SCREEN DISPLAY....................................................................................................................................25
DETERMINING OSD SIZE......................................................................................................................................25
DETERMINING OSD LOCATION ON SCREEN ...........................................................................................................25
SELECTING OSD ATTRIBUTES ..............................................................................................................................25
ALPHA BLEND OPERATION....................................................................................................................................26
CONTENTS OF THE REGISTER COLOR LOOK-UP TABLE ..........................................................................................26
TRANSFERRING BITMAP FROM CPU ROM TO DISPLAY ..........................................................................................26
MEMORY CONFIGURATION AND ALLOCATION.................................................................................................27
BYPASSING THE MEMORY SUBSYSTEM..................................................................................................................27
CONFIGURING THE DRAM INTERFACE...................................................................................................................27
Selecting DRAM speed................................................................................................................................27
Programming the refresh rate......................................................................................................................28
Specifying the burst length and type, and CAS Latency.............................................................................28
Additional memory configuration settings....................................................................................................28
DRAM BUFFER ALLOCATION................................................................................................................................29
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Allocating the DRAM space to each buffer..................................................................................................29
VGA Frame Buffer.......................................................................................................................................30
TV Frame Buffers ........................................................................................................................................30
OSD Buffer ..................................................................................................................................................31
Display Read Out from Frame Buffers ........................................................................................................31
CPU Scratch RAM.......................................................................................................................................32
TESTING AND DEBUGGING..................................................................................................................................33
INTERNAL TEST PATTERNS ...................................................................................................................................33
SOFTWARE RESETS AND DISABLES.......................................................................................................................33
REVISION NUMBER...............................................................................................................................................34
FIFO STATUS ......................................................................................................................................................34
SIGNATURE ANALYZERS .......................................................................................................................................34
CPU MEMORY READ BUFFER...............................................................................................................................34
MEMORY SUBSYSTEM STATUS..............................................................................................................................35
MISCELLANEOUS..................................................................................................................................................35
TV MODE SETUP ....................................................................................................................................................37
SELECTING BETWEEN 8-BIT AND 16-BIT TV DECODER INTERFACE ...........................................................................37
DETERMINING IF TV PHASE IS CORRECT ...............................................................................................................37
REQUIRED SYNCHRONIZATION SIGNALS FROM THE TV DECODER............................................................................37
ENABLING TV MODE.............................................................................................................................................37
PROGRAMMING THE CRTC FOR TV MODE............................................................................................................38
PROGRAMMING THE SCALERS FOR TV MODE ........................................................................................................38
IP CONVERSION...................................................................................................................................................38
Bob Mode ....................................................................................................................................................38
CPU INTERFACE.....................................................................................................................................................41
CPU ACCESS TO THE REGISTERS.........................................................................................................................41
CPU ACCESS TO THE DRAM BUFFER ..................................................................................................................41
INTERRUPTS.........................................................................................................................................................42
Enabling an event to generate an interrupt.................................................................................................42
The interrupt/event status register...............................................................................................................42
Clearing an interrupt/event..........................................................................................................................43
POWER MANAGEMENT FOR CHROMACAST 82C205 .......................................................................................45
TIMER..................................................................................................................................................................45
Setting the timer interval..............................................................................................................................45
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Timer Operation Procedure.........................................................................................................................45
POWER SEQUENCING ...........................................................................................................................................45
DPMS POWER MANAGEMENT ..............................................................................................................................46
Notifying the CPU of the DPMS state..........................................................................................................46
Monitor is disconnected from the VGA controller........................................................................................46
ChromaCast 82C205 Power Conservation Techniques..............................................................................46
Example of Power Conservation Policy for DPMS......................................................................................47
APPENDIX A: EXAMPLE REGISTER INITIALIZATION VALUES.........................................................................49
APPENDIX B: COMMON VGA TIMING VALUES...................................................................................................51
APPENDIX C: VCLK2 PLL M & N VALUES...........................................................................................................53
APPENDIX D: CHROMACAST OSD (ON-SCREEN DISPLAY) USER'S GUIDE..................................................57
ENABLING OSD....................................................................................................................................................57
SUPPORTED FUNCTIONS.......................................................................................................................................57
Front Panel input buttons description..........................................................................................................57
RESET .................................................................................................................................................................57
SELECT................................................................................................................................................................57
ADJUST................................................................................................................................................................57
MODE ..................................................................................................................................................................57
RESET BUTTON.....................................................................................................................................................57
MODE BUTTON .....................................................................................................................................................57
DESCRIPTION OF SUPPORTED ICONS.....................................................................................................................58
Contrast Icon: ..............................................................................................................................................58
Brightness Icon:...........................................................................................................................................58
Horizontal position Icon: ..............................................................................................................................58
Horizontal Screen size Icon:........................................................................................................................58
Vertical Position Icon:..................................................................................................................................58
Vertical Screen Size Icon:............................................................................................................................58
Focus Icon:..................................................................................................................................................58
OPTi Icon:....................................................................................................................................................58
Recall Icon:..................................................................................................................................................59
USER Recall mode......................................................................................................................................59
Factory Recall mode....................................................................................................................................59
VGA or TV input Select mode Icon..............................................................................................................59
Exit menu.....................................................................................................................................................59
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OSD Description Language Select..............................................................................................................59
MANUFACTURE DEBUGGING MODE.........................................................................................................................60
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Introduction
This is the programmer’s guide for the ChromaCast 82C205 LCD Monitor Controller. It is an application note for
the ChromaCast 82C205 Databook that contains detailed register descriptions. This guide will walk the
programmer through the various programming sequences necessary in order to build a customized LCD monitor
control application.
The ChromaCast 82C205 Monitor Controller is a controller for LCD Flat Panel Monitors. The 82C205 performs
several functions including:
• clock generation for the display, and memory,
• scaling,
• frame rate conversion,
• television mode support,
• on screen display menu overlay,
• dithering,
• power management.
The 8051 compatible micro-controller interfaces to the ChromaCast 82C205 LCD Monitor Controller and assists
in the configuration process so the 82C205 can be enabled to perform the above functions. The 8051 will be
referred to hereafter as the CPU or micro-controller.
The CPU initializes the registers of the 82C205, enabling the 82C205 to accept different incoming resolutions and
refresh rates, and allows the 82C205 to interface with many different types of flat panels. In addition, the CPU
provides the on-screen display (OSD) bitmap data to the 82C205, as well as the EDID data used in the Display
Data Channel (DDC). The objective of this programmer’s guide is to present a logical description of each major
function of ChromaCast 82C205 and a methodology for programming these functions. Suggested programming
procedures and values will be included.
This guide is divided into the following sections:
q Configuring ChromaCast 82C205 for a Specific Panel
This section details how to configure ChromaCast 82C205 for a particular panel. Issues such as the
number of bits per pixel that the panel supports, number of pixels per clock, panel resolution, and the
timing of the panel synchronization signals are discussed. In order to configure the ChromaCast 82C205
properly, the programmer must have a copy of the panel timing specification.
q VGA Video Input Interface
This section details how to detect the incoming resolution and synchronization timing from the VGA, as
well as how to program the ChromaCast 82C205 to accept the incoming VGA signal.
q Scaling
This section details how to program the ChromaCast 82C205 Scaler. The 82C205 can display the
incoming video at its original resolution, or it can scale the video up or down to match the panel size. The
video can be displayed full scale on the panel, or in a “centered” mode at its original resolution
surrounded by a black border.
q On Screen Display
This section details how to overlay an on screen display on top of the video path. Issues such as size and
location of the OSD, color depth, attributes, and other tradeoffs are discussed.
q Memory Configuration and Allocation
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This section details how to program the 82C205 so it can interface with the DRAM. This section also
allocates the DRAM to buffers for use by the ChromaCast 82C205.
q Testing
This section indicates what sort of testing and debug options are available on the ChromaCast 82C205.
q TV Mode
This section details how to operate the TV mode on the 82C205. The ChromaCast 82C205 interfaces
with an NTSC/PAL decoder and accepts YUV 4:2:2 format. ChromaCast 82C205 performs a YUV to RGB
color space transform and then performs interlace-to-progressive (IP) scan conversion. Discussions of
different interlace-to-progressive conversion options are included.
q CPU Interface
This section explains the CPU interface to the ChromaCast 82C205, including addressing for the
registers, and the DRAM buffer. The interrupt sources are also explained.
q Power Management
This section explains how to operate the general purpose timer on the 82C205, as it is an integral part of
the power management system. Power sequencing for power-up and power-down on the panels is
explained, as well as policies for DPMS power management.
q Example Register Values for ChromaCast 82C205
Appendix A offers an snapshot of the register values during operation of the 82C205. The setup is for a
1024x768, 60 Hz panel accepting a 1024x768, 70 Hz VGA input.
q Common VGA Timing Values
Appendix B includes some common VGA Timing values that describe the incoming VGA signal.
q Memory and Display Clock Programming Table
Appendix C includes the programming settings for the internal PLLs for memory clock and display clock
frequencies.
q On-Screen Display (OSD) User's Guide
Appendix D provides a preliminary user's guide for the use of the On-Screen (0SD) to configure
ChromaCast to provide the most satisfactory image.
Nomenclature
Numbers representing different bases will be denoted as follows: A hexadecimal number will be followed by a
lower case “h”, as in A5h. A number without an “h” appended to it will be assumed to be a decimal value.
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Choosing ChromaCast 82C205 Hardware Configuration
ChromaCast 82C205 has a 24-bit digital interface that can be used with a PanelLink or LVDS receiver or external
A/D converters. In addition to an external A/D converter, ChromaCast 82C205 supports external clock sources.
It is recommended that the system uses an external Reference Clock source and shares the Reference Clock
(14.318 MHz) with the CPU system clock.
Internal/External Hardware Selection
Internal/External
Memory Clock
Select
Internal/External
Display Clock Select
Register FCh, Bit[3]
Register FCh, Bit[2]
1 = internal clock
0 = external clock
Configuring ChromaCast 82C205 for a Specific Panel
Before beginning, the programmer will need a specification for the panel. The following information should be
extracted from the specification:
• Total Number of Data Lines to Panel
• Bits Per Pixel
• Pixels Per Clock
• Power Sequencing Timing
• Timing for the Horizontal and Vertical Syncs, and Display Enable (DE)
ChromaCast 82C205 uses a resistor strap option at power up to specify some of the above parameters. VESA
naming conventions as referenced in FPDI-1 are used. The following naming conventions are used:
• A = Active, i.e. TFT display
• S = Single Scan. STN and TFT displays are single scan.
For instance, a TFT display with 12-bit color and a 24-bit data interface would be referred to as A-444-S24. The
“444” term indicates 4 bits red, 4 bits green, and 4 bits blue. Using this nomenclature, select the panel type that is
applicable and set the strapping resistors appropriately. Refer to the databook for details on the strapping options.
The strapped panel type can be read from a register.
Panel Type
Panel Type
(Read only)
In addition to the strap option, bits per pixel (per color component) must be specified. For example, if the panel
supports 18 bits per pixel (bpp), then the dither “Primary Bits” value should be programmed to 6. (The RGB data
is digitized into 24-bpp values, hence to display 18-bpp, a dithering algorithm must be utilized.) For reasons of
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bandwidth or other tradeoffs, the captured data can be also be dithered to a bpp value that is smaller than the
panel supports. The panel drive reformat module will then automatically “scale” the bpp up to the panel
specification. So at the expense of some color depth, an 18 bpp panel could be driven with only 9 bpp captured,
and the 82C205 will automatically format the data to 18 bpp; however, the resultant image will actually only
display 29 colors, instead of the desired 218. There are other dither options, but these will be discussed later. For
very large OSDs or high refresh, high resolution VGA modes, bandwidth can become critical.
Primary Color Bits
Primary Bits Register 38h, Bits[7:4]
Display CRTC Programming
The following parameters for the Display CRTC timing, including pixel clock frequency, horizontal and vertical
sync timings, timing for DE, and polarities of the horizontal and vertical syncs are determined by the specification
for the panel that the ChromaCast 82C205 is controlling.
Pixel Clock Frequency (in MHz):
The panel is driven by a pixel clock, which is the same clock that drives the display subsystem of the ChromaCast
82C205. This pixel clock frequency for a TFT panel is generally between 25 – 108 MHz. This clock can be
generated by an internal PLL within the 82C205 or by an external crystal oscillator. On the panel specification,
this clock is normally called FPSHIFT or FPS. The frequency requirement for this panel must be read from the
panel specification. Call this value FPSF. Then program the VCLK2 PLL so that it outputs the FPSF frequency:
The reference clock for the VCLK2 PLL is 14.318 MHz. Program the N and M values of the PLL (the divider ratio)
so the PLL will generate FPSF frequency. The formula is FPSF = 14.318 MHz * N / M. A table of suggested values
for M and N is included in the Appendix. Unless the display clock needs to be very low frequency, or the duty
cycle needs to be adjusted, the divide by 2 option for the VCLK2 PLL can remain disabled.
One more detail about the pixel clock that needs to be determined is whether or not the clock is gated, i.e. is the
clock continuously toggling, or is it gated so that it is only toggling when data is valid. Most DSTN displays require
a gated clock, while TFT panels do not.
The last pixel clock specification that needs to be programmed is whether the panel data is stable on the falling
edge of pixel clock or the rising edge.
Pixel Clock Frequency
Gated Clock Register A1h, Bit[2]
Clock Phase Register A1h, Bit[3]
Divide Clock by 2 Register C6h, Bit[6]
M Values Register C6h
N Values Register C7h
Horizontal Sync Polarity:
This register sets the polarity of the horizontal sync to the panel. It has no relationship to the polarity of the
incoming sync from the VGA.
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Note: Polarity can be defined as follows: If the sync is high while data is active, then it is an active low sync. If the
sync is low while data is active, then is it an active high sync.
Horizontal Sync Polarity
Polarity Register A1h, Bit[0]
Horizontal Sync Width (in units of pixel clock)
The width of the active part of the sync (when data is not valid).
Horizontal Sync Width
Sync Width Register 82h, 83h
Horizontal Display Start (in units of pixel clock)
This is the time between the start of the horizontal sync and the start of data valid. For TFT displays, special
attention must be given to where the data ready line goes active (DRDY or DE) in order to determine this value.
Hence, this timing specification refers to the time between the start of the horizontal sync and the first pixel clock
following the horizontal sync. The value of the Horizontal Display Start must be an odd number
Horizontal Display Start
Display Start Register 84h, 85h
Horizontal Display End (in units of pixel clock)
This is the time between the start of the horizontal sync and the end of data valid.
Horizontal Display End
Display End Register 86h, 87h
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Horizontal Total (in units of pixel clock)
This is the period of Horizontal Sync.
Horizontal Total
Total Register 80h, 81h
Vertical Sync Polarity
This register sets the polarity of the vertical sync to the panel. It has no relationship to the polarity of the incoming
sync from the VGA.
Note: Polarity can be defined as follows: If the sync is high while data is active, then it is an active low sync. If the
sync is low while data is active, then it is an active high sync.
Vertical Sync Polarity
Polarity Register A1h, Bit[1]
Vertical Sync Width (in units of video lines)
The width of the active part of the sync (when data is not valid).
Vertical Sync Width
Sync Width Register 8Ch, 8Dh
Vertical Display Start (in units of video lines)
This is the time between the start of the vertical sync and the start of data valid.
Vertical Display Start
Display Start Register 8Eh, 8Fh
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Vertical Display End (in units of video lines)
This is the time between the start of the vertical sync and the end of data valid.
Vertical Display End
Display End Register 90h, 91h
Vertical Total (in units of video lines)
This is the period of the vertical sync. For ALL panels, if the vertical total value does not differ between even and
odd frames, enter the same value for vertical total in the even vertical total register as in the odd vertical total
register.
Vertical Total
Odd Total Register 88h, 89h
Even Total Register 8Ah, 8Bh
Panel Window Default Settings
Later in this guide the centering option will be discussed, which allows a low resolution image to be displayed on a
higher resolution panel, surrounded by a black border. Until that discussion, assume that the incoming image is
scaled to the full panel size, hence the following Panel Window Registers should be set to the corresponding
values in the Display CRTC as a default.
• Panel Window Horizontal Start = Display CRTC Horizontal Start (Registers 84h, 85h) + 11h
• Panel Window Horizontal End = Display CRTC Horizontal End (Registers 86h, 87h) + 11h
• Panel Window Vertical Start = Display CRTC Vertical Start (Registers 8Eh, 8Fh)
• Panel Window Vertical End = Display CRTC Vertical End (Registers 90h, 91h)
Panel Window Registers
Panel Window
Horizontal Start
Panel Window
Horizontal End
Registers 98h, 99h
Registers 9Ah, 9Bh
Panel Window
Vertical Start
Panel Window
Vertical End
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Registers 9Eh, 9Fh
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FPFRAME
FPLINE
DE (DRDY)
DATA
ChromaCast 82C205
Display Timing Waveforms
Signal Description Symbol Min Typical Max Unit
FPFRAME
Vertical Total t
V Sync Width t
Vertical Display Start t
Vertical Display End t
FPLINE
Horizontal Total t
H Sync Width t
Horizontal Display Start t
Horizontal Display End t
DE Data Valid t
FPSHIFT Pixel Clock Frequency t
Vertical Timing for TFT Panel
t
1
0
1
2
3
5
0 4095 Lines
0 4095 Lines
0 4095 Lines
0 4095 Lines
0 4095 Pixel
Clock
6
0 4095 Pixel
Clock
7
0 4095 Pixel
Clock
8
0 4095 Pixel
Clock
10
0 4095 Pixel
Clock
11
t
0
10 120 MHz
t
2
t
3
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Horizontal Timing for TFT Panel
…
FPLINE
DE (DRDY)
DATA
DE (DRDY)
FPSHIFT
DATA
Detail of Pixel Clock Timing
ChromaCast 82C205
t
t
6
t
7
5
t
8
t
10
t
11
* Polarity of FPFRAME, FPLINE, & FPSHIFT is programmable.
* One and Two Pixels Per Clock are supported.
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VGA Video Input Interface
The video data input interface includes a 24-bit digital input port which can be used to interface an external A/D
converter or a PanelLink or LVDS receiver, and an 8/16 bit interface (actually shared with the 24-bit digital input
port) for interfacing to a TV decoder.
Each resolution from the VGA controller has a refresh rate, horizontal sync frequency, and pixel clock frequency
associated with it. The VESA document VESA Monitor Timing Specifications discusses this in depth.
ChromaCast 82C205 provides feedback to the 8051 micro-controller specifying the refresh rate and horizontal
sync frequency of the VGA input. The 8051 micro-controller must then update the capture clock divider word (for
the line-locked PLL), the capture CRTC registers, and the scaler ratio.
Sample VESA Table from VESA Monitor Timing Specifications
Resolution Refresh
Rate
1024x768 60 Hz 48.4 kHz 65 MHz VESA
Horizontal
Frequency
Pixel
Frequency
Standard
Type
Original
Document#
Standard
Date
VG901101A 8/9/91
Guidelines
Calculating the Horizontal Sync Frequency (F
The F
value can be determined by the micro-controller by reading the horizontal sync frequency status
HSYNC
)of the Incoming VGA
HSYNC
register. This register gives the number of reference clock cycles (14.318 MHz or 70 ns) between horizontal sync,
i.e. the period of hsync in units of reference clocks. Then the micro-controller can calculate F
by multiplying
HSYNC
the number of reference clocks * 70 ns and inverting the result:
F
= 1 / (70 ns * number of reference clocks per hsync interval).
HSYNC
Horizontal Sync Frequency Status
Horizontal Sync
Register 72h, 73h
Counter
Calculating the Refresh Rate or Vertical Sync Frequency (F
The F
value can be determined by the micro-controller by reading the resolution counter status register. This
VSYNC
) of the Incoming VGA
VSYNC
register gives the number of horizontal syncs between vertical syncs, i.e. the period of vsync in units of incoming
video lines. Then the micro-controller can calculate F
F
, by the number of horizontal syncs in the vertical interval:
HSYNC
F
VSYNC
= F
/ Resolution counter register value
HSYNC
by dividing the frequency of the horizontal sync,
VSYNC
Vertical Sync Frequency Status
Vertical Sync
Register 70h, 71h
Counter
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Determining the Resolution of the Incoming VGA
The resolution of the VGA can be determined by reading the resolution counter status register. This register gives
the number of horizontal syncs between vertical syncs, i.e. the period of vsync in units of incoming video lines.
Then the micro-controller can map this count to the most likely resolution by referencing VESA timing
specifications in the form of a table. For instance, a reading of 810 (decimal) would most likely correspond to 768
active video lines, hence a 1024x768 resolution. The programmer then sets up a quantizer that maps the
resolution counter’s value to the most likely resolution. Blanking time causes the count to be greater than the
number of active lines in a frame, but not significantly greater. Typical resolutions supported are 720x400,
640x480, 800x600, 1024x768, and 1280x1024, but this is a question of policy on how one wishes to define the
quantizer. The resolution counter is the same value used to calculate F
Vertical Sync Frequency Status
VSYNC.
Vertical Sync
Counter
Register 70h, 71h
Determining the frequency of the Pixel Clock used by the VGA
The pixel clock used by the VGA is not transmitted with the data, so it must be determined from the VESA
standards definition. Once the resolution, refresh rate, and horizontal sync frequency are determined, the pixel
clock from the VGA can be calculated by referencing a VESA table. Each resolution has several different refresh
rates, and each rate has a certain recommended pixel clock associated with it. If one wishes to support nonVESA endorsed modes, then that can be accommodated by changing the table mapping.
Determining the polarity of the horizontal and vertical incoming syncs
The 82C205 automatically detects the polarity of the incoming horizontal and vertical syncs from the VGA
controller. The polarities of these incoming syncs are independent of the polarities of the syncs required by the
panel. The incoming sync polarity information is available in a status register.
Capture Sync Polarity Status
Hsync Polarity Register 52h
Bit[2]
Vsync Polarity Register 52h
Bit[3]
Capture CRTC Programming
The Capture CRTC programming is independent of the Display CRTC programming (except in the case of
memory bypass mode where frame rate conversion is not performed). Capture CRTC timing information can be
obtained from reading the above mentioned status registers in the 82C205 and correlating this information with a
VESA Monitor Timing table. The Appendix includes common Capture CRTC settings for certain VGA modes.
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Programmer's Guide
ChromaCast 82C205
Horizontal Sync Width (in units of VCLK1)
This register defines the width of the active part of the sync (when data is not valid). This is for internal use, so it
can be set to any value greater that 1. As a rule of thumb, set this to 10.
Horizontal Sync Width
H Sync Width Register 40h, 41h
Horizontal Display Start (in units of pixel clock)
This is the time between the start of the horizontal sync and the start of data valid. It can be calculated by first
looking up the number of pixel clocks between the horizontal sync and the start of active data in the VESA
Computer Monitor Timing Standard. (These values will have to be stored in a table in the CPU program ROM.)
Horizontal Display Start
H Display Start Register 42h, 43h
Horizontal Display End (in units of pixel clock)
This is the time between the start of the horizontal sync and the end of data valid. This is calculated by adding the
horizontal size of the incoming VGA to the Horizontal Display Start value (Registers 42h, 43h).
Horizontal Display End
H Display End Register 44h, 45h
Horizontal Total (in units of pixel clock)
This is the period of Horizontal Sync. This can be determined by reading the Horizontal Frequency Count Register
(Registers 72h, 73h) and performing the following calculation:
Horizontal Total = (Horizontal Frequency Count * VCLK1f / 14.318 MHz) -1
Horizontal Total
H Total Register 46h, 47h
Vertical Sync Width (in units of video lines)
The width of the active part of the sync (when data is not valid). This is for internal use, so it can be set to any
value greater than 1. As a rule of thumb, set this the sync width to 1. The vertical sync width is specified by a start
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