OPTi 82C576/7/8 (Viper Xpress) BIOS programming guide

OPTi

®

Application Note (OPTi Confidential)

Product Name: Viper Xpress+ Chipset
Title: BIOS Programming Guide
Date: January 16, 1997

OPTi Inc.

888 Tasman Drive

Milpitas, CA 95035

[phone]

Fax: [phone]

Scope

This document outlines the rec omme nde d proce d ure for pro­gramming the inte rna l re gis ters of the Viper Xpress + Chips et .
It is intende d to be a reference for a BIOS develop er using
the Viper Xpress+ Chipset in a PC design. This document
classifie s the i nterna l regist ers of the Viper Xpress + Chips et
based on the subsystems that they control.

Figure 1 Boot Setting

Progra m chip se t re g isters for f a il sa fe operation

Program chipset registers for re q ui re d pin multiple xi ng

Memory detection and selection

Shadow BIOS ROM

Discussion

BIOS Settings

Given below is a chipset specific illustrative flow char t that a
BIOS needs to follow to program the chipset registers.

Tables 1 through 4 provide the register settings r equired of
the chipse t that the BIOS sh ould ensure in order for t he sys­tem to boot. These are fail safe boot values.

Size and enable cache

Program chipset registers for optimum reliable performance
(i.e., wait states for cache , DRAM PCI cycl es, etc.)

Enable performance enhancing features

Program IDE as a single- or multi-function device

PCI initialization
may be done

PCI interrupt assignment

Program chipset registers using values
defined in the board BIOS spec

OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and especially disclaims any implied warranties of
merchantability or fitness for any particular purpose. Further, OPTi Inc. reserves the right to rev i se the design and associated documentation and to make changes
from time to time in the content without obligation of OPTi Inc. to notify any person of such revisions or cha nges.

915-2000-067 Page 1 of 27
Revision: 1.0 OPTi C onfidential

Enable de ep bu ffe rs b efore giv ing control to bo ot O S

Control to BIOS

Application Note OPTi Confidential

Table 1 82C579 Fail Safe Boot Values

Loc. Value

PCIDV0

PCI Config Register Space

00h 45h
01h 10h
02h 69h
03h C5h
04h 07h
05h 00h
06h 80h
07h 02h
08h 10h
09h 00h
0Ah 00h

0Bh 06h
0Ch 00h
0Dh 00h
0Eh 00h
0Fh 00h

10h 00h

11h 00h

12h 00h

13h 00h

14h 00h

15h 00h

16h 00h

17h 00h

18h 00h

19h 00h
1Ah 00h
1Bh 00h
1Ch 00h
1Dh 00h
1Eh 00h
1Fh 00h

20h 00h

21h 00h

Loc. Value

22h 00h
23h 00h
24h 00h
25h 00h
26h 00h
27h 00h
28h 00h
29h 00h
2Ah 00h

2Bh 00h
2Ch 00h
2Dh 00h
2Eh 00h
2Fh 00h

30h 00h

31h 00h

32h 00h

33h 00h

34h 00h

35h 00h

36h 00h

37h 00h

38h 00h

39h 00h
3Ah 00h
3Bh 00h
3Ch 00h
3Dh 00h
3Eh 00h
3Fh 00h

40h 00h

41h 00h

42h 00h

43h 20h

(1)

44h

45h 00h

01h

Loc. Value

46h 00h
47h 00h
48h 00h
49h 00h
4Ah 00h

4Bh 00h
4Ch
4Dh 00h
4Eh 00h
4Fh 00h

SYSCFG

Sys Cntrl Register Space

00h 00h

01h 00h

02h 00

03h 00h

04h 00h

05h 00h

06h 00h

07h 00h

08h 00h

09h 00h
0Ah 00h
0Bh 00h
0Ch 00h
0Dh 00h
0Eh 00h
0Fh 00h

10h 00h

11h 00h

12h 00h

13h 80h

(1)

14h

15h 00h

16h 00h

17h 00h

40h

80h

(2)

Loc. Value

18h 00h
19h 88h
1Ah 00h
1Bh 00h
1Ch 00h
1Dh 00h
1Eh 08h
1Fh 02h
20h 8Ah
21h 01h
22h 00h
23h 00h
24h 00h
25h 00h
26h 00h
27h 06h
28h 00h
29h 00h
2Ah 01h
2Bh 00h
2Ch 00h
2Dh 00h
2Eh 00h
2Fh 00h

(1) SYSCFG 14h must be writ-

ten first followed by
PCIDV0 44h[1]. It is impor­tant that PCIDV0 44h-47h
is always a 32-bit write and
in a tight sequence code.

(2) If L2 c ac h e is bein g us ed in

the system, 4Eh[6] should
be set to 1.

OPTi

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OPTi Confidential Application Note

Table 2 82C578 Fail Safe Boot Values

Loc. Value

PCID V1

PCI Config Register Space

00h 45h
01h 10h
02h 68h
03h C5h
04h 07h
05h 00h
06h 80h
07h 02h
08h 10h

09h 00h
0Ah 01h
0Bh 06h
0Ch 00
0Dh 00
0Eh 00h
0Fh 00h
10h 00h
11h 00h
12h 00h
13h 00h
14h 00h
15h 00h
16h 00h
17h 00h
18h 00h
19h 00h
1Ah 00h
1Bh 00h
1Ch 00h
1Dh 00h
1Eh 00h
1Fh 00h
20h 00h
21h 00h
22h 00h

Loc. Value

23h 00h
24h 00h
25h 00h
26h 00h
27h 00h
28h 00h
29h 00h
2Ah 00h

2Bh 00h
2Ch 00h
2Dh 00h
2Eh 00h
2Fh 00h

30h 00h

31h 00h

32h 00h

33h 00h

34h 00h

35h 00h

36h 00h

37h 00h

38h 00h

39h 00h
3Ah 00h
3Bh 00h
3Ch 00h
3Dh 00h
3Eh 00h
3Fh 00h

40h 00h

41h 00h

42h 00h

43h 00h

44h 00h

45h 00h

46h 06h

47h 00h

Loc. Value

48h 00h
49h 00h
4Ah 00h

4Bh 00h
4Ch 00h
4Dh 00h
4Eh 00h
4Fh 00h

50h 00h

51h 00h

52h 00h

53h 00h

54h 00h

55h 02h

56h 00h

57h 00h

58h 00h

59h 00h
5Ah 00h
5Bh 00h
5Ch 00h
5Dh 00h
5Eh 00h
5Fh C0h

60h 00h

61h 00h

62h 00h

63h-FCh 00h

FDh xxh
FEh xxh
FFh xxh

SYSCFG

Pwr Mgmt Regis ters

E0h 00h
E1h 00h
E2h 00h
E3h 00h

Loc. Value

E4h 00h
E5h 00h
E6h 00h
E7h 00h
E8h 00h
E9h 00h
EAh 01h

EBh 01h
ECh 01h
EDh 00h
EEh 00h
EFh 00h

F0h 00h

F1h 00h

F2h 00h

F3h 00h

F4h 00h

F5h 00h

F6h 00h

F7h 00h

F8h 00h

F9h 00h
FAh 00h
FBh 00h
FCh 00h
FDh 00h
FEh 00h

FFh 10h

OPTi

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Application Note OPTi Confidential

Table 3 Register Boo t Values without Deep Buf fers

Loc. Value

SYSCFG

Sys Cntrl Register Space

00h 00h
01h DDh
02h 03h
03h EEh
04h 05h
05h 00h
06h 15h
07h xxh
08h 6Ah

09h 00h
0Ah 00h
0Bh 00h
0Ch 40h
0Dh 02h
0Eh 43h
0Fh 24h

10h 83h

11h 08h

12h 00h

13h 83h

14h 80h

15h A1h

16h A4h

17h 02h

18h 50h

19h 00h
1Ah 00h
1Bh 00h
1Ch 00h
1Dh 20h
1Eh CCh
1Fh 02h

20h 8Fh

21h 03h

Loc. Value

22h 00h
23h 06h
24h 00h
25h 00h
26h 00h
27h 00h
28h 00h

29h 00h
2Ah 01h
2Bh 00h
2Ch 00h
2Dh 00h
2Eh 40h
2Fh 00h

PCIDV0

PCI Config Register Space

80000000h C5691045h
80000004h 02800007h
80000008h 06000010h
8000000Ch 00000000h
80000010h 00000000h
80000014h 00000000h
80000018h 00000000h
8000001Ch 00000000h
80000020h 00000000h
80000024h 00000000h
80000028h 00000000h
8000002Ch 00000000h
80000030h 00000000h
80000034h 00000000h
80000038h 00000000h
8000003Ch 00000000h
80000040h 20000000h
80000044h 00000007h
80000048h 00000000h
8000004Ch 00000000h

Loc. Value

80000050h 00000000h
80000054h 00000000h
80000058h 00000000h

8000005Ch 00000000h

80000060h 00000000h
80000064h 00000000h
80000068h 00000000h

8000006Ch 00000000h

80000070h 00000000h
80000074h 00000000h
80000078h 00000000h

8000007Ch 00000000h

PCIDV1

PCI Config Register Space

80000800h C5681045h
80000804h 92800107h
80000808h 06010010h
8000080ch 00800000h
80000810h 00000000h
80000814h 00000000h
80000818h 00000000h

8000081Ch 00000000h

80000820h 00000000h
80000824h 00000000h
80000828h 00000000h

8000082Ch 00000000h

80000830h 00000000h
80000834h 00000000h
80000838h 00000000h

8000083Ch 00000000h

80000840h 20000000h
80000844h 40060001h
80000848h C0000000h

8000084Ch 40000000h

80000850h 0004C000h
80000854h 000000D0h

Loc. Value

80000858h 00000000h

8000085Ch 00000000h

80000860h 00000000h
80000864h 00000000h
80000868h 00000000h

8000086Ch 00000000h

80000870h 00000000h
80000874h 00000000h
80000878h 00000000h

8000087Ch 00000000h

OPTi

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OPTi Confidential Application Note

Table 4 Register Boot Values with Deep Buffers

Loc. Value

SYSCFG

Sys Cntrl Register Space

00h 00h
01h DDh
02h 03h
03h EEh
04h 05h
05h 00h
06h 15h
07h xxh
08h 6Ah
09h 00h
0Ah 00h
0Bh 00h
0Ch 40h
0Dh 02h
0Eh 43h
0Fh 24h
10h 83h
11h 08h
12h 00h
13h 83h
14h 80h
15h A1h
16h A4h
17h 02h
18h 50h
19h 00h
1Ah 00h
1Bh 00h
1Ch 00h
1Dh 20h
1Eh CCh
1Fh 02h

Loc. Value

20h 8Fh
21h 03h
22h 00h
23h 06h
24h 00h
25h 00h
26h 00h
27h 00h
28h 00h

29h 00h
2Ah 0Dh
2Bh 00h
2Ch 21h
2Dh 00h
2Eh 48h
2Fh 00h

PCIDV0

PCI Config Register Space

80000000h C5691045h
80000004h 02800007h
80000008h 06000010h
8000000Ch 00000000h
80000010h 00000000h
80000014h 00000000h
80000018h 00000000h
8000001Ch 00000000h
80000020h 00000000h
80000024h 00000000h
80000028h 00000000h
8000002Ch 00000000h
80000030h 00000000h
80000034h 00000000h
80000038h 00000000h
8000003Ch 00000000h

Loc. Value

80000040h 20000000h
80000044h 20003071h
80000048h 00000000h

8000004Ch 00000000h

80000050h 00000000h
80000054h 00000000h
80000058h 00000000h

8000005Ch 00000000h

80000060h 00000000h
80000064h 00000000h
80000068h 00000000h

8000006Ch 00000000h

80000070h 00000000h
80000074h 00000000h
80000078h 00000000h

8000007Ch 00000000h

PCIDV1

PCI Config Register Space

80000800h C5681045h
80000804h 92800107h
80000808h 06010010h

8000080Ch 00800000h

80000810h 00000000h
80000814h 00000000h
80000818h 00000000h

8000081Ch 00000000h

80000820h 00000000h
80000824h 00000000h
80000828h 00000000h

8000082Ch 00000000h

80000830h 00000000h
80000834h 00000000h
80000838h 00000000h

8000083Ch 00000000h

Loc. Value

80000840h 20000000h
80000844h 40060001h
80000848h C0000000h

8000084Ch 40000000h

80000850h 0004C000h
80000854h 000000D0h
80000858h 00000000h

8000085Ch 00000000h

80000860h 00000000h
80000864h 00000000h
80000868h 00000000h

8000086Ch 00000000h

80000870h 00000000h
80000874h 00000000h
80000878h 00000000h

8000087Ch 00000000h

OPTi

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Application Note OPTi Confidential

Pin Muxing in the Viper Xpress+ Chi pset

The Viper Xpress+ Chipset allows a great amount of flexibility
to enable the system designer to tailor the design optimally to
meet requi r eme nts . The BIO S pr o gra mme r shoul d obta in the
hardware muxing information f rom the board designer to pro­gram the pin mux ing re gister s. These values shoul d be pr o­grammed once and should not be changed during warm
resets.

Table 5 82C578 Group-Wi se Regi ster P rog ramm ab le Pins

Globally, the de s igner can program two bits in the 82C578 to
enable a group of pins t o take on dif ferent functions or can
individually program bits to assign the desired functionality on
a pin-by-pin basis. Table 5 shows the group-wise pin pro­gram ming opti on and Ta ble 6 shows t he register bits used in
pin programming (pin- and group-wise ).

PCID V 1 4 4h[1:0]

Pin No.

141 PIRQ2# PIRQ2# GPCS0## PIRQ2#
143 PIRQ3# PIRQ3# EPMI 2 # PIRQ3#
108 DACK0# DACK0# EDACK0 EDACK0
109 DACK1# DACK1# EDACK1 EDACK1
110 DACK2# DACK2# EDACKEN# EDACKEN#
111 DACK3# DACK3# EDACK2 EDACK2

Note: The group-wise pin functionality of these pins will always be overridden by the pin-wise programmability.

00 01 10 11

Table 6 82C578 Pin Functio nal ity Pro gram ming Register Bits

76543210

PCIDV1 41h Keyboard Control Register - Byte 1 Default = 00h

Keyboard

emulation:

0 = Enable -

Pin 12
functions
as A20M#
output

1 = Disable -

Pin 12
functions
as KBRST
input

PCIDV1 42h Interrupt Edge/Level Control Register - Byte 0 Default = 00h

Pin 122

functionality:

0 = DREQ6
1 = EPMI0#

OPTi

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OPTi Confidential Application Note

Table 6 82C578 Pin Functio nal ity Pro gram ming Register Bits (cont.)

76543210

PCIDV1 44h Pin Functionality Register 1 - Byte 0 Default = 00h

Pin 111 f un ctionality:
0X = C ontrolle d by bits [1 :0]
10 = DACK7#
11 = Reserved
If set to 10, the setting on bits [1:0]

will not affect the functionality that
this pin takes on.

(1) Pin 111 can take on the following functionalities - DACK3#, EDACK2, or DACK7# . DACK3# and EDACK2 are group-wise programmable,

and both are pin-wise programmable with DACK7# .

(2) Pin 109 can take on the following functionalities - DACK1#, EDACK1, or DACK6# . DACK1# and EDACK1 are group-wise programmable,

and both of them are pin-wise programmable with DACK6#.

PCIDV1 45h Pin Functionality Register 1 - Byte 1 Default = 00h

(1) This pin can take on any of the these functional ities - PIRQ3#, GPCS1#, or EPMI2#. PIRQ3# and GPCS1# functionalities are gro u p-wise

programmable, and those two functionalities are pin-wise programmable with EPMI2#.

(1)

Pin 109 f un ctionality:
0X = C ontrolle d by bits [1 :0]
10 = DACK6#
11 = Reserved
If set to 10, the setting on bits [1:0]

will not affect the functionality that
this pin takes on.

Pin 1 43

functionality:

If PCIDV1
51h[4] = 0:

0 = Controlled

by PCIDV1

44h[1:0]
1 = EPMI2#
(If this bit is set

and 51h[4] = 0,
pin 143 takes
on the EPMI2#
functional ity
regardless of
the setting of
44h[1:0])

(1)

This bit deter­mines the
group-wise
functionality of
the PIRQ2#+
GPCS0# . These
two functional­ities are group­wise program ­mable.

0 = Controlled

1 = Reserved

(2)

Pin 141

functionality:

by PCIDV1
44h[1:0]
and
PCIDV1
51h[3] = 0

Pin 108 functionality:
0X = Controlled by bits [1:0]
10 = DACK5#
11 = Reserved

Pin 140 functionality:

00 = PIRQ1#
01 = IRQ0
1X = Reser ved

DACK/PIRQ[3:2]#

gr oup- wise programmable

pin fun ctionalities:

00 = Explicit DACK[3:0]#,

PIRQ[3:2]#

01 = Explicit DACK[7:5,3,1,0 ]#,

GPCS0#, PIRQ[3:2 ]#

10 = Encoded EDACK[2 :0] ,

EDACKEN#

11 = Encoded EDACK[2 :0] ,

EDACKEN#, PIRQ[3:2]#

Pin-wise, these functions may be
overridden by GPCS[x]#,
EPMI[x]#, and DACK[7:5]# (for
DACK3#, DACK1#, and DACK0#).

Pin 139 functionality:

00 = PIRQ0#
01 = EPMI1#
1X = Reser ved

PCIDV1 48h Pin Functionality Register 2 - Byte 0 Default = 00h

Pin 120 functionality:

00 = DREQ3
01 = DREQ3/7
10 = DREQ7
11 = Reserved

PCIDV1 49h Pin Functionality Register 2 - Byte 1 Default = 00h

Pin 117 functionality:

00 = DREQ1
01 = DREQ1/6
10 = DREQ6
11 = Reserved

Pin 116 functionality:

00 = DREQ0
01 = DREQ0/5
10 = DREQ5
11 = Reserved

OPTi

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Application Note OPTi Confidential

Table 6 82C578 Pin Functio nal ity Pro gram ming Register Bits (cont.)

76543210

Pin 1 36

functionality:

0 = IRQ15
1 = Reserved

PCIDV1 4Fh Miscellaneous Control Register - Byte 1 Default = 00h

Pin 1 12

functionality:

0 = DACK5#

(also see
PCIDV1
44h[1:0])

1 = PPWRL #

+PPWRL2

Pin 134 functionality:

0X = IRQ12
10 = MPIRQ2#/3#
11 = Reserved

Pin 132

functionality:

0 = IRQ10
1 = MIRQ10/12

Pin 128

functionality:
0 = IRQ6
1 = MPIRQ0#/

1#

Also see
PCIDV1 53h[7].

Pin 126

functionality:

0 = IRQ4
1 = MIRQ4/6

Pin 123 functionality:

00 = DREQ7
01 = EPMI3#
1X = Reser ved

Pin 113

functionality:

0 = Controlled

by PCIDV1

44h[1:0]
1 = GPCS2#
If set to 1, the

PCIDV1
44h[1:0] setting
will not affect
the func t iona li ty
that this pin
takes on.

PCIDV1 51h Inte rrup t Trigge r Control Reg ist er - Byte 1 Default = 00h

Pin 1 04

functionality:

0 = 32KHz
1 = PREQ3#

Also see
PCIDV1 5Eh[6].

PCIDV1 53h Interrupt Multiplexing Control Register - Byte 1 Default = 00h

Pin

functionality:

0 = Pin #:
125 = IRQ3
127 = IRQ5
128 = IRQ6
129 = IRQ7
131 = IRQ9
133 = IRQ11

1 = Pin #:
125 = MIRQ3/5
127 = MIRQ7/9
128 = MIRQ11/

15
129 = EPMI1#
131 = EPMI2#
133 = GMIRQ

Pin 90

functionali ty:

0 = ZEROWS#
1 = PGNT3#

Pin 146

functionality:

0 = PREQ2#
1 = EPMI0#

Pin 1 10

functionality:

0 = DACK2#
1 = GPCS2#

Also see
PCIDV1
44h[1:0].

Pin 143

functionality:

0 = PIRQ3#
1 = GPCS1#

Also see
PCIDV1 45h[5].

Pin 141

functionality:

0 = PIRQ2#
1 = GPCS0#

PCIDV1 55h PCI Master Control Register - Byte 1 Default = 00h

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OPTi Confidential Application Note

Table 6 82C578 Pin Functio nal ity Pro gram ming Register Bits (cont.)

76543210

SERIRQ# mux-

ing on Pin 1:

0 = Disable
1 = Enable

(1) Also the se PCI DV1 re g ister bits must be set: 54h[ 4] = 1, 59h[3] = 0, and 5Fh[4] = 0.

PCIDV1 59h Pin Functionality Register 3 Default = 00h

(1) Also the se PCI DV1 re g ister bits must be set: 54h[ 4] = 1, 55h[4] = 0, and 5Fh[4] = 0.

(1)

EPMI0# mux-

ing on Pin 1:

0 = Disable
1 = Enable

Pin 106

functionality:

(1)

0 = RTCRD#
1 = PGNT3#

For SDACK2#
function on this
pin, see
PCIDV1 5Eh[6].

For PCI soft
reset genera­tio n t hrou gh
RTCRD#, see
PCIDV1 61h[7]
and 62h[7 ].

PCIDV1 5Eh Steerab le D RQ Control Reg iste r Default = 00h

SDRQ/

SDACK# func-

tion s on pins

105 and 107:

0 = Disable

1 = Enable
(1) Pin 10 5 fun ct io ns a s SDRQ1 a n d pin 107 functions as SDACK1#. Also re fe r to P CIDV1 60h[4].
(2) Pin 10 4 fun ct io ns a s SDRQ2 a n d pin 106 functions as SDACK2#. Also re fe r to P CIDV1 51h[7] and 59h[0].

PCIDV1 5Fh Steerable IRQ Control Register Default = 00h

Pin 52

functionality:

0 = Reserved
1 = MSGN2S

(1) Also the se PCI DV1 re g ister bits must be set: 54h[ 4] = 1, 55h[4] = 0, and 59h[3] = 0.

PCIDV1 60h USB Interrupt Control Register Default = 00h

(1)

SDRQ/

SDACK# func-

tions on pins

104 and 106:

0 = Disable
1 = Enable

Pin 154 functionality:

00 = Reserved
01 = Reserved
10 = MSGS2N
11 = USBGNT#

(2)

SERIRQ# mux-

ing on Pin 1:

0 = Disable
1 = Enable

(1)

OPTi

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Application Note OPTi Confidential

Table 6 82C578 Pin Functio nal ity Pro gram ming Register Bits (cont.)

76543210

Pins 105 and

107

functionality:

0 = RTCAS+

SDRQ1 on
pin 105 and
RTCWR#+
SDACK1#
on pin 107

1 = PREQ4#

on pin 105
and
PGNT4#
on pin 107

PCIDV1 61h PCI Reset Control Register Default = 00h

PCI soft reset

generation

throug h

RTCRD#:
0 =N o action
1 =G enerate a

100µs PCI
reset pulse
if PCIDV1
62h[7] = 0

USBGNT# thru

RTCWR#
(pin 107):

0 = Enabled

only if
PCIDV1
5Fh[7] = 1

1 = Disable (no

USBGNT#
functional­ity)

Buffered DMA LOCK# thru

SERIRQ#/RTCAS pins:
00 = No BFLOCK# thru either pin
01 = BFLOCK# thru SERIRQ# pin

(pin 1)

10 = BFLOCK# thru RTCAS pin

(pin 105)
11 = Reserved
These bit settings wi ll ov erride

PCIDV1 60h[4], 5Fh[4], 59h[3]
and 5Eh[7].

PCIDV1 62h Emulation Control Register Default = 00h

Pin

functionality:

0 = PCIRES#

enable

1 = PCIRES#

disable

OPTi

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OPTi Confidential Application Note

Table 7 82C579 Pin Functio nal ity Pro gram ming Register Bits

76543210

SYSCFG 26h ISA Control Register Default = 00h

USBGNT#:

0 = Through

me ssaging
pro tocol

1 = Through

pin 58

SYSCFG 2Dh Bank-wise EDO Timing Selection Registe r Default = 00h

DIRTYI pin

(pin 158) mux:

0 = MREF#

(MCACHE)

1 = NVMCS

SYSCFG 2Eh PCI Mast er Register Default = 00h

BFLOCK pin

(pi n 177)

control:

0 = Disable
1 = Enable

Pin 102

functionality:

0 = USBCLK
1 = REFRESH#

MSGN2S/

MSGS2N bus

ena bling:

0 = Disable
1 = Enable

DRAM Subsystem

After a p ower-on res et when the BIOS att empts t o configure
the DRAM subsystem, the registers that affect the DRAM
subsystem are lo cat ed in the 82C579. All the registers that
control the DRAM subsy ste m ar e acce ssed by the 22h, 24h
indexing scheme (to access the System Control Register
Space - SYSCFG).

The Viper Xpress+ Chipset supports up to six banks of
DRAM. Given below is a step-by-step procedure for initi aliz­ing the DRAM subsystem of the chipset. Tabl e 8 shows the
registers associated with configuration of the DRAM sub­system.

Step 1

Program SYSCFG 13h[7] = 1. This will enable the Viper
Xpress+ Chipset to fully decode the incoming addres s.

Step 2

The BIOS sh ould then progra m the size of eac h DRAM ban k
to be the maximum size before it determines the exact size of
memory in each bank.

SYSCFG Logical Bank Addressed

13h[2:0] Logical Bank 0
13h[6:4] Logical Bank 1
14h[2:0] Logical Bank 2
14h[6:4] Logical Bank 3
19h[2:0] Logical Bank 4
19h[6:4] Logical Bank 5

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Application Note OPTi Confidential

Notes:

A. SYSCFG 19h[7] and 19h[3] should be set to 1 be fore

starting DRAM sizing.

B. The maximum DRAM size setting in each register is

16Mx72 which corresponds to a 3-bit binary code of

E. Abov e all, the L1 and L2 caches must be disabled when

the DRAM subsystem is being initialized.

Step 3
Size Logical Banks 0 through 5 and program the appropriate
3-bit binary code in the appropriate registers.

“111”.

Table 8 DRAM Confi gur atio n Registers

76543210

SYSCFG 13h Memory Decode Control Register 1 Default = 00h

Memory decode

select:

This bit must
be set to 1 for
full decode
(maximum flexi­bility in choos­ing different
DRAM configu­rations)

SYSCFG 14h Memory Decode Control Register 2 Default = 00h

82C576 mode :

0 = Normal

mode

1 = Clocked

mode

(Must = 1 for
EDO timing)

(1) If SYSCFG 13h[3] is set.

Full decode for logical Bank 1 (RAS1#)

if SYSCFG 13h[7] is set:

000 = 0Kx72 100 = 2Mx72
001 = 256Kx72 101 = 4Mx72
010 = 512Kx72 110 = 8Mx72
011 = 1Mx72 111 = 16Mx72

Full decode for logical Bank 3 (RAS3#)

if SYSCFG 13h[7] is set:

000 = 0Kx72 100 = 2Mx72
001 = 256Kx72 101 = 4Mx72
010 = 512Kx72 110 = 8Mx72
011 = 1Mx72 111 = 16Mx72

SMRAM:

0 = Disable
1 = Enable

SMRAM

control:

Inactive
SMIACT#:

0 = Disable

SMRAM

1 = Enable

SMRAM

Active
SMIACT#:

0 = Enable

SMRAM for
both Code

and Dat a

1 = Enable

SMRAM for
Code only

(1)

Full deco d e for logica l Bank 0 (RAS0# )

if SYSCFG 13h[7] is set:

000 = 0Kx72 100 = 2Mx72
001 = 256Kx72 101 = 4Mx72
010 = 512Kx72 110 = 8Mx72
011 = 1Mx72 111 = 16Mx72

Full deco d e for logica l Bank 2 (RAS2# )

if SYSCFG 13h[7] is set:

000 = 0Kx72 100 = 2Mx72
001 = 256Kx72 101 = 4Mx72
010 = 512Kx72 110 = 8Mx72
011 = 1Mx72 111 = 16Mx72

(1)

(1)

SYSCFG 19h Memory Decode Control Register 3 Default = 00h

Reserved:

Must be written
to 1.

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Full decode for logical bank 5 (RAS5#)

if SYSCFG 13h[7] is set:

000 = 0Kx72 100 = 2Mx72
001 = 256Kx72 101 = 4Mx72
010 = 512Kx72 110 = 8Mx72
011 = 1Mx72 111 = 16Mx72

Reserved:

Must be written
to 1.

Full decode for logical bank 4 (RAS4#)

if SYSCFG 13h[7] is set:

000 = 0Kx72 100 = 2Mx72
001 = 256Kx72 101 = 4Mx72
010 = 512Kx72 110 = 8Mx72
011 = 1Mx72 111 = 16Mx72

Revision: 1.0

OPTi Confidential Application Note

EDO DRAM Auto Detectio n

This secti on of the do cument explai ns the mecha nism used
to automatically detect EDO DRAM SIMMs located on the
motherboard by the Viper Xpress+ Chipset.

Detection between WE# controlled EDO DRAMs and Fast
Page Mode DRAMs

Differentiating between thes e two type of DRAMs is a little bit
more complex because FP M ode DRAMs spe cified at 70ns,
could perform better than their rating and thus may even work
with tighter timing. A second factor that makes the detecti on
complex is the large capacitiv e load pres ented by t he DRAM
on the MD bus. This capacitive load manifests itself in the
form of large discharge times, thereby retaining the last
driven value on the bus for long periods of time.

A solution to this problem is to latch data into the chipset after
a significantly large ti me after the CAS has bee n pulled high.
Also an at tempt c ould be made to ge nerate a conflict on the
bus, thereby discharging the bus and then attempting to read
back the data prese nt on the MD bus.

When SYSCFG 1Fh[6] (in the 82C579) is set to “1” it puts the
Viper Xpress+ Chipset in the Mode of EDO DRAM de tection.
This will cause a quad-word to be read in 4µs . When bit 6 is
set, setting bit 7 to a “1” will cause a conflict to be gene rated
at about 2µs, if necessary.

An algorithm is given below to use this feature and detect the
type of DRAM used on the board. Refer to

Size the first b ank

1. Set SYSCFG 1Fh[6] = 1.

2. Set SYSCFG 1Fh[7] = 1. This step ne eds to be done
only if the user desire s to create a conflict on the bus.

3. Write a known pattern to a pre-determined location in
DRAM.

4. Write a second different pattern to a second pre-deter­mined location in the DRAM.

5. Read back data from the first pre-determined location in
DRAM.

6. Read back data from sec ond pre-determined location.

7. If data read back is the same as the data written to the
first pre-determined location, then the DRAM SIMMs are
WE# EDO SIMMs , othe rwis e they are Fas t Page Mode
DRAM SIMMs.

8. Set SYSCFG 1Ch[2] = 1 if Bank 0 = EDO
Set SYSCFG 1Ch[2] = 0 if Bank 0 = FP DRAM

...........

...........

...........

Set SYSCFG 1Ch[7] = 1 if Bank 5 = EDO
Set SYSCFG 1Ch[7] = 0 if Bank 5 = FP DRAM

9. Repeat for all banks.

Note: While EDO auto detection is in progress, hidden

refresh should be disabled.

Table 9 Register Bi ts Ass oci ated with E DO DRA M Auto Detectio n

76543210

SYSCFG 1Ch EDO DRAM Control Register Default = 00h

EDO DRAM usage:

Each bit is set to a 1 if the user is using EDO DRAMs in each of the available six banks. Bit 2 corresponds
to B an k 0 an d bi t 7 corres ponds to B an k 5, yielding a t otal of si x bank s t hat the user c an populate.

0 = Standard page mode DRAM
1 = EDO DRAM

SYSCFG 1Fh EDO Timing Control Register Default = 00h

0 = Normal
1 = Generate

conflict dur­ing EDO
detection
(bit 6 set) if
necessary

0 = Normal

(f ast page
mode)

1 = Detect EDO

OPTi

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Application Note OPTi Confidential

Shadowing the ROM Area

The BIO S needs to shadow the F0000 area so that the BIOS
code can execute out of local memory. Given below is an
algorithm to achieve this and shows the 82C578 and 82C579
associat ed register b its.

1. The BIOS should set PCIDV1 4Bh[7:6] = 00. This
enables generation of the ROMCS# by the 82C578
whenever the address is i n the F0000 segment.

2. The BIOS should then set SYSCFG 06h[3:2] = 10. This
causes all reads to the F0000 segment to go across the
PCI bus while all writes will be performed on the DRAM.

Table 10 Register Bits Associ ated wi th ROM Shado wi ng

76543210

PCIDV1 4Bh ROMCS# Range Control Register - Byte 1 Default = 00h

ROMCS# for
FFFF8000h-

FFFFFFFFh

segment:

0 = Enable
1 = Disable

ROMCS# for

FFFF0000h-

FFFF7FFFh

segment:

0 = Enable
1 = Disable

ROMCS# for
FFFE8000h­FFFEFFFFh

segment:

0 = Disable
1 = Enable

ROMCS# for
FFFE0000h-

FFFE7FFFh

segment:

0 = Disable
1 = Enable

4. The BIOS should then copy the contents of the ROM in
the F0000 segment to DRAM.

5. The BIOS should set PCIDV1 4Bh[7:6] = 11. This dis­ables generation of the ROMCS# by the 82C578 when­ever the address is in the F0000 segment.

6. The BIOS should then set register SYSCFG 06h[3:2] =

11. This causes all reads and writes to be performed on
the DRAM.

ROMCS# for
FFFD8000h­FFFDFFFFh

segment:

0 = Disable
1 = Enable

ROMCS# for
FFFD0000h-

FFFD7FFFh

segment:

0 = Disable
1 = Enable

ROMCS# for
FFFC8000h­FFFCFFFFh

segment:

0 = Disable
1 = Enable

ROMCS# for
FFFC0000h-

FFFC7FFFh

segment:

0 = Disable
1 = Enable

SYSCFG 06h Shadow RAM Control Register 3 Default = 00h

DRAM hole

in system

memory f rom

80000h-

9FFFFh:

0 = N o hole in

memory

1 = Enable hole

in memory

(1) This setting gives the user the option to have some other device in the address range 80000h-9FFFFh instead of system memory. When

bit 7 is set, the 82C579 will not start the syste m DRAM con tro ller for ac cesse s to this particular address range .

Wait state addi-

(1)

0 = Do not add

1 = Add a wait

tion for PCI

master

snooping:

a wait state
for the
cycle
access fin­ish to do the
snooping

state for the
cycle
access to
finish and
then do the
snooping

C0000h-

C7FFFh

cacheability:

0 = Not

Cacheable

1 = Cacheable

in L1 and L2
(L1 dis­abled b y
SYSCFG
08h[0])

F000 0h­FFFFFh

cacheability:

0 = Not

Cacheable

1 = Cacheable

in L 1 and L2
(L1 dis­abled by
SYSCFG
08h[0])

F0000h-FFFFFh

read/write control:
00 = Read/write PCI bus
01 = Read from DRAM / write to

PCI

10 = Read from PCI / write to

DRAM
11 = Read/write DRAM
If SYSCFG 04h[2] = 1, then the

E0000h-EF FFFh read/write con­trol should have the same setting
as this.

00 = Read/write PCI bus
01 = Read from DRAM / write to

10 = Read from PCI / write to

11 = Read/write DRAM

E0000h-EF FFF h

read/write control:

PCI

DRAM

OPTi

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OPTi Confidential Application Note

PCI Bus Master IDE Configurati on Requirem e nts

The system IDE controller configura tion is done by the BIOS
in two phases. The first phase takes place whe n the device s
on the PCI bus are initialize d. During this phase, the BIOS
assigns interrupts and sets the level of the interrupts. The
second phase of configuring the IDE contr oller takes place
when the features in the system are enabled. During this
phase, the IDE controller is configured for optimum perfor­mance based on the drives installed in the system. Thi s is
when the timing of the IDE controller is programmed into t he
internal registe r s of the co ntroll e r.

The following section include s the tasks that are done by the
BIOS during both of these phases. The BIOS is req uired to
separate the two phases based on the guidelines provi ded
above.

In order to optimiz e the PCI IDE Module for both DMA and
PIO operations, the following steps are expect ed to be ful­filled by the system BIOS:

1. Enable the PCI IDE Module: PCIDV1 4Fh[6] = 1.

2. Configure the PCI IDE Module through Mechanism #1 as
Bus #0, Device #1, and Function #1. Also set SYSCFG
FFh[4] = 1 (82C578).

3. Detect the PCI bus frequency and record it into IDE I/O
Address 1F5h[0]. For a synchronous PCI Viper Xpress+
system, the PCI bus frequency equals the system bus
frequency divided by two.

If a 25MHz PCI bus is detected, a 1 should be written
into the IDE I/O Address 1F5h[0] and 01 s hould be writ­ten into PCIDV1 47h[5:4] for the proper ISA clock divisor
as well.

If the Viper Xpres s + sy st em is configur e d for a n asyn ­chronous PCI cloc king scheme , the re is no need to per­form this checking since an externa l 33MHz (power -up
default) is feeding into the IDE module.

4. The default IDE ownership at PCIIDE 40h[4] should be
set to 1. This allows the multiplexed ISA/IDE bus always
park to the IDE Module.

5. The 32-by te re ad pre fet ch FIFO sh o uld be ena bled by
setting PCIIDE 40h[5] = 1.

6. Concurr en t ref resh and I D E cycles should be enabled by
setting PCIDV1 52h[0] = 1.

7. PCI IDE one wait state reads for primary and secondary
channels should be enabled at IDE I/O Address 1F3h[4].

8. Read prefetch for primary and secondary channels
should be enabled at IDE I/O Address 1F6h[6] and
176h[6] accordingly.

9. Enable master capability at PCIIDE 04h[2]. Once mas­tering is enable d, set PCID V1 54 h[7:4] = Fh.

10. Assign value for bus master IDE base addres s at
PCIIDE 20h-23h.

11. Depe n di n g o n the ca pabilitie s of the syst em’s hard
drives and the PCI bus frequency, setup the IDE timings
accordingly. The applicable SET_FEATURES com­mands (i.e., Flow Control Enable) should be issued to
the c orresponding IDE drives as well.

12. If no device is in the primary slave (Drive 1) location, set
the command pulse and recovery time (1F 0h/1 F1h,
Index-1) to correspond to PIO Mode 0.

13. If no device is in the secondary ma ste r (Drive 0) location
or slave (Drive 1) location, set the command pulse and
recovery time (170h/171h, Index-0 and 170h/171h,
Index-1) to correspond to PIO Mode 0.

Table 11 PCI Bus Master IDE Configurati on Associ ated Registe r Bits

76543210

PCIDV1 4Fh Miscellaneous Control Register - Byte 1 Default = 00h

IDE

functionality

support:

0 = Disable
1 = Enable

SYSCFG FFh General Purpos e Chip Selec t Control Reg ister Default = 00h

Reserved:

Must be written
to 1 .

OPTi

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Application Note OPTi Confidential

Table 11 PCI Bus Master IDE Configurati on Associ ated Registe r Bits

76543210

I/O Address 1F5h Strap Register Default = xxh

PCI CLK speed:

0 = 33MHz
1 = 25MHz

PCIDV1 47h Cycle Control Register 1 - Byte 1 Default = 00h

ATCLK frequency select:

00 = LC LK÷4
10 = LC LK÷2
01 = LC LK÷3
11 = LC LK

PCIIDE 40h IDE Initia liza tion Control Register Default = 00h

Enha nced

slave:

0 = 82C621A-

compatible
mode, uses
a 16-byte
FIFO in
PIO Mode

1 = Enhanced

mode, uses
a 32-byte
FIFO in
PIO Mode

Reserved:

Must be written
to 1 .

PCIDV1 52h Interrupt Multiplexing Control Register - Byte 0 Default = 00h

Concurrent

r ef res h and

IDE cycle:
0 = Disable

1 = Enable

ISA devices that
rely on accu­rate refresh
addres ses for
p roper opera­tion should dis­able this bit.

I/O Address 1F3h Control Register Default = xxh

Enable one

wait state read:

0 = 2 WS

minimum

1 = 1 WS

minimum for
data reads

OPTi

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OPTi Confidential Application Note

Table 11 PCI Bus Master IDE Configurati on Associ ated Registe r Bits

76543210

I/O Address 1F6h Miscel laneou s Registe r Default = xxh

Read prefetch:

0 = Disable
1 = Enable

I/O Address 176h Misc ellaneo us Register Default = xxh

Read prefetch:

0 = Disable
1 = Enable

PCIIDE 04h Com ma nd Register - Byte 0 Default = 4xh

IDE controller

becomes a PCI

master to gen-

erate PCI

accesses:
0 = Disable

1 = Enable

Note: This bit
must be explic­itly pro ­gra mmed.

PCIDV1 54h PCI Master Control Register - Byte 0 Default = 00h

PCI master

write X-1-1-1:

0 = Disable
1 = Enable

PCIIDE 20h-23h Bus Master IDE Base Address Register Default = 01000080h

This registe r is the l/O b ase address indica to r for the Bus Ma ster IDE Re gi st ers. The add ress bl ock has a size of 16 bytes .
Bits [3 1: 0] co rresp on d to: 20 h = [7:0 ] , 21 h = [ 15 :8] , 22h = [23:16], 23h = [31:2 4].

- Bits [3:0] are read-only and default to 0001.

- Bits [31:4] are writable.

I/O Addres s 1F0 h, Index-1 Read Cyc le Timin g Regi ster-B

The value programmed in this register plus one determines the DRD#
pulse width in LCLK s ( for a 16-bit read fro m the IDE Data Register).

(1) Read Cycle Timing Register-B shares the l/O address with Read Cycle Timing Register-A, indexed by 1F6h[0]. It controls the read cycle

timing of the IDE Data Register for the drive not selected by 1F3h[3:2] if 1F3h[7] = 1.

(2) See Tabl e 14 or Table 15 (of this do cum en t).

PCI master

read X-1-1-1:

0 = Disable
1 = Enable

Read pulse wid th:

PCI master/IDE

concur renc e:

0 = Disable
1 = Enable

(Also see
PCIIDE 42h[4]
and [2])

New AHOLD

protocol:
0 = Disable
1 = Enable

(use HREQ

to latch

AHOLD)

(1)

Read recovery time:

The value programmed in this register plus two determines the recov-

(2)

ery time between the end of DRD# and the next DA[2:0]/DCSx# being
presente d (a fter a 16-bit read fro m the IDE Data Regi ster) , me a su red

in LCLKs.

(2)

Default = xxh

OPTi

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Application Note OPTi Confidential

Table 11 PCI Bus Master IDE Configurati on Associ ated Registe r Bits

76543210

I/O Addres s 1F1h, Ind ex -1 Write Cycle Timin g Regi ste r-B

Write pulse width:
The val ue p ro gr amme d i n th is register plus one determin es t he DWR #
pulse width in LCLKs (for a 16-bit write from the IDE Data Register).

The value programmed in this register plus two determines the recov-

(2)

ery time between the end of DWR# and the next DA[2:0]/DCSx# being
presented (after a 16-bit write from the IDE Data Register), measured

in LCLKs.

(1) Write Cycle Timing Register-B shares the l/O address with Write Cycle Timing Register-A, indexed by 1F6h[0]. It controls the write cycle

timing of the IDE Data Register for the drive not selected by 1F3h[3:2] if 1F3h[7] = 1.

(2) See Table 14 or Table 15 (of this do cum en t).

(1)

Default = xxh

Write recovery time:

(2)

I/O Address 170h, Index-0 Read Cycle Timing Register-A

Read pulse wid th:
The value programmed in this register plus one determines the DRD#
pulse width in LCLK s (for a 16 -bit read fro m the IDE Data Register).

The value programmed in this register plus two determines the recov-

(2)

ery time between the end of DRD# and the next DA[2:0]/DCSx# being

(1)

Default = xxh

Read recovery time:

presente d (a fter a 16-bit read fro m the IDE Data Regi ster) , me a su red
in LCLKs.

(2)

(1) Read Cycle Timing Register-A shares the l/O address with Read Cycle Timing Register-B, indexed by 176h[0]. It controls the read cycle

timing of the IDE Data Regist er for the drive selected by 173h[3: 2] .

(2) See Table 14 or Table 15 (of this do cum en t).

I/O Address 171h, Index-0 Write Cycle Timing Register-A

Write pulse width:
The val ue p ro gr amme d i n th is register plus one determin es t he DWR #
pulse width in LCLKs (for a 16-bit write from the IDE Data Register).

The value programmed in this register plus two determines the recov-

(2)

ery time between the end of DWR# and the next DA[2:0]/DCSx# being

(1)

Default = xxh

Write recovery time:

presented (after a 16-bit write from the IDE Data Register), measured
in LCLKs.

(2)

(1) Write Cycle Timing Register-A shares the l/O address with Write Cycle Timing Register-B, indexed by 176h[0]. It controls the write cycle

timing of the IDE Data Regist er for the drive selected by 173h[3: 2] .

(2) See Table 14 or Table 15 (of this do cum en t).

I/O Address 170h, Index-1 Read Cycle Timing Register-B

Read pulse wid th:
The value programmed in this register plus one determines the DRD#
pulse width in LCLK s (for a 16 -bit read fro m the IDE Data Register).

The value programmed in this register plus two determines the recov-

(2)

ery time between the end of DRD# and the next DA[2:0]/DCSx# being

(1)

Default = xxh

Read recovery time:

presente d (a fter a 16-bit read fro m the IDE Data Regi ster) , me a su red
in LCLKs.

(2)

(1) Read Cycle Timing Register-B shares the l/O address with Read Cycle Timing Register-A, indexed by 176h[0]. It controls the read cycle

timing of the IDE Data Register for the drive not selecte d by 173h[ 3:2] if 173h[ 7] = 1.

(2) See Table 14 or Table 15 (of this do cum en t).

I/O Address 171h, Index-1 Write Cycle Timing Register-B

Write pulse width:
The val ue p ro gr amme d i n th is register plus one determin es t he DWR #
pulse width in LCLKs (for a 16-bit write from the IDE Data Register).

The value programmed in this register plus two determines the recov-

(2)

ery time between the end of DWR# and the next DA[2:0]/DCSx# being

(1)

Default = xxh

Write recovery time:

presented (after a 16-bit write from the IDE Data Register), measured
in LCLKs.

(2)

(1) Write Cycle Timing Register-B shares the l/O address with Write Cycle Timing Register-A, indexed by 176h[0]. It controls the write cycle

timing of the IDE Data Register for the drive not selecte d by 173h[ 3:2] if 173h[ 7] = 1.

(2) See Table 14 or Table 15 (of this do cum en t).

OPTi

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OPTi Confidential Application Note

Programming PCI Bus Master IDE Timing

The power-up default of the IDE module is PIO Mode 0 for all
four IDE devices. However, any of the IDE devices can be
programmed up to PI O Mode 3. In addition, there are four
sets of registers (two sets for each channel) that allow spe­cific timings to be progra mmed on a “per-devi ce” basis, see
Table 12. These re gi ster sets a re shared by the DMA and
PIO operations. W ith the IDENTIFY_DRI VE command infor­mation, the BIOS can opt imize the IDE timing for e ach drive
individually by programming these registers.

Any combination of hard drives or ATAPI devices may be
connected to the two channels of the I DE module in a four­drive configuration. For each channel, both sets of registers
and the power-up default can be used to control any devices
in the chan nel. See Table 13 for deta ils.

Table 14 and Table 15 show the timing and recommended
register settings for various IDE modes defined in the
Enhanced IDE Specifications. They include PIO transfer, Sin­gle-Word DMA transfer, and Multi-Word DMA transfer
modes. The actual cycl e time equals the sum of actua l com­mand active time and actual command inactive (command
recovery and address setup) time. These three timing
requirements shall be met. In some cases, the minimum
cycle time requir ement is gre ater than the sum of the com­mand pulse and command recove ry time. This means either
the command active (command pulse) time, or command
inactive (command recove ry a nd a ddre s s se tup) time can be
lengthene d to ensure that the minim um cy cl e time s are met.

Figure 2 is a flow chart that describes how to program the pri­mary channel of the MIDE interface. For the secondary chan­nel, a similar procedure can be done by changing all the
indexes from 1Fxh to 17xh.

Table 12 Registers for Program mi ng IDE Timin g

Name Address

Timing Registers-A for Primary Channel 1F0h/1F1h - Index-0 1F3h, 1F5h, a nd 1F6h are shared by both
Timing Registers-B for Primary Channel 1F0h/1F1h - Index-1
Timing Registers-A for Secondary Channel 170h/171h - Index-0 173h, 175h, an d 176h are shared by both
Timing Registers-B for Secondary Channel 170h/171h - Index-1

indexes

indexes

Table 13 REGTIMx Programming Options

REGTIM0

1F3h[2]/173h[2]

(1)

1

011Index-1Index-0
001Index-1Index-1
100Index-0

010
000
11XIndex-0Index-0

(1) Recomm ended configurati on
(2) Refer to PCI IDE 40h[1:0]

REGTIM1

1F3h[3]/173h[3]

01Index-0Index-1

REGTIM2

1F3h[7]/173h[7]

Master/Drive 0
Controlled by:

(2)

Defaul t

(2)

Defaul t

Slave/Drive 1

Controlled by:

(2)

Defaul t

Index-0

(2)

Defaul t

OPTi

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Application Note OPTi Confidential

Table 14 16-Bit Timing Parameters with 33/30 MHz PC I Bus

IDE Transfer Modes

Multi-Word DMA

Parame ter:
Register Bits Dimension

Address Set up:

1F6h/176h[5:4]

R/W Command Pulse:

1F0h/170h/1F1h/
171h[7:4], Index-0/1

R/W Recovery Time:

1F0h/170h/1F1h/
171h[3:0], Index-0/1

Enhanced Mode:

PCIIDE 43h [7:6],
[5:4], [3:2], or [1:0]

DRDY:

1F6h/176h[3:1]

Cycle Time Timing in LCLKs 20138654175432168

N/S = Not Specified, N/A = Not Applicable
(1) The actual tim in g (in LCL Ks) that will be generated by the IDE controller if the recommended bit values in hex are programmed.
(2) The timing (in ns) as specified in the Enhanced IDE Specification.
N/S = Not Specified, N/A = Not Applicable

Bit values in hex 211100000000
Timing in LCLKs

Enhanced IDE
Spec in n s

Bit values in hex 543222722F84
Timing in LCLKs

Enhanced IDE
Spec in n s

Bit values in hex 940000600D40
Timing in LCLKs

Enhanced IDE
Spec in n s

Bit values in hex 000122012000

Bit values in hex 000000000000
Timing in LCLKs

Enhanced IDE
Spec in n s

(2)

(2)

(2)

(2)

012345 0 1 2 0 1 2

(1)

322211111111

70 50 30 30 25 N/S N/A N/A N/A N/A N/A N/A

(1)

6543338331695

165 125 100 80 70 N /S 215 80 70 480 240 120

(1)

11621008101562

N/S N/S N/S 70 25 N/S 215 50 25 NS NS NS

(1)

222222222222

600 383 240 180 120 N/S 480 150 120 960 480 240

PIO Modes

Modes

Single-Word DMA

Modes

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Table 15 16-Bit Timing Paramete rs with 25MHz PCI Bus

IDE Transfer Modes

Multi-Word DMA

Parame ter:
Register Bits Dimension

Address Set up:

1F6h/176h[5:4]

R/W Command Pulse:

1F0h/170h/1F1h/
171h[7:4], Index-0/1

R/W Recovery Time:

1F0h/170h/1F1h/
171h[3:0], Index-0/1

Enhanced Mode:

PCIIDE 43h [7:6],
[5:4], [3:2], or [1:0]

DRDY:

1F6h/176h[3:1]

Cycle Time Timing in LCLKs 15106543134324126

(1) The actual tim in g (in LC LKs) that will be generated by the MIDE Module if the recommended bit values in hex are programmed.
(2) The timing (in ns) as specified in the Enhanced IDE Specification.

Bit values in hex 110000000000
Timing in LCLKs

Enhanced IDE
Spec in ns

Bit values in hex 432211521D63
Timing in LCLKs

Enhanced IDE
Spec in ns

Bit values in hex 620000400820
Timing in LCLKs

Enhanced IDE
Spec in ns

Bit values in hex 000122012001

Bit values in hex 000000000000
Timing in LCLKs

Enhanced IDE
Spec in ns

(2)

(2)

(2)

(2)

012345 0 1 2 0 1 2

(1)

221111111111

70 50 30 30 25 N/S N/A N/A N/A N/A N/A N/A

(1)

5433226321374

165 125 100 80 70 N/S 215 80 70 480 240 120

(1)

8421006101041

N/S N/S N/S 70 25 N/S 215 50 25 NS NS NS

(1)

222222222222

600 383 240 180 120 N/S 480 150 120 960 480 240

PIO Modes

Modes

Single-Word DMA

Modes

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Application Note OPTi Confidential

Table 16 IDE Interrupt Routing Char t

82C578 PCI Configuration Register Setting Interrupt Controller

PCI Bu s

Functions

Intrf,

Dev = 01h

Func = 0

IDE Module,

Dev = 01h

Func = 1 82C578 Interrupt Input IDE Interrupts Output

IDE Modes 4Fh[6] 04h[0] 40h[3 ] 40h[2 ] 09 h[3:0] Pin 135

Primary Secondary

Disable

(2)

Legacy

Native Disable 1 1 1 1 xx11 DINT0 ISA IRQ15 PIRQ3#

Legacy

Native

Legacy

Native Native 1 1 0 1 1111 DINT0 DINT1

1. The ISA IRQ14 (ISA IRQ15) will not be availab le to the ISA bus if the on-board prima ry (seco nda ry) IDE is enabled.

2. The 8259 IRQ14 (8259 IRQ15) will not be availa ble for PIRQ[3:0 ]# if the on-boa rd primary (seco nd ary) IDE is enabled .

3. In Native mode, IDE interrupts are shared with PIRQ3# from the PCI bus. It is routed in the same way as PIRQ3# to the interrupt controller
and is controlled by PCIDV1 40h[11:9], 42h[7:1], and 50h[7:6] of the 82C578 (Device #01h, Function #0). Using this mode requires that the
IDE device’s Interrupt Service Routine support interrupt sharing.

Disable

(2)

Native 1 1 0 1 1110 DINT0 DINT1 8259 IRQ14

Legacy

(2)

Legacy

IDE Module

(2)

(2)

Enable

0 PCI Config. Registe r Spa ce ca nnot be acces se d
1 0 x x xxxx
1110xxxx
1111xx10

1 1 0 1 1011 DINT0 DINT1
1100xxxx
11011010

IDE I/O

Enable

2nd IDE

Disable

Native

Mode

Enable

Native/

Legacy

Mode

(1)

IRQ14 or

DINT0

ISA IRQ14 ISA IRQ15 N/A N/A

DINT0 ISA IRQ15 8259 IRQ14 N/A

DINT0 DINT1 8259 IRQ14 8259 IRQ15

Pin 136

IRQ15 or

DINT1

(1)

Primary Secondary

8259 or

PCI INCT

(3)

(3)

PIRQ3#

(3)

PIRQ3#

8259 or

PCI INCT

N/A

(3)

PIRQ3#

8259 IRQ15

(3)

PIRQ3#

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Figure 2 IDE Interface Primary Channel Programming Flow Chart

Enter the IDE I/O Regi sters P rogra mmin g Mode:

Two consecutive 16-bit I/O reads from 1F1h (any other
I/O cyc le between these two reads will disable access
to the IDE registers) followed by an 8-bit I/O write to
1F2h wi th a value of 03h.

Set the value s in the Timing Registe rs-A (Index-0):

1) Write 0 to 1F6h[0] to point to Timing Registers-A.

2) Follow Table 14 or Table 15 to set proper values in
registers 1F0 h an d 1F1h for read/writ e pul se wi dth
and recovery times and PCIIDE 43h[1:0] for enhanced
timing.

Set the value s in the Timing Registe rs-B (Index-1):

1) Write 1 to 1F6[0] to point to Timing Registers-B.

2) Follow Table 14 or Table 15 and set proper values in
registers 1F0 h an d 1F1h for read/writ e pul se wi dth
and recovery times and PCIIDE 43h[3:2] for enhanced
timing.

Program the Address Setup Time and DRDY Delay Time:

1) Follow Ta ble 14 or Table 15, to set pro p e r valu es into
registers 1F6h[5:4]. Reset 1F6h[3:1] to 0.

2) The above values affect hard drives both in Timing Regis­ters-A and Timing Registers-B. If they are not the same
mode, program the slower timings for the address setup
time.

Enable Register-ba se d Timing to Override Powe r-up
Default Values:

Follow the REGTIMx Programming Options (Table 13) to set
proper v a lue s in the registe r s 1F 3h [7,3,2]. Th i s should be
done after read/write pulse and recovery, address setup,
and DRDY delay have been set.

Exit the IDE I/O Registe rs Progra mmin g Mode:

An 8-bit I/O write to 1F2h with a value of 83h.

Programming and Drive Placement Tips:

1. Ensure that IDE I/O Address 1F6h[0] (176h[0] in the
Secondary channel) is set to 0 whenever accessing Tim­ing Registers-A. It is a common mistake that after
accessing Timing Registers-B, this bit is not reset to 0 by
the BIOS. An error hap pens after a soft res et (thos e bits
will not be reset during a soft reset). The BIOS wants to

3. If no IDE hard drives are in the primary slave, secondary
master location or slave location, set only the command
pulse and recovery time (1F0h/1F1h, Index-1, 170h/
171h, Index-0 and 170h/171h, Index-1) to correspond to
PIO Mode 0. This is to e nsure proper timing for an
ATAPI CD-ROM that may be in any of these locations.

reload the timing sets to both T iming Registers-A and -B.
It would actually write to Timing Registers-B twice.

2. The address setup an d recovery time are shar ed by the
two IDE devices on the same channel at 1F6h[5:1]. If
these two devices are not in the same mode, slower
address setup and recovery time should be programmed
to ensure proper timings on the slower drive. Under this
assumption, two drives should be placed on the separate
channels in a two-drive system. In a multi pl e-drive sys­tem, place slower drives on one channel and faster
drives on the other channel.

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Application Note OPTi Confidential

System Configuration

This section of the document will discuss configura tion of the
I/Os in the Viper Xpress+ Chipset.

Cache Sizing Programming Guide

The followi ng ta s ks ne ed t o be completed in or der to si ze the
cache subsyst em.

1. Performing cache tag test

2. Single bank cache SRAM devices detection

Figure 3 Viper Xpress+ Chipset Cache Sizing Program

Turn on L1 as write-through cache; o/p ‘AA’ to Port 80

Write reg ister 07h w/10h, ena bl e wr ite tag test mo de

Populate tags with value 10h by flushing L2 cache

If a usable cache SRAM device is detected, then the cache
needs to be sized. T he foll owi ng ar e va lid cach e sizes for the
Viper Xpress+ Chipset.

• 256KB total cache size

• 512KB total cache size

• 1MB total cache size

• 2MB tota l cache size
The following is a flow diagram of the Vipe r Xpress+ Chi pset

cache sizing progra m.

Read (L1) miss 8 dwords @ A000h and compare

L2 is double bank if all dw match; else single bank

Switch to read tag test mode

Continuously fill 2K lines and check register 07h contents

Loop till end if no mismatch occurs, oth erwi se no tag

Turn off L2 and free ze tag cont en t s; o/p ‘BB’ to Port 80

Set mi s c regs co ntents; turn on L2 as 64 K writeba ck

Write hit location A000h with Pattern A

Read (L1) miss location A000h; no cache if mismatch

Write hit 8 dwords @ A000h each with its location

O/p 80/81/82/83/84 to Port 80; continue if L2 exist

Size L2 as 256KB; o/p 04 if size = 256K, else mo ve on

Size L2 as 512KB; o/p 08 if size = 512K, else mo ve on

Size L2 a s 1MB; o/p 10 if size = 1M, else move on

Size L2 as 2MB; o/p 20 if size = 2M, else no cache

With DL = size (reg 02 ‘OR’) value, program term inat es

Notes: 1. The L2 cac he is placed in the writeback mode by

setting (82C579) SYSCFG 02h[5:4] = 11.

2. The L1 cache’s write-back control bit is set by
programming (82C579) SYSCFG 08h[1] = 1.
Both of these settings should be done by the
BIOS when it e nables the features in the system.

3. o/p = output

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PCI Interrupt Routing

The registers that affect the assignment of interrupts in the
Viper Xpress+ chipset are located in the 82C578. The regis­ters that affect the assignment are PCIDV1 40h, 41h and
50h.

Table 17 Interrupt Assignme nt / Contr ol

PCI
Interrupt PCIDV1

PIRQ0# 40h[2:0] 000 = IRQx
PIRQ1# 40h[5:3]
PIRQ2# 40h[7:6], 41h[0 ]
PIRQ3# 41h[3:1]

Note: The bits provided above c ontrol the interrupt routing

only when the bits are programmed to a value differ­ent from 000. In the event that the bit s are pro­grammed to 000 for a given PIRQx#, then the routing
of that interrupt is controlled by PCIDV1 50h. That
mappin g sche me is provided in Tabl e 18.

Bit Values/Triggered

IRQ

001 = IRQ5
010 = IRQ9
011 = IRQ10
100 = IRQ11
101 = IRQ12
110 = IRQ14
111 = IRQ15

Table 18 Enhanced Interrup t Assig nmen t / Control

Interrupt Sensi ng

Whenever PCI interrupts are routed to ISA interrupts, the
interrupt needs to become level-triggered instead of edge­triggered. The only exception is the IDE interrupt (IRQ14).
Table 1 9 lists the r egiste r bits that a ffect the interru pt trigger
mechanism and the associated interrupt.

Table 19 Interrupt Level Assig nmen t

ISA Interrupt PCIDV1 Bit Value

IRQ3 51h[2] 0 = Edge-triggered
IRQ4 51h[1]
IRQ5 42h[1]
IRQ6 52h[7]
IRQ7 51h[0]
IRQ9 42h[2]
IRQ10 42h[3]
IRQ11 42h[4]
IRQ12 42h[5]
IRQ14 42h[6]
IRQ15 42h[7]

1 = Level-triggered

PCI
Interrupt PCIDV1 Bit Values/Triggered IRQ

PIRQ0# 50h[1:0] 00 = Disable
PIRQ1# 50 h[3 :2]
PIRQ2# 50 h[5 :4]
PIRQ3# 50 h[7 :6]

01 = IRQ3
10 = IRQ4
11 = IRQ7

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Enabling Features in the Viper Xpress + Silicon

All feature s listed in this secti on of the document should be
turned on by the BIOS whil e enabling the adva nced fea tures
in the sy stem. Where indicated, the BIOS needs to follow the
order specifi ed whi le turni ng on thes e feat ure s .

Note: Make sure writes t o re gisters PCIDV0 44h-47h are

always 32-bit writes. No memory access should
be allowed in between configuration writes.

• CPU address pipelining

- SYSCFG 08h[2] = 1

• PCI pre-s noop

- The BIOS should turn on SYSCFG 0Fh[7] first and then
turn on SYSCFG 16h[3]. This order should be main­tained. As lon g as this order is ma inta ine d no ot her
ordering with regard to the other features needs to be
followed.

• Pa ge mis s poste d write

- SYSCFG 11h[2] = 1

• Hidden refresh (82C568)

- PCIDV1 47h[6] = 1

• Progra mming wait state s during PCI ma ster trans fers

- Enhanced Mode - PCI master read:
PCIDV0 44h[1] = 1
PCIDV1 54h[6] = 1
= Controlled by SYSCFG 20h[1:0]

- SYSCFG 20h[1:0]

01 = X-3-3-3
10 = X-2-2-2
11 = X-1-1-1

- Enhanced Mode - PCI master write:
PCIDV0 44h[2] = 1
PCIDV1 54h[7] = 1
= Controlled SYSCFG 20h[3:2]

- SYSCFG 20h[3:2]

01 = X-3-3-3
10 = X-2-2-2
11 = X-1-1-1

Note: It is highly recommended to program X-1- 1-1

transfers for PCI masters

• CPU-to-DRAM FIFO

- Enable (Sequence must be fo llowed)

- SYSCFG 01h[2] = 1 (CAS width for DRAM write - 2
CLK)

- SYSCFG 02h[0] = 1 (CAS precharge - 1 CLK)

- SYSCFG 02h[1] = 1 (DRAM posted write s if already
enabled this bit will be set to 1)

- SYSCFG 2Ch[1:0] = 11 (Generate BOFF when FIFO
full)

- PCI DV0 44h[4] = 1

- PCI DV0 45h[1] = 1

- Disable - Follow reverse sequence.
Note: If DRAM post write already enabled there is no
need to disable it when turning off this feature. Similarly
for CAS width and precharge.

• PCI -to-DRAM FIFO

- Enable/Disable (Sequence must be followed)

- SYSCFG 20h[3:0] = 0Fh (PCI X-1-1-1 enable)

- PCI DV0 47h[5] = 1

- PCIDV0 44h[2:1] = 00

- PCIDV0 44h[6:5] =

00 - Disable read/write FIFO
01 - Disable read/Enable write FIFO
10 - Enable read/Disable write FIFO
11 - Enable read /write F IF O

- SYSCFG 2Ah[3:2] = 11

(bit 2 enabl es rea ds bur st )
(bit 3 enabl es writ e burst)

• CPU-to-PCI FIFO

- Enable (Sequence must be followed)

- SYSCFG 15h[5:4] = 01 (i f PCI posted writes are

already enabled, this bit will be set to either 01, 10 or

11)

- PCI DV0 44h[7] = 1

- SYSCFG 2Eh[3] = 1

- Disable - Follow reverse sequence.
Note: If PCI post write already enabled do not disable it
when turning off this feature.

• EDO 5-2-2- 2 timing

- Enable (Sequence must be followed)

- Turn on EDO functionality

- SYSCFG 1Dh[4] = 1 (Turns on 7-2-2- 2)

- SYSCFG 1Fh[4] = 1 (Turns on 6-2-2-2)

- SYSCFG 26h[3] = 1

- SYSCFG 2Dh[6] = 1

- SYSCFG 2Dh[5:0] = Set for EDO bank detected

(5-2-2-2)

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• Self Refres h

- Enable

- SYSCFG 27h[2:0] =
100 - i f ext clock is 66MHz
101 - i f ext clock is 60MHz
110 - i f ext clock is 50MHz
111 - i f ext clock is 40MHz

- PCIDV1 54h[0] = 1

- Disable

- PCIDV1 54h[0] = 0

- SYSCFG 27h[2:0] = 000

Note: It is recommended to turn on self refr esh and turn off

hidden refresh.

• CPU to Sync SRAM 3-1-1-1-1 pipelining

- Enable (Sequence must be followed)

- SYSCFG 10h[5] = 1

- SYSCFG 04h[3] = 1

• Fast NA (3 CLK single cycle writes)

- Enable (Sequence must be followed)

- Ensure SYSCFG 0Ch[6] =1

- No L2 cache:
SYSCFG 0Eh[2] = 1

- L2 cache en abled
SYSCFG 27h[4] = 1
SYSCFG 0Fh[4] = 1
PCIDV1 55h[1] = 1
PCIDV0 42h[0] = 1
SYSCFG 0Eh[2] = 1

• Buffer DMA

- ISA Retry
SYSCFG 55h[1] = 1
SYSCFG 1Eh[3] = 1
SYSCFG 26h[6] = 1
SYSCFG 22h[4] = 1

• SDRAM

- Read arou nd
SYSCFG 2Ch[4] = 1
PCIDV0 44h[13:12] = 11

- SDRAM timing

- 9-1-1-1

SYSCFG 1Fh[4] = 0
SYSCFG 1Dh[4] = 1
PCIDV0 54h[5:0] = 111111

- 7-1-1-1
SYSCFG 1Fh[4] = 1
SYSCFG 1Dh[4] = 1
PCIDV0 54h[5:0] = 000000

- SDRAM pipeline

- X-1-1-1/2-1-1-1
pipeline set up for ED O
SYSCFG 00h[6] = 1
SYSCFG29h[7] = 1

- X-1-1-1/5-1-1-1
pipeline setup for EDO

Note: For all SDRAM-based systems, the following bits

need to be set:
PCIDV0 48h[4] = 1,
PCIDV0 48h[3] = 0,
PCIDV0 4Eh[6] = 0
PCIDV0 4Eh[5] = 1
PCIDV0 55h[7] = 1
PCIDV0 55h[6] = 1

Deep Buffer Programmi ng

The followi n g sequ e nce shoul d be us ed when enabl ing dee p
buffers.

1. CPU-to-PCI

2. CPU-to-DRAM

3. PCI-to-DRAM
Also the enabl ing of deep buffers with res pect to the entire

BIOS, the followi ng seq uence is recomm ende d.

1. The three deep buffers can be enabled just before giving
control to boot block to st art the OS.

2. When deep buffers are enabled and Ctrl+Alt+Del key is
pressed (soft boot), the BIOS must disable all the thre e
deep buffers in the reverse order of enabling after giving
sufficient time (250 CPU clock time at least) to allow
flushing of buffered data from the buffers. A gain just
before giving control to boot block, they should be
enabled.

3. All the deep buffer enabling/disabling code must be a
tight sequence code without any DRAM or non-configu­ration PCI cycles in-between.

- 8-1-1-1
SYSCFG 1Fh[4] = 0
SYSCFG 1Dh[4] = 1
PCIDV0 54h[5:0] = 000000

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