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UC2 3842

ON Semiconductor UC2 3842, UC3843A, UC2842A, UC2843A Service Manual

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UC3842A, UC3843A, UC2842A, UC2843A
High Performance Current Mode Controllers
Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting, programmable output deadtime, and a latch for single pulse metering.
These devices are available in an 8–pin dual–in–line plastic package as well as the 14–pin plastic surface mount (SO–14). The SO–14 package has separate power and ground pins for the totem pole output stage.
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), ideally suited for off–line converters. The UCX843A is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
• Trimmed Oscillator Discharge Current for Precise Duty Cycle
Control
• Current Mode Operation to 500 kHz
• Automatic Feed Forward Compensation
• Latching PWM for Cycle–By–Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• Direct Interface with ON Semiconductor SENSEFET Products
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8
1
14
8
PIN CONNECTIONS
Compensation
Voltage Feedback
Current Sense
R
T/CT
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
R
T/CT
PDIP–8 N SUFFIX CASE 626
SO–14
D SUFFIX
CASE 751A
1
SO–8
D1 SUFFIX
(Top View)
(Top View)
CASE 751
8
V
ref
7
V
CC
6
Output
Gnd
14
V
ref
13
NC
12
V
CC
11
V
C
10
Output
9
Gnd
Power Ground
8
1
1
2
3
45
1
2
3
4
5
6
7
Semiconductor Components Industries, LLC, 2001
October, 2001 – Rev. 3
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 16 of this data sheet.
1 Publication Order Number:
UC3842A/D
UC3842A, UC3843A, UC2842A, UC2843A
V
7(12)
CC
V
R
Voltage
Feedback
Input
Output
Compensation
ref
8(14)
TCT
4(7)
2(3)
1(1)
R
R
Oscillator
+
-
Error
Amplifier
Pin numbers in parenthesis are for the D suffix SO-14 package.
V
Undervoltage
Lockout
Gnd 5(9)
5.0V
Reference
ref
Latching
PWM
Figure 1. Simplified Block Diagram
MAXIMUM RATINGS
Rating Symbol Value Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) VCC, V Total Power Supply and Zener Current (ICC + IZ) 30 mA Output Current, Source or Sink (Note 1) I Output Energy (Capacitive Load per Cycle) W 5.0 µJ Current Sense and Voltage Feedback Inputs V Error Amp Output Sink Current I Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package
Maximum Power Dissipation @ T Thermal Resistance, Junction–to–Air
N Suffix, Plastic Package
Maximum Power Dissipation @ T
Thermal Resistance, Junction–to–Air Operating Junction Temperature T Operating Ambient Temperature
UC3842A, UC3843A UC2842A, UC2843A
Storage Temperature Range T
1. Maximum Package power dissipation limits must be observed.
= 25°C
A
= 25°C
A
V
CC
Undervoltage
Lockout
V
7(11)
Output
6(10)
5(8)
3(5)
P
R
P
R
T
C
Power Ground
Current Sense Input
O
in
O
D
θ
JA
D
θ
JA J A
stg
C
– 0.3 to + 5.5 V
862 145
1.25 100
+ 150 °C
0 to + 70
– 25 to + 85
– 65 to + 150 °C
30 V
1.0 A
10 mA
mW
°C/W
W
°C/W
°C
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UC3842A, UC3843A, UC2842A, UC2843A
ELECTRICAL CHARACTERISTICS (V
= 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = T
CC
low
to T
[Note 3],
high
unless otherwise noted.)
UC284XA UC384XA
Characteristics Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (I
= 1.0 mA, TJ = 25°C) V
O
Line Regulation (VCC = 12 V to 25 V) Reg Load Regulation (IO = 1.0 mA to 20 mA) Reg Temperature Stability T Total Output Variation over Line, Load, Temperature V Output Noise Voltage (f = 10 Hz to 10 kHz,
= 25°C)
T
J
ref
line
load
S
ref
V
n
4.95 5.0 5.05 4.9 5.0 5.1 V – 2.0 20 – 2.0 20 mV – 3.0 25 – 3.0 25 mV – 0.2 – – 0.2 – mV/°C
4.9 – 5.1 4.82 – 5.18 V – 50 – – 50 – µV
Long Term Stability (TA = 125°C for 1000 Hours) S – 5.0 – – 5.0 – mV Output Short Circuit Current I
SC
– 30 – 85 – 180 – 30 – 85 – 180 mA
OSCILLATOR SECTION
osc/∆V
∆f
osc/∆T
I
dischg
f
osc
osc
47 46
52
–
60
57
47 46
52
–
60
57
– 0.2 1.0 – 0.2 1.0 % – 5.0 – – 5.0 – %
– 1.6 – – 1.6 – V
7.5
7.2
8.4 –
9.5
9.3
7.5
7.2
8.4 –
9.5
9.3
Frequency
= 25°C
T
J
= T
T
to T
A
low
high
Frequency Change with Voltage (VCC = 12 V to 25 V) ∆f Frequency Change with Temperature
T
= T
to T
A
low
high
Oscillator Voltage Swing (Peak–to–Peak) V Discharge Current (V
T
= 25°C
J
= T
T
to T
A
low
high
= 2.0 V)
osc
ERROR AMPLIFIER SECTION
Voltage Feedback Input (V Input Bias Current (VFB = 2.7 V) I Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) A
= 2.5 V) V
O
FB
IB
VOL
2.45 2.5 2.55 2.42 2.5 2.58 V – –0.1 –1.0 – –0.1 –2.0 µA
65 90 – 65 90 – dB Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 – 0.7 1.0 – MHz Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 – 60 70 – dB Output Current
Sink (V Source (V
= 1.1 V, VFB = 2.7 V)
O
= 5.0 V, VFB = 2.3 V)
O
I
Sink
I
Source
2.0
–0.512–1.0
– –
2.0
–0.512–1.0
– –
Output Voltage Swing
High State (R Low State (R
= 15 k to ground, VFB = 2.3 V)
L
= 15 k to V
L
, VFB = 2.7 V)
ref
V
OH
V
OL
5.0 –
0.8
6.2
1.1
–
5.0 –
0.8
6.2
–
1.1
2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. =0°C for UC3842A, UC3843A T
T
low
–25°C for UC2842A, UC2843A +85°C for UC2842A, UC2843A
= +70°C for UC3842A, UC3843A
high
kHz
mA
mA
V
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UC3842A, UC3843A, UC2842A, UC2843A
ELECTRICAL CHARACTERISTICS (V
= 15 V, [Note 4], RT = 10 k, CT = 3.3 nF, TA = T
CC
low
to T
[Note 5],
high
unless otherwise noted.)
UC284XA UC384XA
Characteristics Symbol Min Typ Max Min Typ Max Unit
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 6 & 7) Maximum Current Sense Input Threshold (Note 6) V Power Supply Rejection Ratio
= 12 to 25 V (Note 6)
V
CC
Input Bias Current I Propagation Delay (Current Sense Input to Output) t
A
V th
PSRR
IB
PLH(in/out)
2.85 3.0 3.15 2.85 3.0 3.15 V/V
0.9 1.0 1.1 0.9 1.0 1.1 V
– 70 – – 70 – – –2.0 –10 – –2.0 –10 µA – 150 300 – 150 300 ns
OUTPUT SECTION
Output Voltage
Low State (I
Low State (I
High State (I
High State (I
= 20 mA)
Sink
= 200 mA)
Sink
= 20 mA)
Sink
= 200 mA)
Sink
Output Voltage with UVLO Activated
V
CC
= 6.0 V, I
= 1.0 mA
Sink
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) t Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) t
V
OL
V
OH
V
OL(UVLO)
–
– 13 12
0.1
1.6
13.5
13.4
0.4
2.2
–
– – –
13 12
0.1
1.6
13.5
13.4
– 0.1 1.1 – 0.1 1.1
r f
– 50 150 – 50 150 ns – 50 150 – 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX842A UCX843A
Minimum Operating Voltage After Turn–On
UCX842A UCX843A
V
V
CC(min)
th
15
7.8
9.0
7.0
16
8.4
10
7.6
17
9.0
11
8.2
14.5
7.8
8.5
7.0
16
8.4
10
7.6
PWM SECTION
Duty Cycle
Maximum Minimum
DC
DC
max
min
94
–
–
96
– 0
94
–
–
96
TOTAL DEVICE
Power Supply Current (Note 4)
I
CC
Startup: (VCC = 6.5 V for UCX843A,
= 14 V for UCX842A) Operating
(V
CC
Power Supply Zener Voltage (ICC = 25 mA) V
Z
– –
0.5 12
1.0 17
– –
0.5 12
30 36 – 30 36 – V
4. Adjust VCC above the Startup threshold before setting to 15 V.
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. =0°C for UC3842A, UC3843A T
T
low
–25°C for UC2842A, UC2843A +85°C for UC2842A, UC2843A
= +70°C for UC3842A, UC3843A
high
6. This parameter is measured at the latch trip point with VFB = 0 V.
7. Comparator gain is defined as: A
∆V Output Compensation
V
∆V Current Sense Input
dB
V
0.4
2.2 – –
V
V
17.5
9.0
V
11.5
8.2
% – 0
mA
1.0 17
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UC3842A, UC3843A, UC2842A, UC2843A
80
50
Ω, TIMING RESISTOR (k )
20
8.0
5.0
VCC = 15 V
2.0
T
R
T
= 25°C
A
0.8 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
f
, OSCILLATOR FREQUENCY (Hz)
OSC
Figure 2. Timing Resistor versus
Oscillator Frequency
9.0
VCC = 15 V V
= 2.0 V
OSC
8.5
100
VCC = 15 V
50
T
= 25°C
A
20
10
5.0
2.0
% DT, PERCENT OUTPUT DEADTIME
1.0 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
, OSCILLATOR FREQUENCY (Hz)
f
OSC
Figure 3. Output Deadtime versus
Oscillator Frequency
100
VCC = 15 V CT = 3.3 nF
90
T
= 25°C
A
I
dischg
= 7.2 mA
80
8.0
, DISCHARGE CURRENT (mA)
7.5
dischg
I
7.0
-55 -25 0 25 50 75 100 125
, AMBIENT TEMPERATURE (°C)
T
A
Figure 4. Oscillator Discharge Current
versus Temperature
VCC = 15 V
2.55 V
2.5 V
AV = -1.0 T
= 25°C
A
, MAXIMUM OUTPUT DUTY CYCLE (%)
D
3.0 V
2.5 V
20 mV/DIV
70
60
50
max
40
I
dischg
= 9.5 mA
800 1.0 k 2.0 k 3.0 k 4.0 k 6.0 k 8.0 k
R
, TIMING RESISTOR (Ω)
T
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
VCC = 15 V AV = -1.0 T
= 25°C
A
200 mV/DIV
2.45 V
0.5 µs/DIV
Figure 6. Error Amp Small Signal
Transient Response
2.0 V
0.1 µs/DIV
Figure 7. Error Amp Large Signal
Transient Response
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UC3842A, UC3843A, UC2842A, UC2843A
)
100
80
Gain
60
40
20
, OPEN LOOP VOLTAGE GAIN (dB)
0
VOL
A
-20 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)
Figure 8. Error Amp Open Loop Gain and
Phase versus Frequency
0
-4.0
-8.0
VCC = 15 V VO = 2.0 V to 4.0 V RL = 100 K T
= 25°C
A
Phase
VCC = 15 V
0
30
60
90
120
150
180
10 M10
1.2
1.0
0.8
0.6
0.4
, EXCESS PHASE (DEGREES)
0.2
φ
, CURRENT SENSE INPUT THRESHOLD (V
th
0
V
110
90
VCC = 15 V
T
= 25°C
A
T
= 125°C
A
T
= -55°C
A
0
2.0 4.0 6.0 8.0 , ERROR AMP OUTPUT VOLTAGE (V)
V
O
Figure 9. Current Sense Input Threshold
versus Error Amp Output Voltage
VCC = 15 V R
≤ 0.1 Ω
L
-12
T
-16
-20
ref
V ∆ , REFERENCE VOLTAGE CHANGE (mV)
-24 0 20 40 60 80 100 120
= 125°C
A
T
= 25°C
A
I
, REFERENCE SOURCE CURRENT (mA)
ref
T
A
= 55°C
Figure 10. Reference Voltage Change
versus Source Current
VCC = 15 V IO = 1.0 mA to 20 mA T
= 25°C
A
70
, REFERENCE SHORT CIRCUIT CURRENT (mA)
50
SC
I
-55 -25 0 25 50 75 100 125
T
, AMBIENT TEMPERATURE (°C)
A
Figure 11. Reference Short Circuit Current
versus Temperature
VCC = 12 V to 25 V T
= 25°C
A
O
V ∆ , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
Figure 12. Reference Load Regulation
2.0 ms/DIV
O
V ∆ , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
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2.0 ms/DIV
Figure 13. Reference Line Regulation
UC3842A, UC3843A, UC2842A, UC2843A
0
-1.0
-2.0
3.0
2.0
, OUTPUT SATURATION VOLTAGE (V)
1.0
sat
V
0
, OUTPUT VOLTAGEV
O
V
CC
T
T
= 25°C
A
= -55°C
A
Source Saturation
(Load to Ground)
T
= -55°C
A
Sink Saturation
(Load to VCC)
I
, OUTPUT LOAD CURRENT (mA)
O
VCC = 15 V
80 µs Pulsed Load
120 Hz Rate
T
Gnd
Figure 14. Output Saturation Voltage
versus Load Current
VCC = 30 V CL = 15 pF T
= 25°C
A
= 25°C
A
VCC = 15 V
90%
CL = 1.0 nF T
= 25°C
A
10%
8006004002000
50 ns/DIV
Figure 15. Output Waveform
25
20
15
, SUPPLY CURRENT
CC
I
100 mA/DIV 20 V/DIV
10
, SUPPLY CURRENT (mA)
CC
I
5
UCX843A
UCX842A
RT = 10 k CT = 3.3 nF VFB = 0 V I
Sense
T
= 25°C
A
0
100 ns/DIV
010203040
VCC , SUPPLY VOLTAGE
Figure 16. Output Cross Conduction Figure 17. Supply Current versus
Supply Voltage
= 0 V
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UC3842A, UC3843A, UC2842A, UC2843A
V
CC
7(12)
V
V
CC
in
V
R
T
C
T
Voltage Feedback Input
Output Compensation
ref
8(14)
2.5V
R
Internal
Bias
R
4(7)
Oscillator
+
1.0mA
+
2(3)
-
Error
2R
R
Amplifier
1(1)
5(9)Gnd
Pin numbers in parenthesis are for the D suffix SO-14 package.
Figure 18. Representative Block Diagram
Reference
Regulator
+
3.6V
-
1.0V
Current Sense Comparator
+
-
­+
V
ref
UVLO
S
R
V
CC
UVLO
QT
Q
PWM Latch
+
-
+
­+
-
=
36V
V
C
7(11)
Output
6(10)
Power Ground
5(8)
Current Sense Input
3(5)
Sink Only Positive True Logic
Q1
R
S
Capacitor C
Latch
``Set'' Input
Output/
Compensation
Current Sense
Input
Latch
``Reset'' Input
Output
T
Large RT/Small C
T
Small RT/Large C
T
Figure 19. Timing Diagram
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UC3842A, UC3843A, UC2842A, UC2843A
OPERATING DESCRIPTION
The UC3842A, UC3843A series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off–Line and dc–to–dc converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 18.
Oscillator
The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor C is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates and internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 2 shows RT versus Oscillator Frequency and Figure 3, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within ±10% at T
= 25°C. These internal circuit refinements
J
minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 4 and 5.
In many noise sensitive applications it may be desirable to frequency–lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 21. For reliable locking, the free–running oscillator frequency should be set about 10% less than the clock frequency. A method for multi unit synchronization is shown in Figure 22. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved.
Error Amplifier
A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 8). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is –2.0 µA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop compensation (Figure 31). The output voltage is offset by two diode drops (≈ 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (V
OL
This occurs when the power supply is operating and the load
is removed, or at the beginning of a soft–start interval (Figures 24, 25). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (V comparator’s 1.0 V clamp level:
R
f(min)
Current Sense Comparator and PWM Latch
T
The UC3842A, UC3843A operate as a current mode
3.0 (1.0 V) + 1.4 V
≈
0.5 mA
= 8800 Ω
controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin1). Thus the error signal controls the peak inductor current on a cycle–by–cycle basis. The current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor R
in series with the source
S
of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where:
– 1.4 V
V
Ipk =
(Pin 1)
3 R
S
Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is:
I
pk(max)
1.0 V
=
R
S
When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 23. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the I voltage.
A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability; refer to Figure 27.
).
) to reach the
OH
pk(max)
clamp
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UC3842A, UC3843A, UC2842A, UC2843A
PIN FUNCTION DESCRIPTION
Pin
8–Pin 14–Pin
1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation. 2 3 Voltage
3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
4 7 RT/C
5 – Gnd This pin is the combined control circuitry and power ground (8–pin package only). 6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
7 12 V 8 14 V
– 8 Power Ground This pin is a separate power ground return (14–pin package only) that is connected back
– 11 V
– 9 Gnd This pin is the control circuitry ground return (14–pin package only) and is connected back to
– 2,4,6,13 NC No connection (14–pin package only). These pins are not internally connected.
Function Description
Feedback
T
CC ref
C
This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider.
information to terminate the output switch conduction. The Oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor R
sourced and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor CT through
resistor R
to the power source. It is used to reduce the effects of switching transient noise on the control circuitry.
The Output high state (VOH) is set by the voltage applied to this pin (14–pin package only). With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.
the power source ground.
to V
and capacitor CT to ground. Operation to 500 kHz is possible.
T
ref
.
T
Undervoltage Lockout
Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (V
) and the reference output (V
CC
ref
) are each monitored by separate comparators. Each has built–in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX842A, and 8.4 V/7.6 V for the UCX843A. The V
comparator
ref
upper and lower thresholds are 3.6V/3.4 V. The large hysteresis and low startup current of the UCX842A makes it ideally suited in off–line converter applications where efficient bootstrap startup techniques are required (Figure 34). The UCX843A is intended for lower voltage dc to dc converter applications. A 36 V zener is connected as a shunt regulator form V
to ground. Its purpose is to
CC
protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX842A is 11 V and 8.2 V for the UCX843A.
Output
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull–down resistor.
The SO–14 surface mount package provides separate pins
for V
(output supply) and Power Ground. Proper
C
implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the I
pk(max)
clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of V
. A zener clamp is typically connected
CC
to this input when driving power MOSFETs in systems where VCC is greater than 20 V. Figure 26 shows proper power and control ground connections in a current sensing power MOSFET application.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XA, and ± 2.0% on the UC384XA. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry.
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10
UC3842A, UC3843A, UC2842A, UC2843A
DESIGN CONSIDERATIONS
Do not attempt to construct the converter on
wire–wrap or plug–in pr ototype boards. High Frequency
circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually caused by excessive noise pick–up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low–current signal and high–current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 µF) connected directly to V and V
may be required depending upon circuit layout.
ref
CC
, VC,
This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise generating components.
Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulators closed–loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 20A shows the phenomenon graphically. At t
, switch
0
conduction begins, causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t
, the Current Sense Input
1
reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2 until the next oscillator cycle. The unstable condition can be shown if a pertubation is added to the control voltage, resulting in a small ∆I (dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn–on (t
) is increased
2
by ∆I + ∆I m2/m1. The minimum current at the next cycle
(t3) decreases to (∆I + ∆I m2/m1) (m2/m1). This pertubation is multiplied by m2.m1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn–on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m
is greater than 1, the converter
2/m1
will be unstable. Figure 20B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the ∆I pertubation will decrease to zero on succeeding cycles. This compensation ramp (m
) must
3
have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 33).
∆I
Control Voltage
m1
t
0
t
4
∆I + ∆I
Oscillator Period
m1
Inductor
Current
Control Voltage
∆I
Figure 20. Continuous Current Waveforms
(A)
m2
m
2
m
1
t
1
(B)
m3
Oscillator Period
t
t
2
m2
5
∆ I + ∆I
m
m
2
2
m
m
1
1
t
3
Inductor
Current
t
6
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11
UC3842A, UC3843A, UC2842A, UC2843A
V
ref
8(14)
R
T
External Sync Input
0.01
4(7)
C
T
47
2(3)
1(1)
The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground.
R
R
+
+
­EA
Osc
Bias
R
A
8
R
B
5.0k
6
5
5.0k
2R
R
2
5.0k
C
4
+
R
­Q
+
S
-
MC1455
8(14)
3
4(7)
7
2(3)
1
5(9)
R
1.44
f =
+ 2RB)C
(R
A
D
max
=
B
RA + 2R
1(1)
B
+
-
To Additional UCX84XA's
R
Bias
R
Osc
+
EA
2R
R
5(9)
Figure 21. External Clock Synchronization
Figure 22. External Duty Cycle Clamp and
Multi Unit Synchronization
V
V
R2
R1
Clamp
8(14)
4(7)
2(3)
1(1)
=
CC
7(12)
S
Q
R
Comp/Latch
+
­+
-
7(11)
6(10)
5(8)
3(5)
5.0V
V
+
-
Clamp
ref
+
-
­+
R
Bias
R
Osc
+
1.0mA
+
­EA
2R
R
1.0V
5(9)
1.67
R
R
+ 0.33 x 10 - 3I
2
+ 1
1
R
1
R1 + R
R
2
2
pk(max)
VClamp
=
Where: 0 ≤ V
RS
Clamp
≤ 1.0 V
V
in
Q1
8(14)
R
Bias
R
Osc
4(7)
R
S
2(3)
1.0M
1(1)
C
t
Soft-Start
+
1.0mA
+
­EA
3600C in µF
2R
Figure 23. Adjustable Reduction of Clamp Level Figure 24. Soft–Start Circuit
V
V
CC
V
7(12)
S
Q
R
Comp/Latch
Where: 0 ≤ V
+
­+
-
7(11)
6(10)
5(8)
3(5)
≤ 1.0 V
Clamp
V
C
Clamp
C
3V
5.0V
V
5(9)
=
t
Softstart
-
Clamp
ref
+
-
+
­+
1.0V
VClamp
RS
= - In 1 -
8(14)
R
Bias
R
Osc
4(7)
2(3)
R2
+
1.0mA
+
­EA
2R
R
1(1)
MPSA63
C
R1
V
Clamp
1.67
=
R
2
R
1
+ 1
I
pk(max)
in
5.0V
ref
+
-
+
-
Q1
­+
R
S
Virtually lossless current sensing can be achieved with the implementation of a
R
R
1
2
SENSEFET power switch. For proper operation during over current conditions, a
R
+ R
2
reduction of the I
1
+
-
S
Q
R
Comp/Latch
Control CIrcuitry
Ground:
To Pin (9)
clamp level must be implemented. Refer to Figures 23 and 25.
pk(max)
CC
(12)
+
-
D
(11)
G
(10)
M
(8)
(5)
R
S
1/4 W
5.0V
ref
+
-
+
-
­+
R
1.0V
5(9)
V
in
RS Ipk r
5 =
V
Pin
r
DM(on)
If: SENSEFET = MTP10N10M
Then: V
SENSEFET
pin
S
K
Power Ground
To Input Source
Return
S
Q
R
DS(on)
+ R
R
= 200
S
5 = 0.075 I
S
pk
Figure 25. Adjustable Buffered Reduction of
Clamp Level with Soft–Start
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Figure 26. Current Sensing Power MOSFET
12
7(12)
UC3842A, UC3843A, UC2842A, UC2843A
V
CC
V
in
7(12)
V
CC
V
in
5.0V
ref
+
-
+
-
+
­+
-
7(11)
Q1
6(10)
S
Q
­R
+
Comp/Latch
The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform.
5(8)
3(5)
R
C
R
S
Figure 27. Current Waveform Spike Suppression
I
B
+
0
-
Base
Charge
Removal
C
6(1)
V
in
1
Q1
5.0V
ref
+
-
+
-
­+
Series gate resistor R caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit.
Figure 28. MOSFET Parasitic Oscillations
V
CC
7(12)
5.0V
ref
+
-
+
-
+
­+
-
7(11)
+
­+
-
S
Q
R
Comp/Latch
will damp any high frequency parasitic oscillations
g
Isolation
Boundary
6(1)
5(8)
3(5)
The totem-pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C
R
S
.
1
­+
Comp/Latch
S
Q
R
5(8)
3(5)
R
C
N
R
S
Figure 29. Bipolar Transistor Drive Figure 30. Isolated MOSFET Drive
7(11)
R
Q1
g
6(10)
5(8)
3(5)
V
in
Q1
+ 0
­50% DC 25% DC
Ipk =
N
S
p
Waveforms
V
GS
V
(pin 1)
3 R
+ 0
- 1.4
S
R
S
-
N
P
N
S
8(14)
R
Bias
R
Osc
4(7)
2(3)
+
1.0mA
+
­EA
2R
R
1(1)
MCR
101
The MCR101 SCR must be selected for a holding of less than 0.5 mA at T The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
2N
3905
2N
3903
A(min)
Figure 31. Latched Shutdown Figure 32. Error Amplifier Compensation
5(9)
.
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13
From V
O
R
i
C
R
I
d
2.5V
+
2(3)
R
f
1.0mA
+
­EA
2R
R
1(1)
5(9)
Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current.
From V
O
R
p
R
i
C
R
I
C
d
p
2.5V
+
2(3)
R
f
1.0mA
+
­EA
2R
R
1(1)
5(9)
Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current.
UC3842A, UC3843A, UC2842A, UC2843A
V
CC
7(12)
V
in
18k
4.7k
0.01
4700pF
10k
100pF
From V
MPS3904
R
Slope
O
R
i
R
d
8(14)
5.0V
-m
1.0V
ref
+
-
+
-
-
+
Comp/Latch
m
R
T
R
Bias
R
4(7)
C
T
2(3)
C
R
f
f
1(1)
Osc
+
1.0mA
+
-
EA
-3.0 m
2R
R
5(9)
+
-
+
-
7(11)
6(10)
S
Q
R
5(8)
3(5)
The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation.
Figure 33. Slope Compensation
MBR1635
T1
2200 1000
MUR110
1000
1000 10
MUR110
680pF
2.7k
L2, L3 - 25 µH at 1.0 A, Coilcraft Z7157.
T1 - Primary: 45 Turns # 26 AWG
T1 - Secondary ± 12 V: 9 Turns # 30 AWG
T1 - (2 strands) Bifiliar Wound
T1 - Secondary 5.0 V: 4 Turns (six strands)
T1 - #26 Hexfiliar Wound
T1 - Secondary Feedback: 10 Turns #30 AWG
T1 - (2 strands) Bifiliar Wound
T1 - Core: Ferroxcube EC35-3C8 T1 - Bobbin: Ferroxcube EC35PCB1 T1 - Gap ≈ 0.01" for a primary inductance of 1.0 mH
8(14)
4(7)
2(3)
1(1)
115Va
c
150k
4.7Ω
+
-
MDA
202
+
250
4.7k
56k
3300pF
1N4935 1N4935
7(12)
100
5.0V
ref
Bias
+
-
+
Osc
+
-
EA
+
Comp/Latch
+
-
+
7(11)
6(10)
S
Q
R
5(8)
3(5)
68
1N4937
22Ω
1.0k
470pF
++
47
MTP
4N50
0.5Ω
5(9)
Figure 34. 27 Watt Off–Line Flyback Regulator
R
S
L1
+
+
5.0V/4.0A
5.0V RTN
+
12V/0.3A
+L2
10
±12V RTN
++
-12V/0.3A
L3
1N4937
L1 - 15 µH at 5.0 A, Coilcraft Z7156.
Test Conditions Results
Line Regulation: 5.0 V
± 12 V
Load Regulation: 5.0 V
± 12 V
Output Ripple: 5.0 V
± 12 V
Vin = 95 Vac to 130 Vac ∆ = 50 mV or ± 0.5%
∆ = 24 mV or ± 0.1%
Vin = 115 Vac, I V
= 115 Vac, I
in
= 1.0 A to 4.0 A
out
= 100 mA to 300 mA
out
∆ = 300 mV or ± 3.0% ∆ = 60 mV or ± 0.25%
Vin = 115 Vac 40 mV
80 mV
Efficiency Vin = 115 Vac 70%
All outputs are at nominal load currents, unless otherwise noted.
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14
pp pp
UC3842A, UC3843A, UC2842A, UC2843A
ORDERING INFORMATION
Operating
Device
UC3842AN PDIP–8 50 Units/Rail UC3842AD SO–14 55 Units/Rail UC3842ADR2 SO–14 2500 Tape & Reel UC3843AN UC3843AD UC3843ADR2 SO–14 2500 Tape & Reel UC3843AD1 SO–8 98 Units/Rail UC3843AD1R2 SO–8 2500 Tape & Reel UC2842AN PDIP–8 50 Units/Rail UC2842AD SO–14 55 Units/Rail UC2842ADR2 SO–14 2500 Tape & Reel UC2843AN UC2843AD UC2843ADR2 SO–14 2500 Tape & Reel UC2843AD1 SO–8 98 Units/Rail UC2843AD1R2 SO–8 2500 Tape & Reel
Temperature Range
T
= 0° to +70°C
A
T
= –25° to +85°C
A
Package Shipping
PDIP–8 50 Units/Rail
SO–14 55 Units/Rail
PDIP–8 50 Units/Rail
SO–14 55 Units/Rail
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15
UC3842A, UC3843A, UC2842A, UC2843A
MARKING DIAGRAMS
PDIP–8 N SUFFIX CASE 626
8
8
UC384xAN
FAWL
YYWW
1
SO–14
D SUFFIX
CASE 751A
14
UCx84xAD
AWLYWW
1
UC284xAN AWL YYWW
1
SO–8
D1 SUFFIX
CASE 751
8
x843A ALYW
1
x = 2 or 3 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week
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16
NOTE 2
–T–
SEATING PLANE
H
UC3842A, UC3843A, UC2842A, UC2843A
58
–B–
14
F
–A–
C
N
D
G
0.13 (0.005) B
PACKAGE DIMENSIONS
PDIP–8
N SUFFIX
CASE 626–05
ISSUE L
K
M
M
A
T
M
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400 B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 D 0.38 0.51 0.015 0.020
L
J
F 1.02 1.78 0.040 0.070 G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135 L 7.62 BSC 0.300 BSC M --- 10 --- 10 N 0.76 1.01 0.030 0.040
INCHESMILLIMETERS

M
–T–
SEATING PLANE
–A–
14 8
G
D 14 PL
0.25 (0.010) A
SO–14
D SUFFIX
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–B–
P
7 PL
M
71
0.25 (0.010) B
C
X 45
R
K
M
S
B
T
S
M
M
F
J
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009
M 0 7 0 7
 
P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
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17
UC3842A, UC3843A, UC2842A, UC2843A
PACKAGE DIMENSIONS
SO–8
D1 SUFFIX
CASE 751–07
ISSUE W
–Y–
–Z–
–X–
A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
G
C
SEATING PLANE
0.10 (0.004)
H
D
0.25 (0.010) Z
M
SXS
Y
N
X 45
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010
J
J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244
INCHES
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18
Notes
UC3842A, UC3843A, UC2842A, UC2843A
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19
UC3842A, UC3843A, UC2842A, UC2843A
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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20
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