ON Semiconductor TCC-404 User guide

Four-Output PTIC Control IC

TCC-404

Introduction

TCC−404 is a four−output high−voltage digital to analog control IC specifically designed to control and bias ON Semiconductor’s Passive Tunable Integrated Circuits (PTICs).

These tunable capacitor control circuits are intended for use in mobile phones and dedicated RF tuning applications. The implementation of ON Semiconductor’s tunable circuits in mobile phones enables significant improvement in terms of antenna radiated performance.

The tunable capacitors are controlled through a bias voltage ranging from 1 V to 28 V. The TCC−404 high−voltage PTIC control IC has been specifically designed to cover this need, providing four independent high−voltage outputs that control up to four different tunable PTICs in parallel. The device is fully controlled through a MIPI RFFE digital interface.

Key Features

• Controls ON Semiconductor’s PTIC Tunable Capacitors

• Compliant with Timing Needs of Cellular and Other Wireless System

Requirements

• 30 V Integrated Boost Converter with Four up to 28 V Programmable

DAC Outputs

• Low Power Consumption

• MIPI RFFE Interfaces (1.8 V) with 26 MHz Read and 52 MHz Write

• Automatic On−chip Turbo Calculation − Simplified Turbo Messaging

• ASDIV Switch Support over GPIO Toggle or RFFE Command to

facilitate Dual Settings for two Antennae (Dual Radio)

• Integrated Diode and Reduced External Components

• Reduced Value 2.2 mH − 4.7 mH Inductor

• Small Form Factor 1575 x 1025 mm, WLCSP 4x3 Array

• This is a Pb−Free Device

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WLCSP12

CASE 567WF

MARKING DIAGRAM

T44x

ALYWG

T44x= Specific Device Code x = a or b A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information on page 39 of this data sheet.

Typical Applications

• Multi−band, Multi−standard, Advanced and Simple Mobile Phones

• Tunable Antenna Matching Networks

• Compatible with Closed−loop and Open−loop Antenna Tuner

Applications

March, 2021 − Rev. 2

1 Publication Order Number:

TCC−404/D

VDDA

GND

L_BOOST VHV

VIO

VDDA

VREG

VHV

Booster

TCC−404

vio_on

ibias_start / vref_start

Regulators

Bandgap

VREG

POR

OSC

VIO

POR

Start

Reference

Interface

Level

Shifter

CLK DATA

4 bit

DAC

por_vreg

Registers

7 bit

DAC

7 bit

DAC

7 bit

Level

Shifter

OTP

Figure 1. Control IC Functional Block Diagram

OUTD

DAC

7 bit

DAC

VHV

OUTA

OUTB

OUTC

OUTD

L_BOOST

D1D2D3

OUTC

OUTB

OUTA

GNDA

DATA

VDDA

VIO

CLK

Figure 2. RDL Padout, Bump Side View (left), PCB footprint (right), with RDL Bump Assignment

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TCC−404

RDL Pin Out

Table 1. PAD DESCRIPTIONS

RDL Name Type Description

A1 OUTD AOH High Voltage Output D

A2 VHV AOH / AIH Boost High Voltage (can be forced externally)

A3 L_BOOST AOH Boost Inductor

B1 OUTC AOH High Voltage Output C

B2 GNDA P Analog Ground

B3 VDDA P Analog Supply

C1 OUTB AOH / AI High Voltage Output B

C2 AD DIO Antenna Diversity (Note 1)

C3 VIO P Digital IO Supply

D1 OUTA AOH / AI High Voltage Output A

D2 DATA DIO MIPI RFFE Digital IO

D3 CLK DI MIPI RFFE Clock

Legend: Pad Types

AIH= High Voltage Analog Input AOH= High Voltage Analog Output DI= Digital Input DIO= Digital Input/Output (IO) P= Power

1. To be grounded if not utilized.

ELECTRICAL PERFORMANCE SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Rating Unit

VDDA Analog Supply Voltage −0.3 to +5.5 V

VIO IO Reference Supply Voltage −0.3 to +2.5 V

I/O

HVH

ESD (HBM)

STG

AMB_OP_MAX

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

Input Voltage Logic Lines (DATA, CLK) −0.3 to VIO + 0.3 V

VHV Maximum Voltage −0.3 to 33 V

Human Body Model, JESD22−A114, All I/O 2,000 V

Storage Temperature −55 to +150 °C

Max Operating Ambient Temperature without Damage +110 °C

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TCC−404

Table 3. RECOMMENDED OPERATING CONDITIONS

Rating

Symbol Parameter

AMB_OP

J_OP

Operating Ambient Temperature −30 − +85 °C

Operating Junction Temperature −30 − +125 °C

VDDA Analog Supply Voltage 2.3 − 5.5 V

VIO IO Reference Supply Voltage 1.62 − 1.98 V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

Min Typ Max

Unit

Table 4. DC CHARACTERISTICS (T

equivalent series load of 5.6 kW and 2.7 nF; C

Symbol

Parameter Min Typ Max Unit Comment

= −30 to +85°C; V

= 22 nF; L

= 15 V for each output; 2.3 V<VDDA< 5.5 V; VIO = 1.8 V; R

OUTX

= 2.2 mH; unless otherwise specified)

BOOST

LOAD

SHUTDOWN MODE

VDDA

L_BOOST

BATT

VIO

CLK

DATA

VDDA Supply Current − − 1.5 mA

L_BOOST Leakage − − 1.5

Battery Current − − 2.5

VIO Supply Current −1 − 1

CLK Leakage −1 − 1

DATA Leakage −1 − 1

VIO Supply is Low

ACTIVE MODE

BATT

Average battery current, 2 outputs actively switching 16 V for 1205 ms to 2 V

− 1200 1600 mA At VHV = 20 V VDDA = 3.3 V

for 1705 ms to 8 V for 1705 ms

BATT_SS0

BAT_SS2

BATT_SS16

L_BOOST

Average battery current, 4 outputs @ 0 V steady state

Average battery current, 4 outputs @ 2 V steady state

Average battery current, 4 outputs @ 16 V steady state

Average inductor current, 2 outputs actively switching 16 V for 1205 ms to 2 V

− 750 950 At VHV = 20 V VDDA = 3.3 V

− 850 1200 mA At VHV = 20 V VDDA = 3.3 V

− 1000 1300 At VHV = 20 V VDDA = 3.3 V

− 1000 1400 At VHV = 20 V VDDA = 3.3 V

for 1705 ms to 8 V for 1705 ms and 3 outputs are @ 16 V steady state

L_BOOST_SS0

L_BOOST_SS2

L_BOOST_SS16

VIO_INACT

VIO_ACTIVE

Average inductor current, 4 outputs @ 0 V steady state

Average inductor current, 4 outputs @ 2 V steady state

Average inductor current, 4 outputs @ 16 V steady state

− 550 750 At VHV = 20 V VDDA = 3.3 V

− 700 1000 At VHV = 20 V VDDA = 3.3 V

− 850 1100 At VHV = 20 V VDDA = 3.3 V

VIO average inactive current − − 3 VIO is high, no bus activity

VIO average active current − − 250 VIO = 1.8 V, master sending

data at 26 MHz

LOW POWER MODE

VDDA

L_BOOST

BATT

VIO

VDDA Supply Current − − 25 mA

L_BOOST Leakage − − 6

Battery Current − − 31 I

VDDA

+ I

L_BOOST

VIO Supply Current − − 3 No bus activity

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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TCC−404

Table 5. BOOST CONVERTER CHARACTERISTICS

(VDDA from 2.3 V to 5.5 V; VIO = 1.8 V; TA = –30 to +85°C; CHV = 22 nF; L

Symbol

VHV_min Minimum programmable output volt-

Parameter Conditions Min Typ Max Unit

Active mode − 15 −

age (average), DAC Boost = 0h

VHV_max Maximum programmable output volt-

Active mode − 30 −

age (average), DAC Boost = Fh

Resolution Boost voltage resolution 4−bit DAC − 1 −

L_BOOST_LIMIT

Inductor current limit − 300 − mA

Table 6. ANALOG OUTPUTS (OUT A, OUT B, OUT C, OUT D)

(VDDA from 2.3 V to 5.5 V; VIO = 1.8 V; VHV = 26 V; TA = –30 to +85°C; R

Parameter

SHUTDOWN MODE

OUT

OUT A, OUT B, OUT C, OUT D output impedance

ACTIVE MODE

Maximum output voltage − 24 or

Minimum output voltage − − 1 V DAC A, B, C, D = 01h, DAC Boost =

Slew Rate − 3 10

OUT A, OUT B, OUT C, OUT D set in pull−down mode

Resolution Voltage resolution (1−bit) − 189 /

OFFSET

Zero scale, least squared best fit −1 − +1 LSB

Gain Error −3.0 − +3.0 %V

DNL Differential non−linearity least

squared best fit

INL Integral non−linearity least squared

best fit

RIPPLE

Over current protection − 5 65 mA Any DAC output shorted to ground

Output ripple with all outputs at steady state

Description Min Typ Max Unit Comment

7 − −

− − 1000

220

−0.9 − +0.9 LSB 1 V to 24 V with 26 V VHV

−1 − +1 LSB 1 V to 24 V with 26 V VHV

− − 40 mV RMS 1 V to 24 V with 26 V VHV

= 2.2 mH; unless otherwise specified)

BOOST

= ∞ unless otherwise specified)

load

DAC disabled

− V DAC A, B, C, D = 7Fh, DAC Boost = Fh, I

0h to Fh, I

2 V to 20 V step, measured at V

OUT

LOAD

5.6 kW and 2.7 nF, Turbo enabled

DAC A, B, C, D = 00h, DAC Boost = 0h to Fh, selected output(s) is disabled

− mV (1 LSB = 1−bit) based on VOH selection

OUT

1 V to 24 V with 26 V VHV

< 10 mA

= 15.2 V,

= equivalent series load of

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TCC−404

THEORY OF OPERATION

Overview

The control IC outputs are directly controlled by programming the four DACs (DAC A, DAC B, DAC C, DAC D) through the digital interface.

The DAC stages are driven from a reference voltage, generating an analog output voltage driving a high−voltage amplifier supplied from the boost converter (see Figure 1 − Control IC Functional Block Diagram).

The control IC output voltages can be programmed to scale from 0 V to 24 V, with 127 steps of 189 mV. The nominal control IC output can be approximated to 189 mV x (DAC value).

The control IC output voltages can also be programmed to scale from 0 V to 28 V, with 127 steps of 220 mV. The nominal control IC output can be approximated to 220 mV x (DAC value).

For performance optimization the boost output voltage (VHV) can be programmed to levels between 15 V and 30 V via the DAC_boost register (4 bits with 1 V steps). The startup default level for the boosted voltage is VHV = 28 V.

For proper operation and to avoid saturation of the output devices and noise issues, it is recommended to operate the boosted VHV voltage at least 2 V (>4 V [6 V recommended] if using Turbo−Charge Mode) above the highest programmed V

Operating Modes

voltage of any of the three outputs.

OUT

The following operating modes are available:

1. Shutdown Mode: All circuit blocks are off, the DAC outputs are disabled and placed in high Z state and current consumption is limited to minimal leakage current. The shutdown mode is entered upon initial application of VDDA or upon VIO being placed in the low state. The contents of the registers are not maintained in shutdown mode.

2. Startup Mode: Startup is only a transitory mode. Startup mode is entered upon a VIO high state. In startup mode all registers are reset to their default states, the digital interface is functional, the boost converter is activated, outputs OUT A, OUT B, OUT C and OUT D are disabled and the DAC outputs are placed in a high Z state. Control software can request a full hardware and register reset of the TCC−404 by sending an appropriate PWR_MODE command to direct the chip from either the active mode or the low power mode to the startup mode. From the startup mode the device automatically proceeds to the active mode.

3. Active Mode: All blocks of the TCC−404 are activated and the DAC outputs are fully controlled through the digital interface, DACs remain off until enabled. The DAC settings can be dynamically modified and the HV outputs will be adjusted according to the specified timing diagrams. Each DAC can be individually controlled and/or switched off according to application requirements. Active mode is automatically entered from the startup mode. Active mode can also be entered from the low power mode under control software command.

4. Low Power Mode: In low power mode the serial interface stays enabled, the DAC outputs are disabled and are placed in a high Z state and the boost voltage circuit is disabled. Control software can request to enter the low power mode from the active mode by sending an appropriate PWR_MODE command. The contents of all registers are maintained in the low power mode.

VDDA = 0

Shutdown

VIO = LOW

automatic

Low Power

(User Defined)

Battery insertion

VIO = HIGH

PWR_MODE =

0bx1

VIO = LOW

PWR_MODE = 0b00

PWR_MODE = 0b10

Figure 3. Modes of Operation

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Startup

(Registers reset)

PWR_MODE =

0bx1

Active

(User Defined)

TCC−404

VDDA Power−On Reset (POR)

Upon application of VDDA, TCC−404 will be in shutdown mode. All circuit blocks are off and the chip draws only minimal leakage current.

VIO Power−On Reset and Startup Conditions

A high level on VIO places the chip in startup mode which provides a POR to TCC−404. POR resets all registers to their default settings. VIO POR also resets the serial interface circuitry. POR is not a brown−out detector and VIO needs to be brought back to a low level to enable the POR to trigger again.

Table 7. VIO POWER−ON RESET AND STARTUP

Default State for

DAC Boost [1101] VHV = 28 V

Power Mode [01]>[00] Transitions from shutdown to startup and then automatically to active mode

DAC Enable [0000] V

DAC A Output in High−Z Mode

DAC B Output in High−Z Mode

DAC C Output in High−Z Mode

DAC D Output in High−Z Mode

VIO POR

A, B, C, D Disabled

OUT

Comment

VIO Shutdown

A low level at any time on VIO places the chip in shutdown mode in which all circuit blocks are off. The contents of the

registers are not maintained in shutdown mode.

Table 8. VIO THRESHOLDS (VDDA from 2.3 V to 5.5 V; T

Parameter

VIORST VIO Low Threshold − − 0.2 V When VIO is lowered below this threshold level the

Description Min Typ Max Unit Comments

= –30 to +85°C unless otherwise specified)

chip is reset and placed into the shutdown mode

Power Supply Sequencing

The VDDA input is typically directly supplied from the battery and thus is the first on. After VDDA is applied and before VIO is applied to the chip, all circuits are in the shutdown mode and draw minimum leakage currents. Upon application of VIO, the chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface.

Table 9. TIMING (VDDA from 2.3 V to 5.5 V; V

= 2.2 mH; VHV = 20 V; Turbo−Charge mode off unless otherwise specified)

BOOST

Parameter

POR_VREG

BOOST_START

SD_TO_ACT

SET+

SET−

SET+

SET−

Internal bias settling time from shutdown to active mode − 50 120

Time to charge CHV @ 95% of set VHV − 130 −

Startup time from shutdown to active mode − 180 250

Timing for a 2 V to 16 V transition, measured when voltage reaches within 5% of target voltage, measured between the R (5.6 kW) and C (2.7 nF) of an equivalent PTIC series load.

Timing for a 16 V to 2 V transition, measured when voltage reaches within 5% of target voltage, measured between the R (5. 6 kW) and C (2.7 nF) of an equivalent PTIC series load.

Output A, B, C, D positive settling time with Turbo − 35 −

Output A, B, C, D negative settling time with Turbo − 35 −

Description Min Typ Max Unit Comments

= 1.8 V; TA = –30 to +85°C; OUT A, OUT B, OUT C, OUT D; CHV = 47 nF;

For info only

Voltage settling time

connected on V

Effective PTIC tuning voltage

settling time,

measured between

an equivalent R and

C PTIC load

Voltage settling time

connected on V

Voltage settling time

connected on V

− 50 60

A, B, C, D

OUT

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TCC−404

Figure 4. Output Settling Diagram

Shutdown Startup

VDDA

VIO

vio_on

startup references

dvreg_en

vreg_short

avreg

dvreg

vref

nvbg_en

vbg_ok

dvreg_on (digital supply monitoring)

nforce_reset = VIO_ON& DVREG_ON)

Active

rc_enable

rc osc

clk_dig = rc_osc 64us after nforce_reset & vbg_ok & rc_enable

nreset_dig = latched 64us after (nforce_reset & vbg_ok_osc_on)

OTP read

VHV

32us

POR_VREG

boost_start

SD_TO_ACT

ure 5. Startup Timing Diagram

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TCC−404

Boost Control

TCC−404 integrates an asynchronous current control boost converter. It operates in a discontinuous mode and features spread−spectrum circuitry for Electro−Magnetic Interference (EMI) reduction.

Boost Output Voltage (VHV) Control Principle

The asynchronous control starts the boost converter as soon as the VHV voltage drops below the reference set by the 4−bit DAC and stops the boost converter when the VHV voltage rises above the reference again.

Recharge

Set VHV

Figure 6. VHV Voltage Waveform

High Impedance (High Z) Feature

In shutdown mode the OUT pins are set to a high impedance mode (high Z). Following is the principle of operation for the control IC:

1. The DAC output voltage V

OUT

DAC code

127

24 or 28 V

is defined by:

OUT

(eq. 1)

2. The RFFE_REG_0x05 controls the range of the DAC (24 or 28 V).

3. The voltage VHV defines the maximum supply voltage of the DAC supply output regulator and is set by a 4−bit control.

4. The maximum DAC DC output voltage V

OUT

is limited to (VHV – 2 V). DAC can achieve higher output voltages, but timing is not maintained for swings above VHV − 2 V.

5. The minimum output DAC voltage V

OUT

is 1.0 V

max.

CHV

Delay

Due to the slow response time of the control loop, the VHV voltage may drop below the set voltage before the control loop compensates for it. In the same manner, VHV can rise higher than the set value. This effect may reduce the maximum output voltage available. Please refer to Figure 6 below.

The asynchronous control reduces switching losses and improves the output (VHV) regulation of the DC/DC converter under light load, particularly in the situation where TCC−404 only maintains the output voltages to fixed values.

CHV

Boost

Running

Discharge

Delay

Figure 7. DAC Output Range Example A

VHV

Delay

Time

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Figure 8. DAC Output Range Example B

TCC−404

Digital Interface

The control IC is fully controlled through a digital interface (DATA, CLK). The digital interface is described in the following sections of this document.

Turbo−Charge Mode

The TCC−404 control IC has an autonomous Turbo−Charge Mode that significantly shortens the system settling time when changing programming voltages.

In Turbo−Charge Mode the DAC output target voltage is temporarily set to either a delta voltage above or a delta voltage below the actual desired target. The delta voltage is 4 volts.

After the DAC value message is received, the delta voltage is calculated by hardware, and is applied in digital format to the input of the DAC, right after trigger is received. The period for which the delta voltage is maintained to the input of the DAC, the Turbo time, is autonomously calculated and based on the following considerations:

• DACA CONTROL[1:0] / DACB CONTROL[1:0] /

DACC CONTROL[1:0] / DACD CONTROL[1:0] : These are the DAC operational mode control bits. The bit[0] in the control defines the step size of the DAC as 189 mV (0) or 220 mV (1). The bit[1] in the control enables the autonomous turbo mode. In order the Turbo operation to be enabled each DAC has to have this bit set. Otherwise the DAC values are applied without Turbo.

• TurboUpMultiplier[2:0]: If the Turbo direction is UP,

the base autonomous Turbo time calculated is multiplied with this configuration factor. The default state of this configuration provides the optimum time for the Turbo UP operation. The factor decoding is as

below: ‘000’: multiplication by 1.0 ‘001’: multiplication by 1.125 ‘010’: multiplication by 1.25 ‘011’: multiplication by 1.375 (default) ‘100’: multiplication by 1.5 ‘101’: multiplication by 1.625 ‘110’: multiplication by 1.75 ‘111’: multiplication by 1.875

• TurboDownMultiplier[2:0]: If the Turbo direction is

DOWN, the base autonomous Turbo time calculated is

multiplied with this configuration factor. The default

state of this configuration provides the optimum time

for the Turbo DOWN operation. The factor decoding is

as below: ‘000’: multiplication by 1.0 ‘001’: multiplication by 1.125 ‘010’: multiplication by 1.25 ‘011’: multiplication by 1.375 (default) ‘100’: multiplication by 1.5 ‘101’: multiplication by 1.625 ‘110’: multiplication by 1.75 ‘111’: multiplication by 1.875

• TurboDownFactor[1:0]: If the Turbo direction is

DOWN and the target voltage is below 4V the Turbo time calculation further adjusted with this factor. The default setting provides the optimum Turbo DOWN operation.

• GL_A / GL_B / GL_C / GL_D: These are the DAC

update mode configuration fields, which need to be set to turbo mode at the new DAC value update and prior to the SW trigger (optional). These bits are part of the DAC value register. If they are set to 0, the DAC is in Turbo Mode, as long as the corresponding DAC CONTROL register is configured so. If the Turbo is not enabled the DAC value is applied as is.

• The Turbo UP or DOWN voltage is decided based on

the comparison of the new DAC value and the old DAC value. If the new value is greater, the turbo direction will be UP. Otherwise it will be DOWN. In case of both DAC values being equal, there is no DAC update applied. After a turbo request is received, any trigger will start the turbo output transition. The trigger could be:

♦ A MIPI−RFFE software trigger controlled by

RFFE_PM_TRIG register

♦ An AD pad toggle if the GPIO is enabled as trigger

source or MIPI−RFFE command is sent to trigger the AD.

♦ An internal generated trigger after the corresponding

DAC value is updated, as described in section DAC Update Triggering.

The DAC values send by digital turbo−charge logic to

DACs are:

• During turbo−charge delay duration the value applied is

“DAC_new ±4 V” (the polarity of the 4 V turbo will depend on if turbo charge is up or down)

• If DAC_new > DAC old, and DAC_new+4 V is

exceeding the word length of the DAC, it is saturated to max value possible.

• If DAC_new < DAC_old, and DAC_new−4 V is a

negative number, a DAC value of 0 is applied.

♦ After turbo−charge delay duration the value applied

is the actual DAC_new.

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TCC−404

Table 10. GLIDE TIMER STEP DURATION

DAC GLIDE TIMER [4:0]

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 2

0 0 0 0 1 4

0 0 0 1 0 6

0 0 0 1 1 8

0 0 1 0 0 10

0 0 1 0 1 12

0 0 1 1 0 14

0 0 1 1 1 16

0 1 0 0 0 18

0 1 0 0 1 20

0 1 0 1 0 22

0 1 0 1 1 24

0 1 1 0 0 26

0 1 1 0 1 28

0 1 1 1 0 30

0 1 1 1 1 32

1 0 0 0 0 34

1 0 0 0 1 36

1 0 0 1 0 38

1 0 0 1 1 40

1 0 1 0 0 42

1 0 1 0 1 44

1 0 1 1 0 46

1 0 1 1 1 48

1 1 0 0 0 50

1 1 0 0 1 52

1 1 0 1 0 54

1 1 0 1 1 56

1 1 1 0 0 58

1 1 1 0 1 60

1 1 1 1 0 62

1 1 1 1 1 64

Glide Step Duration in Glide Mode [ms]

Transition from Turbo to Turbo or Immediate Update

In the event a new trigger is received during a turbo

transition, the ongoing turbo operation is halted and the new DAC value is applied immediately. There won’t be any Turbo and the hi_slew is kept low.

Transition from Turbo to Glide

In the event that a new glide transition is triggered during

a turbo event, then the turbo process is stopped and the current target value is set at the DAC output immediately without hi_slew. The new glide is started from this value.

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DAC Disable during Turbo (including active to low power mode transition)

If the DAC, which is in Turbo is disabled, the target DAC value is immediately applied without hi_slew. The DAC does not continue with the Turbo when it is re−enabled.

Turbo coming out of Low Power Mode

If the DAC, which is in low power mode is triggered with a new Turbo DAC update, the DAC_old value is taken as 0V in autonomous Turbo calculation.

TCC−404

Glide Mode

The TCC−404 control IC has a Glide Mode that significantly extends the system transition time when changing programming voltages.

Glide Mode is controlled by the following registers:

• GLIDE TIMER STEP SIZE [4:0]: This register is used

only in glide mode and shared between all DACs. It defines the step duration of each glide step. If each DAC is updated over and over with the same glide step, these fields do NOT need to be updated at each DAC update. The various configuration values are listed in Table 10.

• GL_A / GL_B / GL_C / GL_D: These are the DAC

updatemode configuration fields, which need to be set to glide mode at the new DAC value update and prior to the SW trigger (optional). These bits are part of the DAC value register. If they are set to 1, the DAC is in glide mode.

After a Glide request is received, any trigger will start the Glide output transition.

The trigger could be:

• a MIPI−RFFE software trigger controlled by

RFFE_PM_TRIG register

• An AD pad toggle if the GPIO is enabled as trigger

source or MIPI−RFFE command is sent to trigger the AD

• an internal generated trigger after the corresponding

DAC value is updated, as described in a later section.

Immediately after the trigger, the DAC_old value is loaded in the MSB’s of the upper byte of a 15 bit accumulator, while the lower byte of accumulator is being reset to 0x00.

At the same time a count step is calculated:

GLIDE_STEP[6:0] = DAC_new – DAC_old; if DAC_new > DAC_old

GLIDE_STEP[6:0] = DAC_old – DAC_new; if DAC_new < DAC_old

ACCUMULATOR[14:0] = DAC_old, 0x00;

NOTE: Glide is disabled if DAC_new = DAC_old.

From the moment the trigger is received, a tick is generated internally, with a frequency controlled by the GLIDE TIMER STEP SIZE register. Each DAC has its own tick generator running independently of the other DAC. Each time a trigger is received for a DAC, the setting of the GLIDE TIMER STEP SIZE register is sampled in a counter

dedicated to that DAC. Any update of the GLIDE TIMER STEP SIZE register after trigger is received will be ignored until the next trigger is received

Each time a tick is generated, the content of the accumulator is either incremented or decremented, depending whether DAC_new is either bigger or smaller than DAC_old.

ACCUMULATOR[14:0] = ACCUMULATOR[14:0] + GLIDE_STEP; if DAC_new > DAC_old

ACCUMULATOR[14:0] = ACCUMULATOR[14:0] − GLIDE_STEP; if DAC_new < DAC_old

Each time a tick is generated, the output of the DAC[6:0] is updated with the value of ACCUMULATOR[14:8];

The Gliding process continues until, upper 7 bits of the accumulator matches the value of the DAC_new.

ACCUMULATOR[14:8] ≥ DAC_new, when DAC_new > DAC_old

ACCUMULATOR[14:8] ≤ DAC_new, when DAC_new < DAC_old

The Glide timer will reference the 2 MHz clock divided to provide between 2 ms and 64 ms per glide step.

Each DAC is independent in terms of its switching operation, thus each DAC may be independently programmed for Normal, Turbo or Glide regardless of the switching operation of the other DACs.

Transition from Glide to Glide

In the event a new glide request is received during a glide transition, the ongoing glide operation is halted and the new glide operation is started from the DAC value, where the previous glide has left off. The DAC timers can be updated to a new value at the trigger.

Transition from Glide to Turbo or Normal Switching

In the event that a new Normal switching or Turbo DAC value is received during a Glide transition, then the Glide process is stopped and the DAC immediately switches to the newly received target value without Turbo or Glide. The hi_slew is not applied.

DAC Disable during Glide (including active to low power mode transition)

If the DAC, which is gliding is disabled, the DAC value holds on to the value where the glide stops. The DAC does not continue with the glide when it is re−enabled. It drives the last calculated DAC value without a hi_slew.

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TCC−404

ASDIV − Dual Radio Control

The TCC−404 carries two sets of registers (Radio0 and Radio1) for only DAC_A/B/C/D Value Registers. The Radio0 set consists of RFFE_REG_0x06, RFFE_REG_0x07, RFFE_REG_0x08, RFFE_REG_0x09. The Radio1 set consists of RFFE_REG_0x0A, RFFE_REG_0x0B, RFFE_REG_0x0C, RFFE_REG_0x0D. These registers set the actual DAC values when their set is active and control the glide turn on and off.

The Dual Radio Control field at RFFE_REG_0x0E register governs the operation of the Dual Radio functionality. The AD pad can be enabled to switch between the Radio0 and Radio1 values according to the state of this pad. The reset state of this register is to disable the Dual Radio operation.

The control register has the following states:

0: The AD (Antenna Diversity) pad is disabled. There is no toggling between the Radio0 and Radio1 Registers. The Radio0 DAC registers are used as the active shadow registers for trigger.

1: The AD (Antenna Diversity) pad is enabled. The Radio0 register set is triggered when the pad input transitions into “0” from “1”. The Radio1 register set is triggered when the pad input transitions into “1” from “0”. The RC clock domain retimed AD pad value defines which set of shadow registers are active for all triggering purposes.

2: The AD (Antenna Diversity) pad is disabled. The Radio0 DAC registers are triggered in any transition into this control value. Rewriting of the same value does not issue a re−trigger. The RC clock domain retimed register activates the Radio0 set of registers. A SW trigger or immediate update captures these Radio0 shadow content into active registers in any consecutive triggering.

3: The AD (Antenna Diversity) pad is disabled. The Radio1 DAC registers are triggered in any transition into this control value. . Rewriting of the same value does not issue a re−trigger. The RC clock domain retimed register activates the Radio1 set of registers. A SW trigger or immediate update captures these Radio1 shadow content into active registers in any consecutive triggering.

The AD pad does not have any pull on it. It has to be physically connected to ground or VIO supply externally. The RC domain retimed state of the dual radio

control can be observed through the upper nibble of the Dual radio control register (0x0E). A write into this field is ignored. The sampling of the AD pad is blocked during any RFFE communication to prevent trigger collision between the AD pad and the RFFE Interface. Since the conventional triggering occurs at the end of an RFFE frame, this aligns all sources of triggering.

If a DAC is disabled, the dual radio triggering does not apply to this DAC. It holds the last triggered active register value prior to getting disabled.

ASDIV − Dual Radio Operation Disabled (State0)

This is the single Radio operation, where the Radi0 set of registers in address range 0x06 to 0x09 are the shadow registers mapped to active registers. They are triggered by either immediate update (depending on SW trigger masking) or SW trigger.

The AD pad state is still captured at RC oscillator clock domain continuously. This register output can still be read over the RFFE interface at the dual radio control address (0x0E). This reading does not reflect the active DAC register. The active DAC register is enforced to be the Radio0 set.

This allows the AD pad to be utilized for any system signal state detection when the dual radio is not active.

In this mode of operation the data read back from the Radio0 or Radio1 set of registers always returns the triggered active data sourced from Radio0 set of registers

ASDIV – AD PAD Enabled (State1)

The AD pad defines the active set of registers for triggering. At each transition of the AD pad the corresponding set of DAC value registers are triggered.

Only the set of registers the AD pad is pointing to can be used to trigger an immediate update. In case of the SW trigger enable, only the registers AD pad is activating will be triggered. Therefore there is no possibility to trigger Radio0 and Radio1 set of registers at the same time.

The read back from Radio0 or Radio1 set of registers return only the triggered active register values. The source of the trigger could be either set, only the current active register is read back.

If any exit from this mode is requested, the active registers hold their state (unless the request is to transition into State2 or State3). The exit itself is not a source of trigger.

If the AD Pad value switches under low power mode, the state of the pad can’t be detected until the part is active and the DACs are re−enabled. At this point, if its state is different than the state entering into low power mode, the trigger is applied.

ASDIV – Dual Radio over RFFE – Radio0 Trigger (State2)

The AD pad value is ignored in this mode of operation. The status register at address 0x0E reflects the current active set of Radio registers. In case of the low power mode, there could be a difference between this reading and the dual radio control register value, since the register would not be sampled until the part goes back to active mode.

The transition into this state triggers the Radio0 set of registers. If the register is updated as part of an extended register write, the trigger waits until the end of the frame. This way under the same frame the corresponding Radio0 registers can be updated and a trigger is requested.

The immediate update or SW triggering can still be utilized using the Radio0 set of registers.

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