ON Semiconductor NCP1219PRINTGEVB User Manual

NCP1219PRINTGEVB

NCP1219 48 W Printer
Evaluation Board User's
Manual

Introduction

The NCP1219 is the newest part in the NCP12XX family
of current−mode flyback controllers. The controller features
dynamic self supply (DSS), eliminating the need for
external startup circuitry, contributing to a cost effective,
low parts count flyback controller design. The NCP1219
also includes a user programmable skip cycle threshold,
reducing power dissipation at light loads and in standby
mode. An externally provided latch signal delivered to the
Skip/latch pin allows the realization of protection
functionality.

The 48 W ac adapter evaluation board targets a printer
adapter application with a 24 V output, reconfigurable to

7.25 V in standby mode selectable with an external signal.
The use of DSS mode is demonstrated for low input
voltages, while an auxiliary winding is used for higher input
voltages to maintain standby power below 1 W. The
NCP1219 evaluation board shows latched−mode protection
function through the optional primary and secondary
overvoltage protection circuits.

The evaluation board is designed as an off−line printer
adapter power supply. The adapter operates across universal
inputs, 85 Vac to 265 Vac (47 Hz – 63 Hz). The adapter
supplies a regulated 24 V output. It can deliver a steady state
30 W output with transient capability of 48 W, as defined in
Figure 1.

2.0 A

1.25 A

http://onsemi.com

EVAL BOARD USER’S MANUAL

bias is provided by either DSS for low input voltages, or an
auxiliary winding for higher input voltages. The
specifications are summarized in Table 1.

Table 1. SUMMARY OF EVALUATION BOARD
SPECIFICATIONS

Requirement Unit Min Max

Input Voltage Vac 85 265

Line Frequency Hz 47 63

Output Voltage Vdc 23.8 24.2

Output Current Adc − 1.25 (2.0 transient

Output Power W − 30 (48 transient peak)

Average
Efficiency (EPA
Energy Star 2.0

Compliance)

Standby Voltage Vdc 7 8

Standby Power W − 1

Output Ripple

Voltage

Output Voltage

Under/Overshoot

During Transient

Load Step from

0.92 A to 2.0 A

h

83.5 −

avg

mV − 200

mV − 200

peak)

Output Current (A)

Figure 1. Transient Output Current Specification

700 ms

time (ms)

300 ms

The system has a low voltage standby mode enabled by
pulling the MC node low. In standby mode the converter
supplies 70 mA of standby current at 7.25 V while
maintaining input power below 1 W. The system is
self−contained, with the NCP1219 bias being provided by
the bulk voltage through an internal startup circuit. The IC

© Semiconductor Components Industries, LLC, 2012

November, 2012 − Rev. 3

0.92 A

Design Procedure

The converter design procedure is divided into several

steps:

• Power Component Selection

• Loop Stability Analysis and Compensation

• IC Supply Circuits

• External Protection Circuits

• Standby Reconfiguration Circuit

Throughout this application note, the minimum and
maximum input voltages are referred as low and high line,
respectively.

The evaluation board schematic is provided in Figure 2
for reference to component values throughout the design
procedure.

1 Publication Order Number:

EVBUM2161/D

J5

123

C20

220uF/6.3V

SGND

NCP1219PRINTGEVB

R34

R35

10K

1k

R32

U4

TL431B

2.26K

Q6

2N7002L

R33

8.06k

330mF/35V

C16

L1

2.2u

1000uF/35V

C15

C14

470pF/250V

D12

100

R18

JP1

1N4007

D2

1N4007

D1

T1

4.75M

R1

F1

C1

2A/250V

C10

C6

JP3

10u, 1.4A

4.75M

R2

0.22mF/275V

MUR420RLG

5

T2

D10

4700pF/630V

R14

120K/0.5W

100u/400V

D13

D4

1N4007

D3

431

1N4007

6

1N4007RLG

1N4007

R15

D6

VCC

2

10

MMSD914T1G

C7

open

000

R13

JP2

1

HS1

Q5

R5

1.4M

VHOUT

2

C21

20

R9

R20

SPA07N65C3

R37

10K

22u/25V

1.82K

R41

open

R11

R8

1.4M

open

open

R10

R16

ZD1

open

12

4

U2

open

R51

1.69

R52

1.69

R53

1.69

R54

1.69

1.82K

R42

LATCH

open

ZD2

3

U1

open

LATCH

HV

Skip/

latch

C18

open

R30

Q3

1nF/440V

D5

J4

VCC

CS

C5

open

open

open

VHOUT

MMSD914T1G

ZD4

open

C3

0.1/25V

DRV

GND

NCP1219AD65R2G

100p

R12

open

C8

open

990

R23

J3

J2

R4

JP4

C9

R6

10

FB

C4

C2

1000p

R3

open

VHOUT

R24

2.49K

12

4

412

U3

SFH615A-3

R31

R25

3

19.6K

C19

0

0.033

J1

AC Connector C8

Figure 2. Evaluation Board Schematic

http://onsemi.com

2

NCP1219PRINTGEVB

Transformer

The turns ratio, N, is chosen to minimize the voltage
stresses placed on main switch, Q5, and the secondary diode,
D12. N is calculated using Equation 1,

) V

Ǔ

f

bulk(max)

(eq. 1)

N +

@ǒV

BV

DSS

k

out

C

@ kD* VOS* V

N

S

+

N

P

where NS is the number of turns on the secondary winding,
N

is the number of turns on the primary winding, kc is the

P

clamp voltage ratio, V

is the regulated output voltage, V

out

is the forward voltage drop of the secondary rectifying
diode, BV
k

is the derating factor of the main switch, Vos is the clamp

D

voltage overshoot, and V

where f
I

out(crit)

is the breakdown voltage of the main switch,

DSS

bulk(max)

L

P(crit)

is the switching frequency of the controller, and

osc

is the maximum DC bulk

+

2 @ f

OSC

@ V

out

@ I

out(crit)

h @ V

@ǒV

is the load current at which the transition between
DCM and CCM occurs. By operating in the transition
between DCM and CCM, the secondary RMS current is
minimized, reducing the requirements on the transformer
and output capacitor. For the evaluation board design, with
a transition occurring at I

= 1.6 A, the primary inductance

out

is 350 mH.

Sense Resistor

To calculate the value of the current current sense resistor,

R

, the peak current of the primary winding of the

sense

transformer must first be calculated. The energy storage
relationship is used to determine the peak primary current,
calculated using Equation 3.

I

peak

+

Ǹ

L

P(crit)

@ f

out

OSC

@ h

(eq. 3)

2 @ P

Using the specified peak output power to calculate the

peak primary current:

Ǹ

2 @ 48 W

350 mH @ 65 kHz @ 85%

+ 2.23 A

The NCP1219 has a current limit comparator reference

voltage, V

, of 1 V, typical. R

ILIM

, is calculated using

sense

Equation 4.

V

+

PWM

I

peak

R

sense

This results in a value of 449 mW for R

(eq. 4)

sense

(R51||R52||R53||R54). A 430 mW resistor is chosen for
sufficient margin to deliver the peak output power.

voltage supplying the controller. Using a 650 V MOSFET
with a derating factor of 0.8 and a clamp voltage ratio, k

1.6 yields a turns ratio of 0.303. This maintains sufficient
margin for the voltage rating of the MOSFET.

The power components for the flyback topology can be
selected for operation in either discontinuous conduction
mode (DCM) or continuous conduction mode (CCM).
Measuring the tradeoffs of the two modes at the power level
required for this design, the transformer is designed to make
a transition between DCM and CCM at low line and a load

f

current of 1.6 A. This ensures that the converter operates in
DCM at nominal load. The critical primary inductance,
L

, to cause this transition is calculated using

P(crit)

Equation 2.

V

)V

out

bulk(min)

bulk(min)

2

ǒ

@

V

out

)

The primary rms current, I

f

Ǔ

N

)V

N

f

Ǔ@ǒ

V

)V

out

N

f

) h @ V

Ǔ

bulk(min)

is needed in order to

L(rms)

calculate the power dissipation in the R
maximum duty ratio, D

D

max

, is calculated using Equation 5.

max

V

+

V

out

out

) N @ V

bulk(min)

The maximum duty ratio determines the change in
primary current, ΔI

Finally, ΔIL is used to calculate I

I

+ D

L(RMS)

, as shown in Equation 6.

L

V

max

bulk(min)

L

pri

@ǒI

peak

@ f

DIL+

Ǹ

@ D

OSC

2

* I

max

as in Equation 7.

L(RMS)

@ DIL)

peak

The power dissipated in the sense resistor is then calculated
using Equation 8.

P

R

sense

+ I

L(RMS)

2

@ R

sense

The power rating of the resistor is chosen to handle the
maximum power dissipation. For this design, the worst case
peak power dissipation is calculated to be 400 mW. Four
1206 surface mount resistors in parallel are chosen to
dissipate the power. Note that this is the worst case power
dissipation calculated assuming a continuous output current
of 2 A. For normal operating conditions (I

out

power dissipation is 208 mW.

(eq. 2)

. First, the

sense

(eq. 5)

(eq. 6)

(eq. 7)

2

DI

L

Ǔ

2

(eq. 8)

= 1.25 A), the

c

, of

http://onsemi.com

3

NCP1219PRINTGEVB

Primary Switch

The main MOSFET switch, Q5, is selected to operate at
a junction temperature of 120°C at an ambient temperature
of 85°C. The maximum power dissipation for Q5 is
calculated using Equation 9, where T
junction temperature, T

is the thermal resistance of the MOSFET.

R

JA

q

An isolated TO−220 with an R

is the ambient temperature, and

A

ǒ

T

* T

+

max

R

qJA

JA

q

P

max

maximum power dissipation of 438 mW. The R

is the maximum

MAX

Ǔ

A

(eq. 9)

of 80°C/W results in a

DS(on)

required to satisfy the maximum power dissipation at
nominal load is approximated by Equation 10. The value is
taken from the datasheet curves for the desired junction
temperature, provided by the MOSFET manufacturer.

P

R

DS(on)

+

I

L(RMS)

max

2

(eq. 10)

The MOSFET is sized so that the thermal requirements
are met under nominal load (30 W). Equation 3 is used to
determine the peak current, in this case using 30 W for P

out

yielding a peak current of 1.7 A.

The controller operates in DCM at low−line and nominal
load. The equation for the primary rms current in DCM is
shown in Equation 11. In this example, the primary rms
current is calculated to be 0.69 A.

D

max

I

L(RMS)

+ I

peak

Ǹ

@

3

(eq. 11)

Substituting the resulting primary rms current into
Equation 10, we find an R

of less than 1.1 W is

DS(on)

required. The Infineon SPA07N65C3 n−channel MOSFET,
with R
conservative approach to the selection of Q5. The R

= 600 mW is used in this design. This is a

DS(on)

used

JA

q

to calculate the maximum power dissipation assumes the
MOSFET operates in free air, without a heat sink. This
design includes an aluminum heat sink attached to the body
of the TO−220, reducing the thermal resistance and
increasing the maximum power capability of the MOSFET.

Secondary Rectifier

The peak inverse voltage, PIV, of D12 is calculated by
Equation 12.

PIV + V

375 V @ 0.303 ) 24 V + 138 V

bulk(max)

@ N ) V

out

(eq. 12)

Applying a silicon derating factor of 0.8 to PIV, the
minimum breakdown voltage of D12 must be greater than
173 V. An MUR420, 200 V ultrafast rectifier is selected.

The power dissipated in the secondary diode, P
approximated by Equation 13, where V
voltage of the selected diode, and I

out

is the forward

f

is the nominal output

current of the converter.

Pd+ Vf@ I

Output Capacitor

out

The output capacitor is selected to satisfy the output
voltage ripple requirements of the controller. The output
capacitor must supply the entire output current during the
controller on time. The capacitor value is calculated using
Equation 14,

I

@ t

out

C

+

out

where t

is the maximum on time of the controller,

on(max)

which can be calculated using D

on(max)

V

ripple

from Equation 5. For

max

this design, Equation 14 results in a capacitor value of 70 mF.

The effective series resistance, ESR, of the capacitor also
plays a significant role in the selection of the output
capacitor. The secondary peak current charges the output

,

capacitor during each cycle, and the ESR must not cause a
voltage drop greater than the ripple voltage. The acceptable
ESR is calculated using Equation 15,

V

ripple

I

sec(peak)

where I

sec(peak)

ESR v

is proportional to the primary peak current

by the turns ratio, as given by Equation 16.

I

I

sec(peak)

+

pri(peak)

N

An ESR of 31 mW is required to meet the 200 mV output
ripple requirement.

The output capacitor also has a specified rms current
capability that must be considered. The rms current seen by
the capacitor, I

where I

Cout(RMS)

I

Cout(RMS)

is the maximum dc load current supplied by

out(avg)

the converter and I

, is calculated using Equation 17,

Ǹ

+ I

sec(RMS)

sec(RMS)

is the secondary rms current. For

2

* I

out(avg)

the maximum load current, the controller operated in CCM
and I

sec(RMS)

For this design at maximum load, I

is calculated using Equation 18.

Cout(RMS)

output capacitor with an ESR of 18 mW and an rms ripple
current capability of 2.77 A is selected, and the resulting
capacitor value is 1000 mF.

is

d

(eq. 13)

(eq. 14)

(eq. 15)

(eq. 16)

2

(eq. 17)

is 2.44 A. An

I

sec(RMS)

+

Ǹ

(

1 * D

)

ǒ

I

@

max

sec(peak)

http://onsemi.com

DI

L

N2@ 3

2

(eq. 18)

Ǔ

DI

2

* I

sec(peak)

4

L

@

)

N

NCP1219PRINTGEVB

Auxiliary Supply Regulator

The HV pin of the NCP1219 can be tied directly to the
bulk storage capacitor and used to supply the IC in the
absence of an auxiliary winding, for instance, during the
startup of the adapter. The startup current is controlled
internally and supplied to the V
V

pin. While VCC is less than the Inhibit threshold

CC

voltage, the V

capacitor is charged with a current source

CC

capacitor through the

CC

of 200 mA (typical). Once the inhibit threshold is exceeded,
the startup current (typically 13.5 mA) is supplied to the
VCC capacitor. When V
current source is disabled, and the V
discharged until V

decreases to less than V

CC

is exceeded, the internal

CC(on)

capacitor is

CC

CC(MIN)

, at
which time the startup current source is enabled, starting the
DSS cycle over again.

The evaluation board contains several options for the HV
pin connection and the biasing of V
is used to supply V

at high line conditions in order to

CC

. An auxiliary winding

CC

satisfy the low standby power requirement of 1 W.

Option 1 – Bulk Connection with Forward Auxiliary
Winding

Connecting the HV pin to the bulk voltage and using a
forward auxiliary winding provides an IC bias dependant on
input voltage, but independent of the output voltage. This is
required in this design due to the dual output voltage design.
Otherwise the converter would require additional circuitry
to prevent the converter from entering DSS mode during the
standby conditions. Figure 3 shows this configuration. The
voltage is supplied by the auxiliary winding through a series
diode.

NAńNP+

ǒ

VCC) V

V

bulk

Ǔ

f

(eq. 19)

This implies that, as the input voltage drops, the auxiliary
winding can not supply the IC. When V
V

CC(MIN)

supplied to the V

, the startup circuit is enabled and the IC bias is

capacitor by the internal current source.

CC

reduces to

CC

Alternately, an auxiliary voltage greater than 20 V can be
used by clamping V

using a zener diode, minimizing the

CC

input voltage at which the controller enters DSS mode. This
is shown in Figure 4.

D12

V

out

Skip/

HV

latch

FB

CS

VCC

GND

DRV

NCP1219

Figure 4. VCC Connection using a Forward Auxilliary

Winding with Added Zener

Option 2 – Full−time DSS Mode (No Auxiliary Winding)

The auxiliary winding is not necessary with DSS mode, so
the connection to the auxiliary winding can be removed
altogether, as shown in Figure 5.

D12

V

out

Skip/

HV

latch

FB

CS

VCC

GND

DRV

NCP1219

Figure 3. VCC Connection Using a Forward Auxiliary

Winding with DSS at Low−Line

The voltage on the VCC pin can not exceed 20 V.
Therefore the ratio between the number of turns on the
auxiliary winding, NA, and the primary winding, N
chosen to maintain V
voltage. N

is calculated using Equation 19.

A/NP

below 20 V at the maximum input

CC

, is

A/NP

http://onsemi.com

D12

Skip/

HV

latch

FB

CS

VCC

GND

DRV

NCP1219

Figure 5. VCC Connection with Full−Time DSS Mode

(No Auxiliary Winding)

If standby power dissipation is not an issue, this option

eliminates the extra components used with the auxiliary

5

V

out

NCP1219PRINTGEVB

winding. Care must be taken not to exceed the thermal
capability of the IC. The power dissipated during DSS mode
is approximated by Equation 20.

P

+ I

DSS

where VHV is the HV pin voltage, and I

CC3

@ V

HV

is the controller

CC3

supply current during normal switching operation. I

(eq. 20)

has

CC3

a component that is dependant on the gate charge of Q5, as
shown in Equation 21,

(eq. 21)

where Q

I

+ I

CC3

is the total gate charge of Q5.

g(tot)

CC2

) Q

g(tot)

@ f

SW

The amount of power the controller is capable of
dissipating depends on many factors, including the V

CC

capacitor value, airflow conditions, proximity of the
controller to other heat generating components on the board,
and the layout of the metal traces on the board and their heat
spreading characteristics. To determine the thermal
characteristics of the controller in the application, the
evaluation board is placed in a controlled ambient
temperature and the V
shutdown is measured. R

that results in temperature

HV

of the controller is given by

JA

q

Eequation 22,

T

* T

DSS

A

(eq. 22)

+

SHDN

P

R

qJA

where TA is the ambient temperature of the system and
T

is the junction temperature at which a thermal

SHDN

shutdown (TSD) fault occurs. For the evaluation board, with
the HV pin tied directly to V
a TSD event, and R

is calculated as 82.5°C/W.

JA

q

It is common to include a resistor, R

, a VHV of 257 V results in

bulk

, in series between

bulk

the bulk voltage and the HV pin to spread the power
dissipation between the controller and R

bulk

. R

bulk

often
consists of at least two resistors in series for protection
against shorted component testing. The same power
dissipation limit is imposed on the controller as in the case
where no series resistor is used. Therefore, adding R

bulk

allows the maximum bulk voltage to increase by dissipating
the difference in the power while the startup circuit is
charging C

. The increased bulk voltage is given by

CC

Equation 23,

P

+

I

DSS

CC3

) I

start

@ R

bulk

(eq. 23)

where P
the R

q

V

bulk

is found by rearranging Equation 22 and using

DSS

measured above.

JA

When adding the series resistors, it is recommended to
maintain a minimum V
headroom to allow the startup circuit to supply I
V

pin. Therefore, at low line, the resistance between the

CC

of 40 V to ensure there is enough

HV

start

to the

bulk voltage and the HV pin can not exceed that given by
Equation 24,

ǒ

V

R

bulk

bulk(min)

v

I

start(min)

* 40 V

Ǔ

(eq. 24)

where I

start(min)

provided to the V
V

bulk(min)

more than 10 kW. For the evaluation board, R
as 3.6 kW so that I
range. For this evaluation board, with R

is the specified minimum startup current

CC

pin. I

start(min)

= 5 mA and assuming

= 90 V, the added series resistance should be no

is chosen

bulk

is 14.7 mA across the input voltage

start

= 3.6 kW, I

bulk

start

= 14.7 mA and a maximum ambient temperature of 85°C,
the resulting maximum V

is 310 V, a 53 V increase in

bulk

comparison to the limit when connecting directly to the bulk
voltage.

The power dissipated by R

during the DSS cycle is

bulk

found using the rms current supplied through the startup
circuit during the DSS cycle, given by Equation 25,

P

Rbulk

+ R

bulk

@ǒI

start(RMS)

Ǔ

(eq. 25)

2

Option 3 – Half−Wave Rectified Connection

To reduce the power dissipation of DSS mode at high
input voltage, the HV pin is connected to the half−wave
rectified node of the bridge rectifier in place of the bulk
voltage. Figure 6 illustrates this configuration.

D12

V

out

Skip/

HV

latch

FB

CS

VCC

DRV

GND

NCP1219

Figure 6. VCC Connection with Full−time DSS Mode

Supplied By the Half−Rectified Sine Wave

The average voltage applied to the HV pin is reduced
because, during half of the input voltage cycle, the HV
voltage is a function of the input sinusoid and the other half
of the cycle the input voltage is zero. The half−wave
rectified waveform is illustrated in Figure 7.

V

peak

V

AVG, (half-wave)

Half-Wave

Rectified Voltage

Figure 7. Half−Wave Rectified Waveform

time

http://onsemi.com

6

NCP1219PRINTGEVB

The average HV pin voltage, V

AVG(half−wave)

, is

calculated using Equation 26.

V

V

AVG(half*wave)

+

Peak

p

(eq. 26)

In comparison, using the example from option 2
(full−time DSS mode with the HV pin connected to V
power dissipation, P

, of 270 mW, and a junction

DSS

bullk

temperature of 107°C is achieved.

The techniques mentioned above can be explored in
different combinations to optimize standby power and
thermal performance of the NCP1219.

Feedback Network

The negative feedback loop that controls the output
voltage senses the output voltage using a voltage divider and
compares it to the internal reference voltage of a TL431
precision reference. The output current of the TL431 is then
a function of the bias that is required to force the internal
reference of the TL431 and the output voltage to be equal.
The TL431 output drives the cathode of an optocoupler,
providing isolation between the primary and secondary side
of the converter. The collector of the optocoupler is
connected to the FB pin of the NCP1219, closing the
feedback loop, as shown in Figure 8.

out

I

),

1

,V

out

V

2

,I

1

I

FB

V

Figure 8. Feedback Network

VFB is compared to VCS to determine the on time. If there
is an increase in load current, V
V

. This causes I1 to decrease. The optocoupler collector

out

current, I

, also decreases causing VFB to increase,

2

begins to decrease with

1

increasing on time for the next switching cycle. The timing
diagram describing the feedback loop is shown in Figure 9.

L,pri

I

time

Figure 9. Feedback Loop Timing Diagram

Standby Reconfiguration Control

The evaluation board has a dual output voltage mode. In
normal operation, the converter provides a 24 V regulated
output. During standby mode, the output supplies 7.25 V
with a standby current of 70 mA. The output voltage level
is selected by actively altering the voltage divider supplying
the feedback loop. An additional resistor is connected in
series with R32. A small signal MOSFET (Q6) is placed in
parallel with the added resistance, as shown in Figure 10.

http://onsemi.com

7

NCP1219PRINTGEVB

Figure 10. Standby Mode Reconfiguration Circuit

When 5 V is applied to the MC pin, Q6 turns on and R33
is bypassed. In this mode, the voltage divider is set by R31
and R32 only, providing 24 V to the output. If the MC pin is
grounded or floating Q6 is off connecting R33 in series with
R32. This reduces the voltage divider value and sets the
output to 7.25 V.

Loop Stability

The output voltage regulation is provided by the negative
feedback loop described in the previous section. If the
feedback loop is not stable, the converter oscillates. To
ensure the stability of the converter, the closed loop
frequency response phase margin should be greater than 45°
at the crossover frequency. The first step in stabilizing the
closed control loop is to analyze the frequency response of
the power stage. Its contribution will determine the pole and
zero placement. The gain and pole and zero placement of the
feedback network are selected to achieve the desired
crossover frequency and phase margin.

ON Semiconductor provides the excel based design tool
”FLYBACK AUTO”. It provides an automated method of
compensating the feedback loop of an isolated flyback
converter using the TL431 and an optocoupler. The tool
takes system level inputs from the user, such as bulk input
voltage, output voltage, output current, and controller
switching frequency. A screenshot of the parameter capture
screen is shown in Figure 11.

Figure 11. Screenshot of the Parameter Capture

Screen from the Design Tool FLYBACK AUTO

After the input and output parameters are entered, the
frequency response of the power stage is calculated. The
response is presented both numerically, showing the
frequency of each pole and zero, along with the dc gain of
the power stage and graphically through the use of a Bode
plot. This is shown in the screenshot presented in Figure 12.

Figure 12. Screenshot of the Power Stage Frequency

Response from the FLYBACK AUTO tool

Next, the contribution of the optocoupler to the frequency
response of the system is considered. The pole of the
compensation is selected to be less than that of the
optocoupler. The user enters information about the
optocoupler collected from the datasheet or through
frequency response characterization of the chosen
optocoupler. The optocoupler chosen for the evaluation
board design is a Vishay SFH615A−3. Using the test setup
shown in Figure 13, the optocoupler frequency response and
CTR are measured. For the frequency response
measurement, the dc bias of the 2.49 kW resistor is adjusted
until the collector of the optocoupler measured 2.5 V.

http://onsemi.com

8

NCP1219PRINTGEVB

Figure 13. Optocoupler Frequency Analysis Test

Circuit

From Figure 14, the crossover frequency of the
SFH615A−3 is measured at 4.7 kHz. From the dc bias of the
optocoupler, the current transfer ratio, CTR is measured as
41%. These values are used in the optocoupler page of the
compensation tool.

MAG (dB)

PHASE (°)

Figure 15. Screenshot of the Total Frequency

Response Given By the Design Tool FLYBACK AUTO

A bill of materials for the compensation network is
provided by the tool based on the calculations of the
compensation network, as shown in Figure 16.

Figure 14. Frequency Response of Vishay’s

SFH615A3 Optocoupler

This data is entered into the tool and the capacitance

contribution of the optocoupler is calculated.

The pole and zero placement of the type 2 compensation
configuration is provided by the design tool based on the
desired crossover frequency and phase margin entered by
the user. If the desired crossover frequency causes the pole
frequency of the compensation network to exceed the pole
frequency of the optocoupler, then the crossover frequency
is automatically reduced.

The total loop response is provided by the design tool
based on the power stage response, optocoupler pole
location, and the type 2 compensation design. The user can
check the frequency response at various input voltages and
load conditions to verify system stability over all conditions,
as shown in Figure 15.

Figure 16. Screenshot of the Final Feedback Network

Bill of Materials

The design tool provides a good starting point; a solution
that allows the user to quickly set up a stable feedback
network. It does not, however, release the designer from
measuring the frequency response of the system and
optimizing the loop stability and transient response
tradeoffs. Using an AP Instruments AP200 frequency
response analyzer, the frequency response of the power
stage is confirmed, as shown in Figure 17. The measured
gain boost required for a crossover frequency of 1 kHz is
17 dB, slightly higher than estimated by the compensation
tool.

http://onsemi.com

9