ON Semiconductor NCP1215 User Manual

© Semiconductor Components Industries, LLC, 2005
July, 2005 − Rev. 3
1 Publication Order Number:
NCP1215/D
NCP1215
Low Cost Variable OFF Time Switched Mode Power Supply Controller
The NCP1215 is a controller for low power off−line flyback Switchemode Power Supplies (SMPS) featuring low size, weight and cost constraints together with a good low standby power performance. The operating principle uses switching frequency reduction at light load by increasing the OFF Time. Also, when OFF T ime expands, the peak current is gradually reduced down to approximately 1/4 of the maximum peak current to prevent from exciting the transformer mechanical resonances. The risk of acoustic noise is thus greatly diminished while keeping good standby power performance.
A low power internal supply block also ensures very low current consumption at startup without hampering the standby power performance.
A special primary current sensing technique minimizes the impact of SMPS switching on control IC operation. The choice of peak voltage across the current sense resistor allows dissipation to be further reduced. The negative current sensing technique offers advantages over a traditional approach by avoiding the voltage drop incurred by traditional MOSFET source sensing. Thus, the IC drive capability is greatly improved.
Finally, the bulk input ripple ensures a natural frequency dithering which smooths the EMI signature.
Features
Pb−Free Package is Available
Variable OFF Time Control Method
Very Low Current Consumption at Startup
Natural Frequency Dithering for Improved EMI Signature
Current Mode Control Operation
Peak Current Compression Reduces Transformer Noise
Programmable Current Sense Resistor Peak Voltage
Undervoltage Lockout
Typical Applications
Auxiliary Power Supply
Standby Power Supply
AC−DC Adapter
Off−line Battery Charger
1
8
SOIC−8 D SUFFIX CASE 751
18
5
3 4
(Top View)
FB
CS
NC
PIN CONNECTIONS
7 6
2
NC
CT
GND
Gate
V
CC
MARKING
DIAGRAMS
FAA = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week
1
6
TSOP−6
(SOT23−6, SC59−6)
SN SUFFIX
CASE 318G
FAAYW
1
6
SOIC−8
1
3
FB
CS
2GND
CT
4
Gate
6
(Top View)
5
V
CC
TSOP−6
ORDERING INFORMATION
P1215 ALYW
Device Package Shipping
NCP1215DR2 SOIC−8 2500 Tape & Reel
NCP1215SNT1 TSOP−6
3000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
s
Brochure, BRD801 1/D.
1
8
http://onsemi.com
NCP1215DR2G SOIC−8
(Pb−Free)
2500 Tape & Reel
NCP1215
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2
Figure 1. Typical Application
LineLine
N
+
FB
GND
CT CS
Gate
Vcc
NC
NC
+
+
+
*
*If your application requires a gate−source resistor, please refer to design guidelines in this document.
Figure 2. Representative Block Diagram
Feedback Loop
Control
+
FB
+
Off−Time
Comparator
CT
Voffset
0−7 V
10 mA
12.5−50 mA
CS
+
GND
Current Sense Comparator
Reset
Set
Q
Q
Reference
Regulator
V
DD
I
ref
+
Undervoltage
Lockout
12/8.5 V
Gate
V
CC
Gate Driver
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Á
PIN FUNCTION DESCRIPTION
TSOP−6
SOIC−8
Symbol
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Description
4 1 FB The FB pin provides voltage feedback loop. The current injected into the pin determines the
primary switch OFF time interval. It also influences the peak value of the primary current. 3 2 CT Connection for an external timing programming capacitor. 1 3 CS The CS pin senses the power switch current. 2 4 GND Primary and internal ground. 6 5 Gate Output drive for an external power MOSFET. 5 6 Vcc Power supply voltage and Undervoltage Lockout. 7 7 NC Unconnected pin. 8 8 NC Unconnected pin.
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Á
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage V
cc
18 V
FB Pins Voltage Range V
FB
−0.3 to 18 V
CS and CT Pin Voltage Range V
in
−0.3 to 10 V
Thermal Resistance, Junction−to−Air (SOIC−8 Version)
R
q
JA
178 °C/W
Junction Temperature T
J
150 °C
Storage Temperature Range T
stg
−60 to +150 °C
ESD Voltage Protection, Human Body Model (Except CT Pin) V
ESD−HBM
2.0 kV
ESD Voltage Protection, Human Body Model for CT Pin V
ESD−HBM−CT
1.5 kV
ESD Voltage Protection, Machine Model (Except CT Pin) V
ESD−MM
200 V
ESD Voltage Protection, Machine Model for CT Pin V
ESD−MM−CT
150 V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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ELECTRICAL CHARACTERISTICS (V
CC
= 12 V, for typical values Tj = 25°C, for min/max values Tj = 0°C to +105°C, unless
otherwise noted.)
Characteristic Symbol Min Typ Max Unit
VOLTAGE FEEDBACK
Offset Voltage
V
offset
1.05 1.19 1.34 V
Maximum CT Pin Voltage at FB Current = 25 mA (Including V
offset
) V
CT−25mA
2.4 3.1 4.3 V
Maximum CT Pin Voltage at FB Current = 50 mA (Including V
offset
) V
CT−50mA
3.6 4.6 6.2 V
CT PIN − OFF TIME CONTROL
Source Current (CT Pin Grounded)
I
CT
8.0 9.8 11.5
mA
Source Current Maximum Voltage Capability V
CT−max
6.5 V
Minimum CT Pin Voltage (Pin Unloaded, Discharge Switch Turned On) V
CT−min
20 mV
CURRENT SENSE
Minimum Source Current (I
FB
= 180 mA, CT Pin Grounded)
I
CS−min
8.0 12.5 16
mA
Maximum Source Current (IFB = 0 mA, CT Pin Grounded)
I
CS−max
40 49 58
mA
Comparator Threshold Voltage V
th
15 42 80 mV
Propagation Delay (CS Falling Edge to Gate Output) t
delay
215 310 ns
GATE DRIVE
Sink Resistance (I
sink
= 30 mA) R
OL
25 40 90
W
Source Resistance (I
source
= 30 mA) R
OH
60 80 130
W
POWER SUPPLY
V
CC
Startup Voltage V
startup
12.5 14.2 V
Undervoltage Lockout Threshold Voltage V
UVLO
7.2 9.0 V
Hysteresis (V
startup
− V
UVLO
) V
hys
2.2 3.5 V
VCC Startup Current Consumption (V
CC
= 8.0 V) I
CC−start
2.8 6.5
mA
VCC Steady State Current Consumption
(C
GATE
= 1.0 nF, f
SW
= 100 kHz, FB open)
I
CC−SW
0.55 0.9 1.75 mA
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TYPICAL CHARACTERISTICS
−25
11.5
50
11.2
250
V
startup
, (V)
11.0
TJ, JUNCTION TEMPERATURE (°C)
11.6
TJ, JUNCTION TEMPERATURE (°C)
11.1
11.3
11.4
125
V
offset
, (V)
1.08
Figure 3. V
startup
Threshold vs. Junction
Temperature
Figure 4. V
UVLO
Threshold vs. Junction
Temperature
Figure 5. Operating Current Consumption vs.
Junction Temperature
Figure 6. Offset Voltage vs. Junction
Temperature
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Current Sense Source Current vs.
Junction Temperature
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Current Sense Threshold vs.
Junction Temperature
TJ, JUNCTION TEMPERATURE (°C)
1.12
1.00
1.16
1.20
75 100 −25
8.7
50
8.4
250
V
UVLO
, (V)
8.2
8.8
8.3
8.5
8.6
12
5
75 100
−25
0.985
50
0.970
250
I
CC−SW
, (mA)
0.960
0.990
T
J
, JUNCTION TEMPERATURE (°C)
0.965
0.975
0.980
125
75 100 −25 5025012
5
75 100
1.04
1.06
1.10
1.14
1.18
1.02
−25
48.0
50
46.5
250
I
CS−max
, (
m
A)
45.5
49.0
46.0
47.0
47.5
12575 100
48.5
−25
55
50
40
250
V
CS−th
, (mV)
30
65
35
45
50
12
5
75 100
60
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