查询NCP1200AP100G供应商查询NCP1200AP100G供应商
NCP1200A
PWM Current−Mode
Controller for Universal
Off−Line Supplies Featuring
Low Standby Power
Housed in SOIC−8 or PDIP−8 package, the NCP1200A enhances
the previous NCP1200 series by offering a reduced optocoupler
current together with an increased drive capability. Due to its novel
concept, the circuit allows the implementation of complete off−line
AC−DC adapters, battery charger or a SMPS where standby power is a
key parameter.
With an internal structure operating at a fixed 40 kHz, 60 kHz or
100 kHz, the controller supplies itself from the high−voltage rail,
avoiding the need of an auxiliary winding. This feature naturally eases
the designer task in battery charger applications. Finally,
current−mode control provides an excellent audio−susceptibility and
inherent pulse−by−pulse control.
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the so−called
skip cycle mode and provides excellent efficiency at light loads.
Because this occurs at a user adjustable low peak current, no acoustic
noise takes place.
The NCP1200A features an efficient protective circuitry which, in
presence of an overcurrent condition, disables the output pulses while
the device enters a safe burst mode, trying to restart. Once the default
has gone, the device auto−recovers.
Features
• Pb−Free Packages are A vailable
• No Auxiliary Winding Operation
• Auto−Recovery Internal Output Short−Circuit Protection
• Extremely Low No−Load Standby Power
• Current−Mode Control with Skip−Cycle Capability
• Internal Temperature Shutdown
• Internal Leading Edge Blanking
• 250 mA Peak Current Capability
• Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz
• Direct Optocoupler Connection
• SPICE Models A vailable for TRANsient and AC Analysis
• Pin to Pin Compatible with NCP1200
T ypical Applications
• AC−DC Adapters for Portable Devices
• Offline Battery Chargers
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
http://onsemi.com
MINIATURE PWM
CONTROLLER FOR HIGH
POWER AC−DC W ALL
ADAPTERS AND OFFLINE
BATTERY CHARGERS
MARKING
DIAGRAMS
8
1
HV
8
NC
7
V
6
Drv
5
8
200Ay
ALYW
1
1200APxxx
CC
SOIC−8
8
1
8
1
xxx = Specific Device Code
y = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
Y, YY = Year
W, WW = Work Week
GND
D SUFFIX
CASE 751
PDIP−8
P SUFFIX
CASE 626
(40, 60 or 100)
(4 for 40, 6 for 60, 1 for 100)
PIN CONNECTIONS
Adj
1
FB
2
CS
3
4
(Top View)
AWL
YYWW
Semiconductor Components Industries, LLC, 2004
October, 2004− Rev. 5
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
1 Publication Order Number:
NCP1200A/D
NCP1200A
EMI
FILTER
UNIVERSAL
INPUT
*Please refer to the application information section
PIN FUNCTION DESCRIPTION
*
+
NCP1200A
Adj
FB
CS
GND
V
Drv
HV
CC
8
7
6
5
+
1
2
3
4
Figure 1. Typical Application Example
V
+
OUT
Pin No. Pin Name Function Pin Description
1 Adj Adjust the skipping peak current This pin lets you adjust the level at which the cycle skipping process takes
2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is
3 CS Current sense input This pin senses the primary current and routes it to the internal comparator
4 GND The IC ground −
5 Drv Driving pulses The driver’s output to an external MOSFET.
6 V
7 NC − This unconnected pin ensures adequate creepage distance.
8 HV Generates the VCC from the line Connected to the high−voltage rail, this pin injects a constant current into
CC
Supplies the IC This pin is connected to an external bulk capacitor of typically 10 F.
place. Shorting this pin to ground, permanently disables the skip cycle
feature.
adjusted accordingly to the output power demand.
via an L.E.B.
the V
bulk capacitor.
CC
http://onsemi.com
2
NCP1200A
Adj
FB
CURRENT
SENSE
GROUND
HV
1
8
HV CURRENT
SOURCE
80 k
1.2 V
2
SKIP CYCLE
COMPARATOR
+
−
INTERNAL V
UVLO HIGH AND LOW
INTERNAL REGULATOR
CC
NC
7
24 k
Q FLIP−FLOP
DCmax = 80%
3
250 ns
L.E.B.
40−60−100 kHz
CLOCK
20 k 57 k
V
4
REF
+
−
5 V
25 k
1 V
SET
RESET
+
−
OVERLOAD?
Q
±250 mA
V
6
Drv
5
CC
FAULT DURATION
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage V
Thermal Resistance Junction−to−Air, PDIP−8 Version
Thermal Resistance Junction−to−Air, SOIC Version
Maximum Junction Temperature T
CC
R
JA
R
JA
J(max)
Temperature Shutdown − 145 °C
Storage Temperature Range − −60 to +150 °C
ESD Capability, HBM Model (All pins except VCC and HV) − 2.0 kV
ESD Capability, Machine Model − 200 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Grounded − 450 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 F − 500 V
Minimum Operating Voltage on Pin 8 (HV) − 40 V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
16 V
100
178
°C/W
°C/W
150 °C
http://onsemi.com
3
NCP1200A
ELECTRICAL CHARACTERISTICS (For typical values T
V
= 11 V unless otherwise noted.)
CC
Characteristic
= 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
J
Symbol Pin Min Typ Max Unit
Dynamic Self−Supply (All frequency versions, otherwise noted)
V
Increasing Level at which the Current Source Turns−Off V
CC
VCC Decreasing Level at which the Current Source Turns−On V
VCC Decreasing Level at which the Latchoff Phase Ends V
CC(off)
CC(on)
CC(latch)
6 11.2 12.1 13.1 V
6 9.0 10 11 V
6 − 5.4 − V
Internal IC Consumption, No Output Load on Pin 5 ICC1 6 − 750 1000
(Note 1)
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
= 40 kHz ICC2 6 − 1.2 1.4
SW
(Note 2)
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
= 60 kHz ICC2 6 − 1.4 1.6
SW
(Note 2)
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
= 100 kHz ICC2 6 − 1.9 2.2
SW
(Note 2)
Internal IC Consumption, Latchoff Phase ICC3 6 − 350 − A
Internal Startup Current Source (TJ > 0°C, pin 8 biased at 50 V)
High−Voltage Current Source, V
= 10 V IC1 8 4.0 7.0 − mA
CC
High−Voltage Current Source, VCC = 0 IC2 8 − 13 − mA
Drive Output
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal T
Source Resistance R
Sink Resistance R
T
OH
OL
r
f
5 − 67 − ns
5 − 25 − ns
5 27 40 61
5 5.0 10 21
Current Comparator (Pin 5 unloaded unless otherwise noted)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint (Note 3) I
Default Internal Current Setpoint for Skip Cycle Operation I
Propagation Delay from Current Detection to Gate OFF State T
Leading Edge Blanking Duration (Note 3) T
I
IB
Limit
Lskip
DEL
LEB
3 − 0.02 − A
3 0.8 0.9 1.0 V
3 − 360 − mV
3 − 90 160 ns
3 − 250 − ns
Internal Oscillator (VCC = 11 V, pin 5 loaded by 1.0 k)
Oscillation Frequency, 40 kHz Version
Built−in Frequency Jittering, fsw = 40 kHz f
Oscillation Frequency, 60 kHz Version f
Built−in Frequency Jittering, fsw = 60 kHz f
Oscillation Frequency, 100 kHz Version f
Built−in Frequency Jittering, fsw = 100 kHz f
f
OSC
jitter
OSC
jitter
OSC
jitter
− 37 43 48 kHz
− − 350 − kHz
− 53 61 68 kHz
− − 460 − kHz
− 90 103 114 kHz
− − 620 − kHz
Maximum Duty Cycle Dmax − 74 83 87 %
Feedback Section (VCC = 11 V, pin 5 unloaded)
Internal Pullup Resistor
Pin 3 to Current Setpoint Division Ratio I
R
ratio
up
2 − 20 − k
− − 3.3 − −
Skip Cycle Generation
Default Skip Mode Level
Pin 1 Internal Output Impedance Z
1. Max value at T
2. Maximum value @ T
3. Pin 5 loaded by 1.0 nF.
= 0°C.
J
= 25°C, please see characterization curves.
J
V
skip
out
1 0.95 1.2 1.45 V
1 − 22 − k
A
mA
mA
mA
http://onsemi.com
4
NCP1200A
5
TYPICAL CHARACTERISTICS
70
60
50
40
30
LEAKAGE (A)
20
10
0
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 3. HV Pin Leakage Current vs. Temperature
10.2
10.1
10.0
, (V)
9.9
CC(on)
V
9.8
9.7
12.5
12.3
12.1
11.9
11.7
, THRESHOLD (V)
11.5
CC(off)
V
11.3
11.1
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 4. V
900
850
800
750
ICC1 (A)
700
40 kHz
650
vs. Temperature
CC(off)
100 kHz
60 kHz
9.6
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 5. V
2.10
1.90
1.70
1.50
ICC2 (mA)
1.30
1.10
0.90
−25 0 25 50 75 100 125
TEMPERATURE (°C)
vs. Temperature
CC(on)
100 kHz
60 kHz
40 kHz
Figure 7. ICC2 vs. Temperature
600
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 6. ICC1 vs. Temperature
110
104
98
92
86
80
(kHz)
74
SW
68
F
62
56
50
44
38
−25 0 25 50 75 100 12
100 kHz
60 kHz
40 kHz
TEMPERATURE (°C)
Figure 8. Switching Frequency vs. Temperature
http://onsemi.com
5
NCP1200A
5
TYPICAL CHARACTERISTICS
5.50
5.45
5.40
5.35
5.30
LATCHOFF
CC
V
5.25
5.20
5.15
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Latchoff vs. Temperature Figure 10. ICC3 vs. Temperature
CC
Source
Sink
60
50
40
30
Ohm
20
10
Figure 9. V
490
460
430
400
370
340
ICC3 (A)
310
280
250
220
190
−25 0 25 50 75 100 12
TEMPERATURE (°C)
1.00
0.96
0.92
0.88
0.84
CURRENT SETPOINT (V)
0
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 11. Drive and Source Resistance vs.
Temperature
1.40
1.35
1.30
1.25
(V)
1.20
SKIP
V
1.15
1.10
1.05
1.00
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 13. V
vs. Temperature
SKIP
0.80
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 12. Current Sense Limit vs. Temperature
87
85
83
81
79
DUTY MAX (%)
77
75
73
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 14. Max Duty Cycle vs. T emperature
http://onsemi.com
6
NCP1200A
APPLICATION INFORMATION
Introduction
The NCP1200A implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part−count is the key parameter,
particularly in low−cost AC−DC adapters, auxiliary
supplies, etc. Due to its high−performance High−Voltage
technology, the NCP1200A incorporates all the necessary
components normally needed in UC384X based supplies:
timing components, feedback devices, low−pass filter and
self−supply. This later point emphasizes the fact that
ON Semiconductor’s NCP1200A does NOT need an
auxiliary winding to operate: the product is naturally
supplied from the high−voltage rail and delivers a V
CC
to the
IC. This system is called the Dynamic Self−Supply (DSS).
Dynamic Self−Supply
The DSS principle is based on the charge/discharge of t h e
V
bulk capacitor from a low level up to a higher level. W e
CC
can easily describe the current source operation with a bunch
of simple logical equations:
POWER−ON: IF VCC < VCCH THEN Current Source is
ON, no output pulses
IF VCC decreasing > VCCL THEN Current Source is OFF,
output is pulsing
IF V
increasing < VCCH THEN Current Source is ON,
CC
output is pulsing
Typical values are: VCCH = 12 V, VCCL = 10 V
To better understand the operational principle, Figure 15’s
sketch offers the necessary light:
V
= 2 V
V
CC
Current
Source
ripple
ON
UVLO
= 12 V
H
UVLO
OUTPUT PULSES
= 10 V
L
OFF
The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg max equals
22 nC. With a maximum switching frequency of 68 kHz fo r
the P60 version, the average power necessary to drive the
MOSFET (excluding the driver efficiency and neglecting
various voltage drops) is:
F
⋅ Qg ⋅ V
SW
CC
with
FSW = maximum switching frequency
Qg = MOSFET’s gate charge
VCC = VGS level applied to the gate
To obtain the final IC current, simply divide this result by
VCC: I
= FSW ⋅ Qg = 1.5 mA. The total standby power
driver
consumption at no−load will therefore heavily rely on the
internal IC consumption plus the above driving current
(altered by the driver’s efficiency). Suppose that the IC is
supplied from a 350 VDC line. The current flowing through
pin 8 is a direct image of the NCP1200A consumption
(neglecting the switching losses of the HV current source).
If ICC2 equals 2.3 mA @ T
= 25°C, then the power
J
dissipated (lost) by the IC is simply: 350 x 2.3 m = 805 mW.
For design and reliability reasons, it would be interesting to
reduce this source of wasted power which increases the die
temperature. This can be achieved by using different
methods:
1. Use a MOSFET with lower gate charge Qg
2. Connect pin through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
V
becomes
MAINS(peak) 2
. Our power
contribution example drops to: 223 x 2.3 m = 512
mW. If a resistor is installed between the mains and
the diode, you further force the dissipation to
migrate from the package to the resistor. The
resistor value should account for low−line startups.
3. Permanently force the V
level above VCCH with
CC
an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully self−supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. Make sure the auxiliary
voltage never exceeds the 16 V limit.
10.0 M 30.0 M 50.0 M 70.0 M 90.0 M
Figure 15. The charge/discharge cycle over a
10 F V
capacitor
CC
http://onsemi.com
7
mains
NCP1200A
HV
Figure 16. A simple diode naturally reduces the average voltage on pin 8
Skipping Cycle Mode
The NCP1200A automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18).
Suppose we have the following component values:
Lp, primary inductance = 1 mH
F
, switching frequency = 61 kHz
SW
Ip skip = 200 mA (or 333 mV/R
SENSE
)
The theoretical power transfer is therefore:
1
Lp Ip2 FSW 1.2 W
2
If this IC enters skip cycle mode with a bunch length of
20 ms over a recurrent period of 100 ms, then the total
power transfer is: 1.2 . 0.2 = 240 mW.
Cbulk
1
2
3
4
8
7
6
5
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight:
FB
4.2 V, FB Pin Open
3.2 V, Upper
NORMAL CURRENT
MODE OPERATION
SKIP CYCLE OPERATION
I
= 333 mV/R
P(min)
SENSE
Figure 17.
Dynamic Range
1 V
When FB is above the skip cycle threshold (1 V by
default), the peak current cannot exceed 1 V/R
SENSE
. When
the IC enters the skip cycle mode, the peak current cannot go
below Vpin1 / 3.3. The user still has the flexibility to alter
this 1 V b y either shunting pin 1 to ground through a resistor
or raising it through a resistor up to the desired level.
Grounding pin 1 permanently invalidates the skip cycle
operation.
Figure 18. Output Pulses at Various Power Levels (X = 5.0 s/div) P1 P2 P3
http://onsemi.com
8
Power P1
Power P2
Power P3
NCP1200A
300 M
200 M
100 M
0
315.40 882.70 1.450 M 2.017 M 2.585 M
MAX PEAK
CURRENT
Figure 19. The Skip Cycle T akes Place at Low Peak Currents which Guaranties Noise−Free
Operation
We recommend a pin 1 operation between 400 mV and 1.3
V that will fix the skip peak current level between 120 mV
/ RSENSE and 390 mV / RSENSE.
Non−Latching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
SKIP CYCLE
CURRENT LIMIT
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 20 depicts the application example:
ON/OFF
Q1
1
2
3
4
8
7
6
5
Figure 20. Another Way of Shutting Down the IC without a Definitive Latchoff State
http://onsemi.com
9
NCP1200A
Power Dissipation
The NCP1200A is directly supplied from the DC rail
through the internal DSS circuitry. The average current
flowing through the DSS is therefore the direct image of the
NCP1200A current consumption. The total power
dissipation can be evaluated using: (V
− 11 V) ⋅ ICC2.
HVDC
If we operate the device on a 250 VAC rail, the maximum
rectified voltage can go up to 350 VDC. However, as the
characterization curves show, the current consumption
drops at high junction temperature, which quickly occurs
due to the DSS operation. At T
= 50°C, ICC2 = 1.7 mA for
J
the 61 kHz version over a 1 nF capacitive load. As a result,
the NCP1200A will dissipate 350 . 1.7 mA@T
= 50°C =
J
595 mW. The SOIC−8 package offers a
junction−to−ambient thermal resistance R
of 178°C/W.
JA
Adding some copper area around the PCB footprint will help
decreasing this number: 12 mm x 12 mm to drop R
down
JA
to 100°C/W with 35 copper thickness (1 oz.) or 6.5 mm x
6.5 mm with 70 copper thickness (2 oz.). With this later
number, we can compute the maximum power dissipation
the package accepts at an ambient of 50°C:
T
Pmax
Jmax TAmax
R
JA
750 mW
which is okay with
our previous budget. For the DIP8 package, adding a
min−pad area of 8 0 m m of 35 copper (1 oz.), R
JA
drops
from 100°C/W to about 75°C/W.
In the above calculations, ICC2 is based on a 1 nF output
capacitor. As seen before, ICC2 will depend on your
MOSFET’s Qg: ICC2 ≈ ICC1 + F
x Qg. Final calculation
SW
shall thus accounts for the total gate−charge Qg your
MOSFET will exhibit. The same methodology can be
applied for the 100 kHz version but care must be taken to
keep T
below the 125°C limit with the D100 (SOIC) version
J
and activated DSS in high−line conditions.
If the power estimation is beyond the limit, other solutions
are possible a) add a series diode with pin 8 (as suggested in
the above lines) and connect it to the half rectified wave. As
a result, it will drop the average input voltage and lower the
dissipation to:
350 2
1.7 m 380 mW
b) put an
auxiliary winding to disable the DSS and decrease the power
consumption to VCC x ICC2. The auxiliary level should be
thus that the rectified auxiliary voltage permanently stays
above 10 V (to not re−activate the DSS) and is safely kept
below the 16 V maximum rating.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short−circuit protection. A
short−circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken optocoupler. To account for this situation,
NCP1200A hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in a
burst manner with a low duty cycle. The system
auto−recovers when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time−out used by this IC
works with the V
decoupling capacitor: as soon as the
CC
VCC decreases from the UVLOH level (typically 12 V) the
device internally watches for an overload current situation.
If this condition is still present when the UVLOL level is
reached, the controller stops the driving pulses, prevents the
self−supply current source to restart and puts all the circuitry
in standby, consuming as little as 350 A typical (ICC3
parameter). As a result, the V
level slowly discharges
CC
toward 0.
http://onsemi.com
10
12 V
10 V
5.4 V
V
Drv
CC
NCP1200A
REGULATION
OCCURS
HERE
LATCHOFF
PHASE
TIME
DRIVER
PULSES
INTERNAL
FAULT FLAG
STARTUP PHASE
Figure 21. If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes.
If the fault still persists when V
reached UVLOL, then the controller cuts everything off until recovery.
CC
When this level crosses 5.4 V typical, the controller enters
a new startup phase by turning the current source on: V
rises toward 12 V and again delivers output pulses at the
UVLOH crossing point. If the fault condition has been
removed before UVLOL approaches, then the IC continues
its normal operation. Otherwise, a new fault cycle takes
place. Figure 21 shows the evolution of the signals in
FAULT OCCURS HERE
in either simulating or measuring in the lab how much time
CC
the system takes to reach the regulation at full load. Let’s
suppose that this time corresponds to 6 ms. Therefore a V
fall time of 10 ms could be well appropriated in order to not
trigger the overload detection circuitry. If the corresponding
IC consumption, including the MOSFET drive, establishes
at 1.8 mA for instance, we can calculate the required
presence of a fault.
capacitor using the following formula:
Calculating the VCC Capacitor
As the above section describes, the fall down sequence
depends upon the VCC level: how long does it take for the
V
line to go from 12 V to 10 V? The required time depends
CC
on the startup sequence of your system, i.e. when you first
apply the power to the IC. The corresponding transient fault
duration due to the output capacitor charging must be less
than the time needed to discharge from 12 V to 10 V,
V = 2 V. Then for a wanted t of 10 ms, C equals 9 F or
22 F for a standard value. When an overload condition
occurs, the IC blocks its internal circuitry and its
consumption drops to 350 A typical. This happens at
V
CC
are in latchoff phase. Again, using the calculated 22 F and
350 A current consumption, this latchoff phase lasts:
296 ms.
DRIVER
PULSES
TIME
FAULT IS
RELAXED
TIME
t
= 10 V and it remains stuck until VCC reaches 5.4 V : we
otherwise the supply will not properly start. The test consists
V C
i
CC
, with
http://onsemi.com
11
NCP1200A
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if they are a low impedance
path is offered between V
and GND. If the current sense
CC
pin is often the seat of such spurious signals, the
high−voltage pin can also be the source of problems in
certain circumstances. During the turn−off sequence, e.g.
when the user unplugs the power supply , the controller is still
fed by its V
capacitor and keeps activating the MOSFET
CC
ON and OFF with a peak current limited by Rsense.
Unfortunately , if the quality coefficient Q of the resonating
network formed by Lp and Cbulk is low (e.g. the MOSFET
Rdson + Rsense are small), conditions are met to make the
circuit resonate and thus negatively bias the controller . Since
we are talking about ms pulses, the amount of injected
charge (Q = I x t) immediately latches the controller which
brutally discharges its V
capacitor. If this VCC capacitor
CC
is of sufficient value, its stored energy damages the
controller. Figure 22 depicts a typical negative shot
occurring on the HV pin where the brutal V
discharge
CC
testifies for latchup.
Figure 22. A negative spike takes place on the Bulk capacitor at the switch−off sequence
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 23). Please note that the negative
spike is clamped to –2 x Vf due to the diode bridge. Please
refer to AND8069/D for power dissipation calculations.
3
Rbulk
> 4.7 k
2
+
Cbulk
Figure 23. A simple resistor in series avoids any
1
2
3
4
latchup in the controller
8
7
6
1
5
+
CV
CC
Another option (Figure 24) consists in wiring a diode from
V
to the bulk capacitor to force VCC to reach UVLOlow
CC
sooner and thus stops the switching activity before the bulk
capacitor gets deeply discharged. For security reasons, two
diodes can be connected in series.
3
+
Cbulk
Figure 24. or a diode forces VCC to reach
1
2
3
4
UVLOlow sooner
8
7
6
5
1
D3
1N4007
+
CV
CC
http://onsemi.com
12
NCP1200A
ORDERING INFORMATION
Device Type Marking Package Shipping
NCP1200AP40 1200AP40 PDIP−8 50 Units / Rail
NCP1200AP40G
NCP1200AD40R2 200A4 SOIC−8 2500 Units /Reel
NCP1200AP60 1200AP60 PDIP−8 50 Units / Rail
NCP1200AP60G
NCP1200AD60R2
NCP1200AD60R2G 200A6 SOIC−8
NCP1200AP100 1200AP100 PDIP−8 50 Units / Rail
NCP1200AP100G
NCP1200AD100R2
NCP1200AD100R2G 200A1 SOIC−8
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
FSW = 40 kHz
FSW = 60 kHz
FSW = 100 kHz
1200AP40 PDIP−8
(Pb−Free)
1200AP60 PDIP−8
(Pb−Free)
200A6 SOIC−8 2500 Units /Reel
(Pb−Free)
1200AP100 PDIP−8
(Pb−Free)
200A1 SOIC−8 2500 Units / Reel
(Pb−Free)
50 Units / Rail
50 Units / Rail
2500 Units /Reel
50 Units / Rail
2500 Units / Reel
†
http://onsemi.com
13
NCP1200A
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AC
−Y−
−Z−
−X−
A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
G
C
SEATING
PLANE
0.10 (0.004)
H
D
0.25 (0.010) Z
M
Y
SXS
N
X 45
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
INCHES
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
0.6
0.024
4.0
0.155
1.270
0.050
SCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
14
NOTE 2
−T−
SEATING
PLANE
H
58
−B−
14
F
−A−
C
N
D
G
0.13 (0.005) B
NCP1200A
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
L
J
K
M
M
A
T
M
M
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10 −−− 10
N 0.76 1.01 0.030 0.040
INCHESMILLIMETERS
http://onsemi.com
15
NCP1200A
The product described herein (NCP1200A), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357. There
may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NCP1200A/D
16
Loading...