ON Semiconductor NCP1060, NCP1063 User Manual

High-Voltage Switcher for Low Power Offline SMPS

NCP1060, NCP1063

The NCP106X products integrate a fixed frequency current mode controller with a 700 V MOSFET. Available in a PDIP−7, SOIC−10 or SOIC−16 package, the NCP106X offer a high level of integration, including soft−start, frequency−jittering, short−circuit protection, skip−cycle, adjustable peak current set point, ramp compensation, and a Dynamic Self−Supply (eliminating the need for an auxiliary winding).

Unlike other monolithic solutions, the NCP106X is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (60 kHz or 100 kHz). When the output power demand diminishes, the IC automatically enters frequency foldback mode and provides excellent efficiency at light loads. When the power demand reduces further, it enters into a skip mode to reduce the standby consumption down to a no load condition.

Protection features include: a timer to detect an overload or a short−circuit event, Overvoltage Protection with auto−recovery and AC input line voltage detection (A version).

The ON proprietary integrated Over Power Protection (OPP) lets you harness the maximum delivered power without affecting your standby performance simply via external resistors.

For improved standby performance, the connection of an auxiliary winding stops the DSS operation and helps to reduce input power consumption below 50 mW at high line.

NCP106x can be seamlessly used both in non−isolated and in isolated topologies.

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MARKING DIAGRAMS

PDIP−7

CASE 626A

AP SUFFIX

SOIC−16

CASE 751B−05

D SUFFIX

SOIC−10

CASE 751BQ

AD or BD SUFFIX

NCP1063fyyyG

P106xfyyy

AWL

YYWWG

AWLYWW

1060fyyy

ALYWX

Features

• Built−in 700 V MOSFET with R

of 34 W (NCP1060) and

DS(on)

11.4 W (NCP1063)

• Large Creepage Distance Between High−voltage Pins

• Current−Mode Fixed Frequency Operation – 60 kHz or 100 kHz

(130 kHz on demand)

• Adjustable Peak Current: see below table

• Fixed Ramp Compensation

• Direct Feedback Connection for Non−isolated Converter

• Internal and Adjustable Over Power Protection (OPP) Circuit

• Skip−Cycle Operation at Low Peak Currents Only

• Dynamic Self−Supply: No Need for an Auxiliary Winding

• Internal 4 ms Soft−Start

• Auto−Recovery Output Short Circuit Protection with Timer−Based

Detection

• Auto−Recovery Overvoltage Protection with Auxiliary Winding

Operation

• Frequency Jittering for Better EMI Signature

• No Load Input Consumption < 50 mW

• Frequency Foldback to Improve Efficiency at Light Load

• These Devices are Pb−Free and are RoHS Compliant

x = Power Switch Circuit

On−state Resistance

(0 = 34 W, 3 = 11.4 W) f = Brown In (A = Yes, B = No) yyy = Oscillator Frequency

(060 = 60 kHz, 100 = 100 kHz) A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information on page 28 of this data sheet.

Typical Applications

• Auxiliary / Standby Isolated and

Non−isolated Power Supplies

• Power Meter SMPS

• Wide Vin Low Power Industrial SMPS

March, 2021 − Rev. 10

1 Publication Order Number:

NCP1060/D

NCP1060, NCP1063

Table 1. PRODUCT INFORMATION & INDICATIVE MAXIMUM OUTPUT POWER

230 Vac + 15% 85 − 265 Vac

Product R

NCP1060 60 kHz

NCP1063 100 kHz

DS(on)

34 W

11.4 W

NOTE: Informative values only, with T

on minimum copper area as recommended.

= 25°C, T

amb

IPK(0)

300 mA 3.3 W 8.3 W 1.9 W 4.7 W

780 mA 6.2 W 15.5 W 3.3 W 7.8 W

= 100°C, PDIP−7 package, Self supply via Auxiliary winding and circuit mounted

case

Adapter Open Frame Adapter Open Frame

GND

VCC

LIM/OPP

PDIP−7

DRAIN

COMP

GND

GND GND

VCC

LIM/OPP

COMP

SOIC−16

DRAIN DRAIN

DRAIN DRAIN N.C. N.C. N.C. N.C.

GND

VCC

LIM/OPP

COMP

SOIC−10

Figure 1. Pin Connections

Table 2. PIN FUNCTION DESCRIPTION

Pin No

PDIP 7 SOIC 10 SOIC 16

1 1 1−4 GND The IC Ground

2 2 5 V

3 3 6 LIM/OPP Ipeak set / Over

4 4 7 FB Feedback signal

5 5 8 Comp Compensation The error amplifier output is available on this pin. The

6 9−12 This un−connected pin ensures adequate creepage dis-

7,8 6−10 13−16 Drain Drain connection The internal drain MOSFET connection

Pin Name Function Pin Description

Powers the internal

circuitry

This pin is connected to an external capacitor. The V includes an auto−recovery over voltage protection.

The current drown from the pin decreases Ipeak of the

power limitation

primary winding. If resistive divider from the auxiliary winding is connected to this pin it sets the OPP compensation level (it diminishes the peak current.)

This is the inverting input of the trans conductance error

input

amplifier. It is normally connected to the switching power supply output through a resistor divider.

network connected between this pin and ground adjusts the regulation loop bandwidth. Also, by connecting an opto−coupler to this pin, the peak current set point is adjusted accordingly to the output power demand.

tance

DRAIN DRAIN DRAIN DRAIN DRAIN

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Table 3. TYPICAL APPLICATIONS

NCP1060, NCP1063

• If the output voltage is above

9.0 V typ. (between Vcc(on) level and Vovp level) Vcc is supplied from output via D2

• If the output voltage is below 9.0 V, D2 is redundant, the IC is supplied from DSS

• R2 limits maximum output power (can be omitted if not required)

• Direct feedback, resistive divider formed by R3, R4 sets output voltage

• If the output voltage is above

9.0 V typ. (between Vcc(on) level and Vovp level) Vcc is supplied from output via D3

• If the output voltage is below

9.0 V, D3 and C5 are redundant, the IC is supplied from DSS

• R2 limits maximum output power (can be omitted if not required)

• Optocoupler feedback

Typical Non−isolated Application – Buck Converter

• If the output voltage is above

9.0 V typ. between V level and V supplied from output via D2

• R2 limits maximal output power

• Direct feedback, resistive divider formed by R3, R4 sets output voltage

• VCC supplied from DSS

• Output voltage is below 9.0 V

typ.

• LIM/OPP pin floating − no limit output power

• Direct feedback, resistive divider formed by R2, R3 sets output voltage

OVP

CC(ON)

level − VCC

Typical Non−isolated Application – Buck−Boost Converter

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Table 3. TYPICAL APPLICATIONS (continued)

NCP1060, NCP1063

• VCC supplied from DSS

• Output voltage is below 9.0 V

typ.

• LIM/OPP pin floating − no limit output power

• Resistive divider formed by R2, R3 sets output voltage

• If the output voltage is above

9.0 V typ. between V level and V supplied from output via D4

• LIM/OPP pin floating − no limit output power

• Resistive divider formed by R2, R3 sets output voltage

OVP

CC(ON)

level − VCC

Typical Non−isolated Application – Flyback Converter

Typical Isolated Application – Flyback Converter

• VCC supplied from auxiliary winding

• Resistive divider formed by R2, R3 sets output power limit and over power protection

• Optocoupler feedback, resistive divider formed by R6, R7 sets output voltage

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NCP1060, NCP1063

VCC

COMP(up)

COMP(REF )

DRAIN

ms Filter

80−

OVP

pflag

VCC OVP

SCP

recovery

Jittering

OSC

LineOK

Sawtooth

OFF

TSD

Foldback

VCC

Management

LineOK

UVLO

Sawtooth

COMPskip

SKIP

Ramp

SKIP = ”1”èShut down some

blocks to reduce consumption

compensation

UVLO Reset V

OFF UVLO

Line

Detection

LEB

GND

COMP

FB/COMP

Processing

COMPfault

to CS setpoint

COMP

LMOP (min)ILMOP (max )

LMDEC

pflag

FreezeIpk(0)

LMOP

PKL

LMOP

LIM/OPP

Figure 2. Simplified Internal Circuit Architecture

Reset

Soft−Start

Reset SS as recoving from

SCP, TSD, VCC OVP or UVLO

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NCP1060, NCP1063

Table 4. MAXIMUM RATING TABLE (All voltages related to GND terminal)

Rating

Power supply voltage, V

pin, continuous voltage V

Voltage on all pins, except Drain and VCC pin Vinmax −0.3 to 10 V

Drain voltage BVdss −0.3 to 700 V

Maximum Current into VCC pin I

Drain Current Peak during Transformer Saturation (TJ = 150°C, Note 2):

NCP1060 NCP1063

Drain Current Peak during Transformer Saturation (T

= 125°C, Note 2):

NCP1060 NCP1063

Drain Current Peak during Transformer Saturation (T

= 25°C, Note 2):

NCP1060 NCP1063

Thermal Resistance, Junction−to−Air – PDIP7 with 200 mm@ of 35−m copper area

Thermal Resistance, Junction−to−Air – SOIC10 with 200 mm@ of 35−m copper area

Thermal Resistance, Junction−to−Air – SOIC16 with 200 mm@ of 35−m copper area

Junction−to−Top Thermal Characterization Parameter – PDIP7

Junction−to−Top Thermal Characterization Parameter – SOIC10

Junction−to−Top Thermal Characterization Parameter – SOIC16

Junction Temperature Range T

Storage Temperature Range T

Human Body Model ESD Capability (All pins except HV pin) per JEDEC JESD22−A114F HBM 2 kV

Charged−Device Model ESD Capability per JEDEC JESD22−C101E CDM 1 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

2. Maximum drain current I on. Figure 3 below provides spike limits the device can tolerate.

is obtained when the transformer saturates. It should not be mixed with short pulses that can be seen at turn

DS(PK)

Symbol Value Unit

DS(PK)

−0.3 to 20 V

10 mA

mA 300 850

335 950

520

1500

stg

115 °C/W

132 °C/W

104 °C/W

7.3 °C/W

2.3 °C/W

2.5 °C/W

−40 to +150 °C

−60 to +150 °C

Figure 3. Spike Limits

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NCP1060, NCP1063

Table 5. ELECTRICAL CHARACTERISTICS

(For typical values T

Symbol

SUPPLY SECTION AND VCC MANAGEMENT

CC(on)

CC(min)

CC(off)

CC1

CCskip

POWER SWITCH CIRCUIT

DS(on)

DSS

DSS(off)

on(min)

INTERNAL START−UP CURRENT SOURCE

start1

start2

CCTH

start(min)

CURRENT COMPARATOR

IPK

IPK(0)

3. The final switch current is: I the primary inductor in a flyback, and t

4. Oscillator frequency is measured with disabled jittering.

= 25°C, for min/max values TJ = −40°C to +125°C, VCC = 14 V unless otherwise noted)

Rating Pin Min Typ Max Unit

VCC increasing level at which the switcher starts operation 2 (5) 8.4 9.0 9.5 V

VCC decreasing level at which the HV current source restarts 2 (5) 7.0 7.5 7.8 V

VCC decreasing level at which the switcher stops operation (UVLO) 2 (5) 6.7 7.0 7.2 V

Internal IC consumption, NCP1060 switching at 60 kHz, LIM/OPP = 0 A Internal IC consumption, NCP1060 switching at 100 kHz, LIM/OPP = 0 A Internal IC consumption, NCP1063 switching at 60 kHz, LIM/OPP = 0 A Internal IC consumption, NCP1063 switching at 100 kHz, LIM/OPP = 0 A

Internal IC consumption, COMP is 0 V (No switching on MOSFET) 2 (5) − 340 −

Power Switch Circuit on−state resistance NCP1060 (Id = 50 mA)

Tj = 25°C Tj = 125°C

NCP1063 (Id = 50 mA)

Tj = 25°C Tj = 125°C

Power Switch Circuit & Startup breakdown voltage

= 120 mA, Tj = 25°C)

(ID

(off)

Power Switch & Startup breakdown voltage off−state leakage current Tj = 125°C (Vds = 700 V)

Switching characteristics (RL = 50 W, VDS set for I

Turn−on time (90% − 10%) Turn−off time (10% − 90%)

Minimum on time

NCP1060 NCP1063

High−voltage current source, VCC = V

CC(on)

High−voltage current source, VCC = 0 V 7, 8

VCC Transient level for I

start1

to I

toggling point 2 (5) − 1.4 − V

start2

Minimum startup voltage, VCC = 0 V 7, 8

Maximum internal current setpoint at 50% duty cycle FB = 2 V, LIM/OPP = 0 mA, Tj = 25°C

NCP1060 NCP1063

Maximum internal current setpoint at beginning of switching cycle FB = 2 V, LIM/OPP pin open Tj = 25°C

NCP1060 NCP1063

/ (Vin/LP + Sa) x Vin/LP + Vin/L

IPK(0)

the propagation delay.

prop

2 (5) −

7, 8

(6−10)

(13−16)

7, 8

(6−10)

(13−16)

7, 8

(6−10)

(13−16)

= 0.7 x Ilim)

drain

7, 8

(6−10)

(13−16)

7, 8

(6−10)

(13−16)

– 200 mV 7, 8

(6−10)

(13−16)

(6−10)

(13−16)

(6−10)

(13−16)

−

x t

, with Sa the built−in slope compensation, Vin the input voltage,

prop

0.92

−

0.97

0.99

1.07

34 65

11.4 22

−

41 72

14.0 24

700 − − V

− 84 −

−

20 10

200 230

−

5 8 12 mA

− 0.5 − mA

21 V

−

250 650

−

268 702

300 780

332 858

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NCP1060, NCP1063

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(For typical values T

Symbol UnitMaxTypMinPinRating

CURRENT COMPARATOR

IPKSW

LMDEC

prop

LEB

INTERNAL OSCILLATOR

OSC

jitter

swing

max

ERROR AMPLIFIER SECTION

REF

OTAlim

OTAen

COMPENSATION SECTION

COMPfault

COMP100%

COMPfreeze

COMP(REF)

COMP(up)

LMOP

LMOP(min)

LMOP(max)

LMOP(neg)

3. The final switch current is: I LP the primary inductor in a flyback, and t

4. Oscillator frequency is measured with disabled jittering.

= 25°C, for min/max values TJ = −40°C to +125°C, VCC = 14 V unless otherwise noted)

Final switch current with a primary slope of 200 mA/ms, F

= 60 kHz (Note 3), LIM/OPP pin open

NCP1060 NCP1063

Final switch current with a primary slope of 200 mA/ms, F

= 100 kHz (Note 3), LIM/OPP pin open

NCP1060 NCP1063

Maximum internal current setpoint at beginning of switching cycle FB = 2 V, LIM/OPP = −285 mA, Tj = 25°C

NCP1060 NCP1063

Soft−start duration (guaranteed by design) − − 4 − ms

Propagation delay from current detection to drain OFF state − − 70 − ns

Leading Edge Blanking Duration

NCP1060 NCP1063

Oscillation frequency, 60 kHz version, Tj = 25°C (Note 4) − 54 60 66 kHz

Oscillation frequency, 100 kHz version, Tj = 25°C (Note 4) − 90 100 110 kHz

Frequency jittering in percentage of f

OSC

Jittering swing frequency − − 300 − Hz

Maximum duty−cycle − 62 66 72 %

Voltage Feedback Input (V

= 2.5 V) 4 (7) 3.2 3.3 3.4 V

COMP

Input Bias Current (VFB = 3.3 V) 4 (7) − 1 −

Transconductance 5 (8) 2 mS

OTA maximum current capability (VFB > V

OTAen

FB voltage to disable OTA 4 (7) 0.7 1.3 1.7 V

COMP current for which Fault is detected 5 (8) − −40 −

COMP current for which internal current set−point is 100% (I

COMP current for which internal current setpoint is: I

Freeze1 or 2

(NCP1060/3)

Equivalent pull−up voltage in linear regulation range (Guaranteed by design)

Equivalent feedback resistor in linear regulation range (Guaranteed by design)

Voltage on LIM/OPP pin @ I Voltage on LIM/OPP pin @ I

= −35 mA

LMOP

= −250 mA, Tj = 25°C

LMOP

Maximum current from LIM/OPP pin 3 (6) −330 −420

Current at which LIM/OPP starts to decrease I

Current at which LIM/OPP stops to decrease I

Negative Active Clamp Voltage (I

/ (Vin/LP + Sa) x Vin/LP + Vin/L

IPK(0)

LMOP

the propagation delay.

prop

PEAK

= −2.5 mA) 3 (6) −0.7 V

−

− − ±6 − %

) 5 (8) ±150

) 5 (8) − −44 −

IPK(0)

5 (8) − −80 −

5 (8) − 2.7 − V

5 (8) − 17.7 −

3 (6) 1.40

1.28

PEAK

3 (6) −20 −26 −32

3 (6) −285

x t

, with Sa the built−in slope compensation, Vin the input voltage,

prop

330 740

320 710

128 312

130 160

1.50

1.35

−

1.60

1.42

kΩ

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NCP1060, NCP1063

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(For typical values T

Symbol UnitMaxTypMinPinRating

COMPENSATION SECTION

LMOP(pos)

FREQUENCY FOLDBACK & SKIP

COMPfold

COMPfold(end)

min

COMPskip

Freeze1

Freeze2

RAMP COMPENSATION

a(60)

a(100)

PROTECTIONS

SCP

recovery

OVP

HV(EN)

TEMPERATURE MANAGEMENT

TSD

hyst

3. The final switch current is: I

the primary inductor in a flyback, and t

4. Oscillator frequency is measured with disabled jittering.

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

= 25°C, for min/max values TJ = −40°C to +125°C, VCC = 14 V unless otherwise noted)

Positive Active Clamp (Guaranteed by design) 3 (6) 2.5 mA

Start of frequency foldback COMP pin current level 5 (8) − −68 −

End of frequency foldback COMP pin current level, fsw = f

min

5 (8) − −100 −

The frequency below which skip−cycle occurs − 21 25 29 kHz

The COMP pin current level to enter skip mode 5 (8) − −120 −

Internal minimum current setpoint (I

COMP

= I

COMPFreeze

= I

COMPFreeze

) in NCP1060 − 110 − mA

) in NCP1063 − 270 − mA

The internal ramp compensation @ 60 kHz:

NCP1060 NCP1063

−

8.4

15.6

The internal ramp compensation @ 100 kHz:

NCP1060 NCP1063

−

14 26

−

mA/ms

Fault validation further to error flag assertion − 35 48 − ms

OFF phase in fault mode − − 400 − ms

VCC voltage at which the switcher stops pulsing 2 (5) 17.0 18.0 18.8 V

The filter of VCC OVP comparator − − 80 −

The drain pin voltage above which allows MOSFET operate, which is detected after TSD, UVLO, SCP, or V

OVP mode. (A version only)

7,8

(6−10)

(13−16)

67 87 110 V

Temperature shutdown (Guaranteed by design) − 150 163 − °C

Hysteresis in shutdown (Guaranteed by design) − − 20 − °C

/ (Vin/LP + Sa) x Vin/LP + Vin/L

IPK(0)

the propagation delay.

prop

x t

, with Sa the built−in slope compensation, Vin the input voltage,

prop

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NCP1060, NCP1063

TYPICAL CHARACTERISTICS

9.15

9.10

9.05

9.00

VOLTAGE (V)

8.95

8.90

8.85

7.00

6.98

6.96

6.94

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 4. V

7.52

7.50

7.48

7.46

7.44

7.42

7.40

VOLTAGE (V)

7.38

7.36

7.34

120 120

100806040200−20−40

vs. Temperature Figure 5. V

CC(on)

7.32

800

700

600

500

400

vs. Temperature

CC(min)

100806040200−20−40

VOLTAGE (V)

6.92

6.90

6.88

0.95

0.94

0.93

0.92

0.91

CURRENT (mA)

0.90

0.89

0.88

Figure 8. I

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 6. V

TEMPERATURE (°C) TEMPERATURE (°C)

CC1 60 kHz

300

CURRENT (mA)

200

100

120

100806040200−20−40

vs. Temperature Figure 7. I

CC(off)

100806040200−20−40

120 120

0.99

0.98

0.97

0.96

0.95

CURRENT (mA)

0.94

0.93

0.92

vs. Temperature Figure 9. I

DSS(off)

CC1 100 kHz

vs. Temperature

100806040200−20−40

120

100806040200−20−40

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