MC34151, MC33151
High Speed Dual
MOSFET Drivers
The MC34151/MC33151 are dual inverting high speed drivers
specifically designed for applications that require low current digital
circuitry to drive large capacitive loads with high slew rates. These
devices feature low input current making them CMOS and LSTTL
logic compatible, input hysteresis for fast output switching that is
independent of input transition time, and two high current totem pole
outputs ideally suited for driving power MOSFETs. Also included is
an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.
Typical applications include switching power supplies, dc to dc
converters, capacitor charge pump voltage doublers/inverters, and
motor controllers.
These devices are available in dual−in−line and surface mount
packages.
Features
• Pb−Free Packages are Available
• Two Independent Channels with 1.5 A Totem Pole Output
• Output Rise and Fall Times of 15 ns with 1000 pF Load
• CMOS/LSTTL Compatible Inputs with Hysteresis
• Undervoltage Lockout with Hysteresis
• Low Standby Current
• Efficient High Frequency Operation
• Enhanced System Performance with Common Switching Regulator
Control ICs
• Pin Out Equivalent to DS0026 and MMH0026
http://onsemi.com
MARKING
DIAGRAMS
8
PDIP−8
P SUFFIX
8
1
8
1
x = 3 or 4
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W= Work Week
CASE 626
SOIC−8
D SUFFIX
CASE 751
MC3x151P
AWL
YYWW
1
8
3x151
ALYW
1
PIN CONNECTIONS
8N.C.
1
N.C.
V
CC
6
+
+
−
+
+
Logic Input A
2
+
Logic Input B
4
5.7V
GND
Figure 1. Representative Block Diagram
Semiconductor Components Industries, LLC, 2004
July, 2004 − Rev. 4
7
Logic Input A
+
Drive Output A
7
100k
Logic Input B
2
3
GND
45
(Top View)
Drive Output A
6
V
CC
Drive Output B
ORDERING INFORMATION
+
Drive Output B
5
100k
3
1 Publication Order Number:
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
MC34151/D
MC34151, MC33151
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage V
Logic Inputs (Note 1) V
CC
in
Drive Outputs (Note 2)
Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to V
CC
)
I
O
I
O(clamp)
Power Dissipation and Thermal Characteristics
D Suffix SOIC−8 Package Case 751
Maximum Power Dissipation @ T
= 50°C
A
Thermal Resistance, Junction−to−Air
P
D
R
JA
P Suffix 8−Pin Package Case 626
Maximum Power Dissipation @ T
= 50°C
A
Thermal Resistance, Junction−to−Air
Operating Junction Temperature T
Operating Ambient Temperature
P
D
R
JA
J
T
A
MC34151
MC33151
MC33151V
Storage Temperature Range T
stg
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
20 V
−0.3 to V
CC
1.5
1.0
0.56
180
1.0
100
W
°C/W
W
°C/W
+150 °C
°C
0 to +70
−40 to +85
−40 to +125
−65 to +150 °C
V
A
ELECTRICAL CHARACTERISTICS (V
= 12 V, for typical values TA = 25°C, for min/max values TA is the only operating
CC
ambient temperature range that applies [Note 3], unless otherwise noted.)
Characteristics
Symbol Min Typ Max Unit
LOGIC INPUTS
Input Threshold Voltage − Output Transition High to Low State
Output Transition Low to High State
Input Current − High State (VIH = 2.6 V)
Input Current − Low State (V
= 0.8 V)
IL
V
IH
V
IL
I
IH
I
IL
−
0.8
−
−
DRIVE OUTPUT
Output Voltage − Low State (I
Output Voltage − Low State (I
Output Voltage − Low State (I
Output Voltage − High State (I
Output Voltage − High State(I
Output Voltage − High State(I
= 10 mA)
Sink
= 50 mA)
Sink
= 400 mA)
Sink
Source
Source
Source
= 10 mA)
= 50 mA)
= 400 mA)
Output Pulldown Resistor R
V
OL
−
−
−
V
OH
10.5
10.4
9.5
PD
− 100 − k
SWITCHING CHARACTERISTICS (TA = 25°C)
= 2.5 nF
L
= 2.5 nF
= 1.0 nF)
L
t
PLH(in/out)
t
PHL(in/out)
t
r
t
f
−
−
−
−
−
−
Propagation Delay (10% Input to 10% Output, C
Logic Input to Drive Output Rise
Logic Input to Drive Output Fall
Drive Output Rise Time (10% to 90%) CL = 1.0 nF
Drive Output Rise Time (10% to 90%) C
Drive Output Fall Time (90% to 10%) CL = 1.0 nF
Drive Output Fall Time (90% to 10%) C
L
TOTAL DEVICE
Power Supply Current
Standby (Logic Inputs Grounded)
Operating (C
= 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)
L
Operating Voltage V
I
CC
−
−
CC
6.5 − 18 V
1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less.
2. Maximum package power dissipation limits must be observed.
3. T
=0°C for MC34151 T
low
−40°C for MC33151 +85°C for MC33151
= +70°C for MC34151
high
1.75
2.6
1.58
20020500
100
0.8
1.2
1.1
1.5
1.7
2.5
11.2
11.1
10.9
3536100
100
14
30
31
16
30
32
6.0
10.51015
V
−
A
V
−
−
−
ns
ns
−
ns
−
mA
http://onsemi.com
2
Logic Input
MC34151, MC33151
12
V
4.7 0.1
+
6
+
+
−
+
5.7V
+
2
+
Drive Output
7
50 C
+
4
3
100k
+
5
100k
L
Logic Input
tr, t
≤ 10 ns
f
5.0 V
0 V
10%
t
PHL
90%
t
PLH
90%
Drive Output
t
10%
f
Figure 2. Switching Characteristics Test Circuit Figure 3. Switching Waveform Definitions
2.4
VCC = 12 V
T
= 25°C
2.0
A
1.6
1.2
0.8
, INPUT CURRENT (mA)
in
I
0.4
0
0 2.0 4.0 6.0 8.0 10 12 −55 −25 0 25 50 75 100 125
Vin, INPUT VOLTAGE (V)
Figure 4. Logic Input Current versus
Input Voltage
2.2
2.0
1.8
1.6
1.4
, INPUT THRESHOLD VOLTAGE (V)
1.2
th
V
1.0
VCC = 12 V
Upper Threshold
Low State Output
Lower Threshold
High State Output
T
, AMBIENT TEMPERATURE (°C)
A
Figure 5. Logic Input Threshold Voltage
versus Temperature
t
r
200
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
160
VCC = 12 V
CL = 1.0 nF
T
= 25°C
A
120
80
40
, DRIVE OUTPUT PROPAGATION DELAY (ns)
V
0
−1.6 −1.2 −0.8 −0.4 0 0 1.0 2.0 3.0 4.0
V
, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)
PLH(IN/OUT)
in
t
th(lower)
Figure 6. Drive Output Low−to−High Propagation
Delay versus Logic Overdrive Voltage
200
160
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
VCC = 12 V
CL = 1.0 nF
T
120
80
40
, DRIVE OUTPUT PROPAGATION DELAY (ns)
V
0
V
PHL(IN/OUT)
in
t
th(upper)
, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)
Figure 7. Drive Output High−to−Low Propagation
Delay versus Logic Input Overdrive Voltage
= 25°C
A
http://onsemi.com
3
MC34151, MC33151
90%
10%
Logic Input
Drive Output
VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
T
= 25°C
A
50 ns/DIV
Figure 8. Propagation Delay Figure 9. Drive Output Clamp Voltage
0
−1.0
V
CC
Source Saturation
(Load to Ground)
−2.0
−3.0
3.0
2.0
, OUTPUT SATURATION VOLTAGE(V)
1.0
sat
V
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Sink Saturation
(Load to V
CC
, OUTPUT LOAD CURRENT (A)
I
O
GND
)
VCC = 12 V
80 s Pulsed Load
120 Hz Rate
T
= 25°C
A
3.0
2.0
High State Clamp
(Drive Output Driven Above VCC)
VCC = 12 V
80 s Pulsed Load
120 Hz Rate
T
= 25°C
1.0
V
0
CC
, OUTPUT CLAMP VOLTAGE (V)
0
clamp
V
−1.0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
GND
, OUTPUT LOAD CURRENT (A)
I
O
(Drive Output Driven Below Ground)
A
Low State Clamp
versus Clamp Current
0
Source Saturation
−0.5
−0.7
−0.9
(Load to Ground)
V
CC
I
source
I
source
= 10 mA
= 400 mA
−1.1
1.9
1.7
I
= 400 mA
sink
1.5
1.0
, OUTPUT SATURATION VOLTAGE(V)
0.8
sat
V
Sink Saturation
0.6
(Load to V
0
−55 −25 0 25 50 75 100 125
CC
I
= 10 mA
sink
GND
)
T
, AMBIENT TEMPERATURE (°C)
A
VCC = 12 V
90%
10%
Figure 10. Drive Output Saturation Voltage
versus Load Current
Figure 11. Drive Output Saturation Voltage
versus Temperature
90%
VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
T
= 25°C
A
VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
T
10 ns/DIV
= 25°C
A
10%
10 ns/DIV
Figure 12. Drive Output Rise Time Figure 13. Drive Output Fall Time
http://onsemi.com
4
MC34151, MC33151
80
VCC = 12 V
VIN = 0 V to 5.0 V
60
T
= 25°C
A
40
t
20
f
−t , OUTPUT RISE-FALL TIME(ns)
r
t
0
0.1 1.0 10 0.1 1.0 10
CL, OUTPUT LOAD CAPACITANCE (nF)
f
t
r
Figure 14. Drive Output Rise and Fall Time
versus Load Capacitance
80
Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle
60
Both Drive Outputs Loaded
T
= 25°C
A
= 18 V, CL = 2.5 nF
1 − V
40
, SUPPLY CURRENT (mA)
20
CC
I
CC
2 − VCC = 12 V, CL = 2.5 nF
3 − V
= 18 V, CL = 1.0 nF
CC
4 − VCC = 12 V, CL = 1.0 nF
1
2
3
4
80
VCC = 12 V
Both Logic Inputs Driven
0 V to 5.0 V
60
50% Duty Cycle
Both Drive Outputs Loaded
T
= 25°C
A
40
, SUPPLY CURRENT (mA)
20
CC
I
0
f = 500 kHz
, OUTPUT LOAD CAPACITANCE (nF)
C
L
f = 200 kHz
f = 50 kHz
Figure 15. Supply Current versus Drive Output
Load Capacitance
8.0
T
= 25°C
A
6.0
4.0
, SUPPLY CURRENT (mA)
2.0
CC
I
Logic Inputs at V
Low State Drive Outputs
CC
Logic Inputs Grounded
High State Drive Outputs
0
10 k
100 1.0 M
f, INPUT FREQUENCY (Hz)
0
0 4.0 8.0 12 16
VCC, SUPPLY VOLTAGE (V)
Figure 16. Supply Current versus Input Frequency Figure 17. Supply Current versus Supply Voltage
APPLICATIONS INFORMATION
Description
The MC34151 is a dual inverting high speed driver
specifically designed to interface low current digital
circuitry with power MOSFET s. This device is constructed
with Schottky clamped Bipolar Analog technology which
offers a high degree of performance and ruggedness in
hostile industrial environments.
Output Stage
Each totem pole Drive Output is capable of sourcing and
sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 at
1.0 A. The low ‘on’ resistance allows high output currents
to be attained at a lower V
than with comparative CMOS
CC
drivers. Each output has a 100 k pulldown resistor to keep
the MOSFET gate low when VCC is less than 1.4 V. No over
current or thermal protection has been designed into the
Input Stage
The Logic Inputs have 170 mV of hysteresis with the input
threshold centered at 1.67 V. The input thresholds are
insensitive to V
making this device directly compatible
CC
with CMOS and LSTTL logic families over its entire
operating voltage range. Input hysteresis provides fast
output switching that is independent of the input signal
transition time, preventing output oscillations as the input
thresholds are crossed. The inputs are designed to accept a
signal amplitude ranging from ground to V
. This allows
CC
the output of one channel to directly drive the input of a
second channel for master−slave operation. Each input has
a 30 k pulldown resistor so that an unconnected open input
will cause the associated Drive Output to be in a known high
state.
device, so output shorting to V
or ground must be
CC
avoided.
Parasitic inductance in series with the load will cause the
driver outputs to ring above VCC during the turn−on
transition, and below ground during the turn−off transition.
With CMOS drivers, this mode of operation can cause a
destructive output latchup condition. The MC34151 is
immune to output latchup. The Drive Outputs contain an
internal diode to V
for clamping positive voltage
CC
transients. When operating with VCC at 18 V, proper power
supply bypassing must be observed to prevent the output
ringing from exceeding the maximum 20 V device rating.
Negative output transients are clamped by the internal NPN
pullup transistor. Since full supply voltage is applied across
http://onsemi.com
5
MC34151, MC33151
the NPN pullup during the negative output transient, power
dissipation at high frequencies can become excessive.
Figures 20, 21, and 22 show a method of using external
Schottky diode clamps to reduce driver power dissipation.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as V
rises from 1.4 V
CC
to the 5.8 V upper threshold. The lower UVLO threshold is
5.3 V, yielding about 500 mV of hysteresis.
Power Dissipation
Circuit performance and long term reliability are
enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the
junction temperature with the package in free air is:
where: T
TJ =TA + PD (R
= Junction Temperature
J
)
JA
TA = Ambient Temperature
PD = Power Dissipation
R
Thermal Resistance Junction to Ambient
JA =
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
P
D =PQ
+ PC + P
T
where: PQ = Quiescent Power Dissipation
P
= Capacitive Load Power Dissipation
C
PT = Transition Power Dissipation
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 17. The
device’s quiescent power dissipation is:
where: I
PQ = VCC I
= Supply Current with Low State Drive
CCL
(1−D) + I
CCL
CCH
(D)
Outputs
I
= Supply Current with High State Drive
CCH
Outputs
D = Output Duty Cycle
The capacitive load power dissipation is directly related
to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
P
=VCC (VOH − VOL) CL f
C
where: VOH = High State Drive Output Voltage
VOL = Low State Drive Output Voltage
CL = Load Capacitance
f = frequency
When driving a MOSFET, the calculation of capacitive
load power PC is somewhat complicated by the changing
gate to source capacitance CGS as the device switches. T o aid
in this calculation, power MOSFET manufacturers provide
gate charge information on their data sheets. Figure 18
shows a curve of gate voltage versus gate charge for the ON
Semiconductor MTM15N50. Note that there are three
distinct slopes to the curve representing different input
capacitance values. To completely switch the MOSFET
‘on’, the gate must be brought to 10 V with respect to the
source. The graph shows that a gate charge Q
of 110 nC is
g
required when operating the MOSFET with a drain to source
voltage VDS of 400 V.
16
MTM15N50
ID = 15 A
T
= 25°C
A
12
VDS = 100 V
8.0
4.0
, GATE−TO−SOURCE VOLTAGE (V)
GS
V
2.0 nF
0
0 40 80 120 160
Qg, GATE CHARGE (nC)
Figure 18. Gate−T o−Source Voltage
versus Gate Charge
8.9 nF
CGS =
VDS = 400 V
Q
g
V
GS
The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
P
C(MOSFET)
= VC Qg f
The flat region from 10 nC to 55 nC is caused by the
drain−to−gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34151 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating
the MC34151 at a higher V
, additional charge can be
CC
provided to bring the gate above 10 V. This will reduce the
‘on’ resistance of the MOSFET at the expense of higher
driver dissipation at a given operating frequency.
The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power
dissipation per driver is approximately:
PT = VCC (1.08 VCC CL f − 8 y 10−4)
P
must be greater than zero.
T
Switching time characterization of the MC34151 is
performed with fixed capacitive loads. Figure 14 shows that
for small capacitance loads, the switching speed is limited
by transistor turn−on/off time and the slew rate of the
internal nodes. For large capacitance loads, the switching
speed is limited by the maximum output current capability
of the integrated circuit.
http://onsemi.com
6
MC34151, MC33151
LAYOUT CONSIDERATIONS
High frequency printed circuit layout techniques are
imperative to p revent e xcessive o utput r inging a nd o vershoot.
Do not attempt to construct the driver circuit on
wire−wrap or plug−in prototype boards. When driving
large capacitive loads, the printed circuit board must c ontain
a low i nductance g round p lane t o m inimize t he v oltage s pikes
induced by the high ground ripple currents. All high current
loops should be kept as short as possible u s ing heavy copper
runs to provide a low impedance high frequency path. For
V
CC
0.1
47
6
TL494
or
TL594
+
++
−
+
5.7V
+
2
100k100k
+
+
4
V
in
7
5
optimum drive performance, it is recommended that the
initial circuit design contains dual power supply bypass
capacitors connected with short leads a s c lose t o t he V
CC
pin
and ground a s t he l ayout w ill p ermit. S uggested c apacitors a re
a low inductance 0.1 F ceramic in parallel with a 4.7 F
tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.
Proper printed circuit board layout is extremely
critical and cannot be over emphasized.
3
The MC34151 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.
Figure 19. Enhanced System Performance with
Common Switching Regulators
Series gate resistor Rg may be needed to damp high frequency parasitic
oscillations caused by the MOSFET input capacitance and any series
wiring inductance in the gate−source circuit. Rg will decrease the
MOSFET switching speed. Schottky diode D1 can reduce the driver’s
power dissipation due to excessive ringing, by preventing the output pin
from being driven below ground.
Figure 20. MOSFET Parasitic Oscillations
Output Schottky diodes are recommended when driving inductive loads at
high frequencies. The diodes reduce the driver’s power dissipation by
preventing the output pins from being driven above V
and below ground.
CC
Figure 21. Direct Transformer Drive Figure 22. Isolated MOSFET Drive
http://onsemi.com
7
MC34151, MC33151
V
in
I
B
+
+
R
g(on)
0
−
Base Charge
Removal
+
C
100k
R
g(off)
1
100k
In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET’s turn−on and
The totem−pole outputs can furnish negative base current for enhanced
transistor turn−off, with the addition of capacitor C1.
turn−off times.
Figure 23. Controlled MOSFET Drive Figure 24. Bipolar Transistor Drive
= 15 V
V
CC
4.7 0.1
+
6
V
in
+
+
−
+
5.7V
+
2
+
4
330pF
3
10k
The capacitor’s equivalent series resistance limits the Drive Output Current
to 1.5 A. An additional series resistor may be required when using tantalum or
other low ESR capacitors.
Figure 25. Dual Charge Pump Converter
+
100k
6.8 10
7
1N5819
+
+
47
+ V
≈ 2.0 V
O
CC
+
100k
5
6.8 10
1N5819
+
47
− V
≈ − V
O
CC
+
Output Load Regulation
IO (mA) +VO (V) −VO (V)
0 27.7 −13.3
1.0 27.4 −12.9
10 26.4 −11.9
20 25.5 −11.2
30 24.6 −10.5
50 22.6 −9.4
http://onsemi.com
8
MC34151, MC33151
ORDERING INFORMATION
Device Package Shipping
MC34151D SOIC−8 98 Units / Rail
MC34151DR2 SOIC−8 2500 Tape & Reel
MC34151DR2G SOIC−8
(Pb−Free)
MC34151P PDIP−8 50 Units / Rail
MC33151D SOIC−8 98 Units / Rail
MC33151DR2 SOIC−8 2500 Tape & Reel
MC33151DR2G SOIC−8
(Pb−Free)
MC33151P PDIP−8 50 Units / Rail
MC33151VDR2 SOIC−8 2500 Tape & Reel
MC33151VDR2G SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
2500 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
†
http://onsemi.com
9
NOTE 2
−T−
SEATING
PLANE
H
58
−B−
14
F
−A−
C
N
D
G
0.13 (0.005) B
MC34151, MC33151
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
L
J
K
M
M
A
T
M
M
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10 −−− 10
N 0.76 1.01 0.030 0.040
INCHESMILLIMETERS
http://onsemi.com
10
MC34151, MC33151
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AB
−Y−
−Z−
−X−
A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
G
C
SEATING
PLANE
0.10 (0.004)
H
D
0.25 (0.010) Z
M
Y
SXS
N
X 45
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
INCHES
1.52
0.060
*For
0.6
0.024
7.0
0.275
http://onsemi.com
4.0
0.155
1.270
0.050
mm
SCALE 6:1
inches
11
MC34151, MC33151
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MC34151/D
12
Loading...