ON Semiconductor MC34071, MC34072, MC34074, MC3407A, MC33071 Technical data

MC34071,2,4,A MC33071,2,4,A

High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers

Quality bipolar fabrication with innovative design concepts are employed for the MC33071/72/74, MC34071/72/74 series of monolithic operational amplifiers. This series of operational amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/µs slew rate and fast setting time without the use of JFET device technology. Although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage range includes ground potential (VEE). With A Darlington input stage, this series exhibits high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response.

The MC33071/72/74, MC34071/72/74 series of devices are available in standard or prime performance (A Suffix) grades and are specified over the commercial, industrial/vehicular or military temperature ranges. The complete series of single, dual and quad operational amplifiers are available in plastic DIP, SOIC and TSSOP surface mount packages.

• Wide Bandwidth: 4.5 MHz

• High Slew Rate: 13 V/µs

• Fast Settling Time: 1.1 µs to 0.1%

• Wide Single Supply Operation: 3.0 V to 44 V

• Wide Input Common Mode Voltage Range: Includes Ground (V

• Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)

• Large Output Voltage Swing: –14.7 V to +14 V (with ±15 V

Supplies)

• Large Capacitance Drive Capability: 0 pF to 10,000 pF

• Low Total Harmonic Distortion: 0.02%

• Excellent Phase Margin: 60°

• Excellent Gain Margin: 12 dB

• Output Short Circuit Protection

• ESD Diodes/Clamps Provide Input Protection for Dual and Quad

EE)

8

P SUFFIX

CASE 626

14

1

P SUFFIX

CASE 646

Output 1

Inputs 1

Inputs 2

Output 2

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8

1

SO–8 D SUFFIX CASE 751

PIN CONNECTIONS

Offset Null

Inputs

1 2

– +

3 4

V

EE

(Single, Top View)

1

Output 1 V

2

–

Inputs 1

3 4

V

EE

(Dual, Top View)

14

TSSOP–14

DTB SUFFIX

CASE 948G

+

1

8

NC

7

V

6

Output

5

Offset Null

8

CC

7

Output 2

6

– +

5

14

SO–14

D SUFFIX

CASE 751A

CC

Inputs 2

1

PIN CONNECTIONS

1

2

1

– +

3 4

V

CC

5

2

+ –

6

78

14

Output 4

13

4

–

Inputs 4

+

12 11

V

EE

3

10

+

Inputs 3

–

9

Output 3

 Semiconductor Components Industries, LLC, 1999

October, 1999 – Rev. 2

(Quad, T op View)

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet.

1 Publication Order Number:

MC34071/D

Inputs

MC34071,2,4,A MC33071,2,4,A

Representative Schematic Diagram

(Each Amplifier)

V

CC

Q2

Q3 Q4

R1

Q8

Q9

C1

R2

Q10

Q1

Bias

–

+

Q5

Q11

Q6

C2

Q7

D2

Q17

R6 R7

D3

Q18

Output

R8

Q19

Base

Current

Cancellation

Offset Null

(MC33071, MC34071 only)

Q13

Q12

D1

R3 R4

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage (from VEE to VCC) V Input Differential Voltage Range V Input Voltage Range V Output Short Circuit Duration (Note 2) t Operating Junction Temperature T Storage Temperature Range T

NOTES: 1.Either or both input voltages should not exceed the magnitude of VCC or VEE.

2.Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 1).

S

IDR

IR

SC

J

stg

+44 V Note 1 V Note 1 V

Indefinite sec

+150 °C

–60 to +150 °C

Q14

Q15 Q16

R5

Current

Limit

VEE/Gnd

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MC34071,2,4,A MC33071,2,4,A

ELECTRICAL CHARACTERISTICS (V

TA = T

Input Offset Voltage (RS = 100 Ω, VCM = 0 V, VO = 0 V)

Average Temperature Coefficient of Input Offset Voltage

Input Bias Current (VCM = 0 V, VO = 0 V)

Input Offset Current (VCM = 0 V, VO = 0V)

Input Common Mode Voltage Range

Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kΩ)

Output Voltage Swing (VID = ±1.0 V)

Output Short Circuit Current (VID = 1.0 V, VO = 0 V,

Common Mode Rejection

Power Supply Rejection (RS = 100 Ω)

Power Supply Current (Per Amplifier, No Load)

NOTES: 3.T

to T

low

VCC = +15 V, VEE = –15 V, TA = +25°C VCC = +5.0 V, VEE = 0 V, TA = +25°C VCC = +15 V, VEE = –15 V, TA = T

RS = 10 Ω, VCM = 0 V, VO = 0 V,

TA = T

TA = +25°C TA = T

low

TA = +25°C TA = T

low

TA = +25°C TA = T

low

TA = +25°C TA = T

low

VCC = +5.0 V, VEE = 0 V, RL = 2.0 kΩ, TA = +25°C VCC = +15 V, VEE = –15 V, RL = 10 kΩ, TA = +25°C VCC = +15 V, VEE = –15 V, RL = 2.0 kΩ,

TA = T

VCC = +5.0 V, VEE = 0 V, RL = 2.0 kΩ, TA = +25°C VCC = +15 V, VEE = –15 V, RL = 10 kΩ, TA = +25°C VCC = +15 V, VEE = –15 V, RL = 2.0 kΩ,

TA = T

TA = 25°C)

Source Sink

RS ≤ 10 kΩ, VCM = V

VCC/VEE = +16.5 V/–16.5 V to +13.5 V/–13.5 V ,

TA = 25°C

VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25°C VCC = +15 V, VEE = –15 V, VO = 0 V, TA = +25°C VCC = +15 V, VEE = –15 V, VO = 0 V,

TA = T

low

)

high

Characteristics Symbol Min Typ Max Min Typ Max Unit

low

to T

low

high

to T

high

to T

high

to T

high

to T

high

to T

low

high

to T

low

high

, TA = 25°C

ICR

to T

low

high

= –40°C for MC33071, 2, 4, /A T =0°C for MC34071, 2, 4, /A = +70°C for MC34071, 2, 4, /A

= +15 V , VEE = –15 V , RL = connected to ground, unless otherwise noted. See Note 3 for

CC

to T

high

A Suffix Non–Suffix

V

IO

∆VIO/∆T — 10 — — 10 — µV/°C

I

IB

I

IO

V

ICR

A

VOL

V

OH

V

OL

I

SC

CMR 80 97 — 70 97 — dB

PSR 80 97 — 70 97 — dB

I

D

= +85°C for MC33071, 2, 4, /A

high

— —

—

— —

50 25

3.7

13.6

13.4

— — —

10 20

— — —

0.5

0.5 —

100

—

6.0 —

VEE to (VCC –1.8) VEE to (VCC –2.2)

100

—

4.0 14 —

0.1

–14.7

—

30 30

1.6

1.9 —

3.0

5.0

500 700

50

300

— —

— — —

0.3 –14.3 –13.5

— —

2.0

2.5

2.8

— — —

— —

25 20

3.7

13.6

13.4

— — —

10 20

— — —

1.0

1.5 —

100

—

6.0 —

VEE to (VCC –1.8) VEE to (VCC –2.2)

100

—

4.0 14 —

0.1

–14.7

—

30 30

1.6

1.9 —

5.0

7.0

500 700

75

300

— —

— — —

0.3 –14.3 –13.5

— —

2.0

2.5

2.8

mV

nA

V

V/mV

V

mA

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MC34071,2,4,A MC33071,2,4,A

AC ELECTRICAL CHARACTERISTICS (V

Characteristics Symbol Min Typ Max Min Typ Max Unit

Slew Rate (Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 500 pF)

AV = +1.0 AV = –1.0

Setting Time (10 V Step, AV = –1.0)

To 0.1% (+1/2 LSB of 9–Bits)

To 0.01% (+1/2 LSB of 12–Bits) Gain Bandwidth Product (f = 100 kHz) GBW 3.5 4.5 — 3.5 4.5 — MHz Power Bandwidth

AV = +1.0, RL = 2.0 kΩ, VO = 20 Vpp, THD = 5.0% Phase margin

RL = 2.0 kΩ

RL = 2.0 kΩ, CL = 300 pF Gain Margin

RL = 2.0 kΩ

RL = 2.0 kΩ, CL = 300 pF Equivalent Input Noise Voltage

RS = 100 Ω, f = 1.0 kHz Equivalent Input Noise Current

f = 1.0 kHz Differential Input Resistance

VCM = 0 V Differential Input Capacitance

VCM = 0 V Total Harmonic Distortion

AV = +10, RL = 2.0 kΩ, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz Channel Separation (f = 10 kHz) — — 120 — — 120 — dB Open Loop Output Impedance (f = 1.0 MHz) |ZO| — 30 — — 30 — W

= +15 V, VEE = –15 V, RL = connected to ground. TA = +25°C, unless otherwise noted.)

CC

A Suffix Non–Suffix

SR

t

s

BW — 160 — — 160 — kHz

f

m

A

m

e

n

i

n

R

in

C

in

THD — 0.02 — — 0.02 — %

8.0 —

— —

— 32 — — 32 —

— 0.22 — — 0.22 —

— 150 — — 150 — MΩ

— 2.5 — — 2.5 — pF

10 13

1.1

2.2

60 40

12

4.0

— —

8.0 —

— —

10 13

1.1

2.2

60 40

12

4.0

— —

V/µs

nV/ Hz√

pA/ Hz√

µs

Deg

dB

Figure 1. Power Supply Configurations Figure 2. Offset Null Circuit

V

Single Supply Split Supplies

3.0 V to 44 V VCC+|VEE|≤44 V

V

CC

1

2

3

4

V

EE

V

CC

V

EE

V

1

2

3

4

V

CC

Offset nulling range is approximately ±80 mV with a 10 k potentiometer (MC33071, MC34071 only).

EE

CC

7

2

–

3

+

4

V

EE

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4

6

5

1

10 k

MC34071,2,4,A MC33071,2,4,A

5

Figure 3. Maximum Power Dissipation versus

T emperature for Package Types

2400

2000

1600

1200

D

P , MAXIMUM POWER DISSIPATION (mW)

SO–14 Pkg

800

400

0

–55 –40 –20 0 20 40 60 80 100 120 140 160

8 & 14 Pin Plastic Pkg

SO–8 Pkg

TA, AMBIENT TEMPERATURE (°C)

Figure 5. Input Common Mode V oltage

Range versus T emperature

V

CC

V

VCC/VEE = +1.5 V/ –1.5 V to +22 V/ –22 V

CC

VCC –0.8

VCC –1.6

VCC –2.4

Figure 4. Input Offset Voltage versus

T emperature for Representative Units

4.0

2.0

0

–2.0

IO

V

–4.0

V , INPUT OFFSET VOLTAGE (mV)

–55 –25 0 25 50 75 100 12

TA, AMBIENT TEMPERATURE (°C)

Figure 6. Normalized Input Bias Current

versus T emperature

1.3

1.2

1.1

1.0

0.9

VCC = +15 V VEE = –15 V VCM = 0

VEE +0.01

V

EE

–55 –25 0 25 50 75 100 125

1.4

1.2

1.0

0.8

IB

I , INPUT BIAS CURRENT (NORMALIZED)

0.6

V

EE

TA, AMBIENT TEMPERATURE (°C)

Figure 7. Normalized Input Bias Current versus

Input Common Mode Voltage

VCC = +15 V VEE = –15 V TA = 25°C

–12 –8.0 –4.0 0 4.0 8.0 12

VIC, INPUT COMMON MODE VOLTAGE (V)

0.8

IB

I , INPUT BIAS CURRENT (NORMALIZED)

0.7 –55 –25 0 25 50 75 100 125

ICR

V , INPUT COMMON MODE VOLTAGE RANGE (V)

TA, AMBIENT TEMPERATURE (°C)

Figure 8. Split Supply Output Voltage

Swing versus Supply V oltage

50

)

, OUTPUT VOLTAGE SWING (V V

RL Connected to Ground TA = 25°C

pp

40

30

20

10

O

0

0 5.0 10 15 20 25

RL = 10 k

VCC, |VEE|, SUPPLY VOLTAGE (V)

RL = 2.0 k

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MC34071,2,4,A MC33071,2,4,A

Figure 9. Single Supply Output Saturation

versus Load Resistance to V

V

VCC –1.0

VCC –2.0

VEE +2.0

VEE +1.0

sat

V , OUTPUT SATURATION VOLTAGE (V)

CC

V

EE

0 5.0 10 15 20

VCC/VEE = +5.0 V/ –5.0 V to +22 V/ –22 V TA = 25°C

CC

Source

Sink

V

EE

IL, LOAD CURRENT (±mA)

Figure 11. Single Supply Output Saturation

versus Load Resistance to Ground

0

V

–0.4

–0.8

2.0

1.0

sat

V , OUTPUT SATURATION VOLTAGE (V)

100 1.0 k 10 k 100 k

CC

VCC = +15 V RL to V TA = 25°C

Gnd

RL, LOAD RESISTANCE TO VCC (Ω)

CC

Figure 10. Split Supply Output Saturation

versus Load Current

V

CC

VCC–2.0

VCC–4.0

0.2

0.1

sat

V , OUTPUT SATURATION VOLTAGE (V)

0

100 1.0 k 10 k 100 k

RL, LOAD RESISTANCE TO GROUND (Ω)

Gnd

V

CC

Figure 12. Output Short Circuit Current

versus T emperature

60

50

40

30

20

SC

10

I , OUTPUT CURRENT (mA)

0

–55 –25 0 25 50 75 100 125

Source

TA, AMBIENT TEMPERATURE (°C)

Sink

VCC = +15 V VEE = –15 V RL ≤ 0.1 Ω ∆Vin = 1.0 V

VCC = +15 V RL = Gnd TA = 25°C

Figure 13. Output Impedance

versus Frequency

50

VCC = +15 V VEE = –15 V

40

VCM = 0 VO = 0 ∆IO = ±0.5 mA

30

TA = 25°C

20

AV = 1000

10

O

Z , OUTPUT IMPEDANCE ( )Ω

0

1.0 k 10 k 100 1.0 M 10 M

AV = 100 AV = 10 AV = 1.0

f, FREQUENCY (Hz)

28

)

24

pp

20 16 12

8.0

4.0

, OUTPUT VOLTAGE SWING (V

O

V

0

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6

Figure 14. Output Voltage Swing

versus Frequency

VCC = +15 V VEE = –15 V AV = +1.0 RL = 2.0 k THD ≤ 1.0% TA = 25°C

3.0 k 10 k 30 k 100 k 300 k 1.0 M 3.0 M f, FREQUENCY (Hz)

MC34071,2,4,A MC33071,2,4,A

5

A,

O

E

LOO

OL

AGE

GAI

(

B)

,

O

AL

AR

O

IC

IS

OR

IO

(

)

A,

O

E

LOO

OL

AGE

GAI

(

B)

Figure 15. T otal Harmonic Distortion

versus Frequency

0.4

% N

T

0.3

T D

N

0.2

M H

0.1

T T

THD

0

10 100 1.0 k 10 k 100 k

AV = 1000

AV = 100

AV = 10

f, FREQUENCY (Hz)

VCC = +15 V VEE = –15 V VO = 2.0 V RL = 2.0 k TA = 25°C

AV = 1.0

Figure 17. Open Loop Voltage Gain

versus T emperature

116

d N

T P V

N P

VCC = +15 V

112

VEE = –15 V VO= –10 V to +10 V RL = 10 k

108

f ≤ 10Hz

104

100

VOL

96

–55 –25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

Figure 16. T otal Harmonic Distortion

versus Output Voltage Swing

4.0 VCC = +15 V

VEE = –15 V

3.0

AV = 1000

pp

2.0

AV = 100

1.0

THD, TOTAL HARMONIC DISTORTION (%)

0

AV = 10 AV = 1.0

0 4.0 8.0 12 16 20

VO, OUTPUT VOLTAGE SWING (Vpp)

RL = 2.0 k TA = 25°C

Figure 18. Open Loop Voltage Gain and

Phase versus Frequency

100

0

80

Phase

60

40

VCC = +15 V VEE = –15 V

20

VO = 0 V RL = 2.0 k

VOL

TA = 25°C

A , OPEN LOOP VOLTAGE GAIN (dB)

0

1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M

Gain

f, FREQUENCY (Hz)

Phase Margin

= 60°

45

90

135

, EXCESS PHASE (DEGREES)

φ

180

Figure 19. Open Loop Voltage Gain and

Phase versus Frequency

20

d N

10

0

T

–10

P V

1. Phase RL = 2.0 k

2. Phase RL = 2.0 k, CL = 300 pF

N

–20

3. Gain RL = 2.0 k

P

4. Gain RL = 2.0 k, CL = 300 pF VCC = +15 V

–30

VEE = 15 V

VOL

VO = 0 V TA = 25°C

–40

1.0 2.0 3.0 5.0 7.0 10 20 30

1

Phase Margin = 60°

f, FREQUENCY (MHz)

Gain Margin = 12 dB

2

100

120

140

160

3

180

4

, EXCESS PHASE (DEGREES)

φ

GBW, GAIN BANDWIDTH PRODUCT (NORMALIED)

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7

Figure 20. Normalized Gain Bandwidth

Product versus T emperature

1.15

1.1

1.05

1.0

0.95

0.9

0.85 –55 –25 0 25 50 75 100 12

TA, AMBIENT TEMPERATURE (°C)

VCC = +15 V VEE = –15 V RL = 2.0 k

MC34071,2,4,A MC33071,2,4,A

Figure 21. Percent Overshoot versus

Load Capacitance

100

VCC = +15 V VEE = –15 V

80

RL = 2.0 k VO = –10 V to +10 V TA = 25°C

60

40

PERCENT OVERSHOOT

20

0

10 100 1.0 k 10 k

CL, LOAD CAPACITANCE (pF)

70 60

50 40 30 20

, PHASE MARGIN (DEGREES)φ

m

10

0

Figure 22. Phase Margin versus

Load Capacitance

VCC = +15 V VEE = –15 V AV = +1.0 RL = 2.0 k to VO = –10 V to +10 V TA = 25°C

10 100 1.0 k 10 k

CL, LOAD CAPACITANCE (pF)

Figure 23. Gain Margin versus Load Capacitance Figure 24. Phase Margin versus Temperature

14 12

10

8.0

6.0

m

4.0

A , GAIN MARGIN (dB)

2.0

VCC = +15 V VEE = –15 V AV = +1.0 RL = 2.0 k to ∞ VO = –10 V to +10 V TA = 25°C

80

CL = 10 pF

60

40

20

, PHASE MARGIN (DEGREES)φ

m

CL = 100 pF

CL = 1,000 pF

CL = 10,000 pF

VCC = +15 V VEE = –15 V AV = +1.0 RL = 2.0 k to VO = –10 V to +10 V

R

∞

0

10 100 1.0 k 10 k

CL, LOAD CAPACITANCE (pF)

Figure 25. Gain Margin versus T emperature

16

VCC = +15 V

12

VEE = –15 V AV = +1.0 RL = 2.0 k to ∞ VO = –10 V to +10 V

8.0

m

4.0

A , GAIN MARGIN (dB)

0

–55 –25 0 25 50 75 100

CL = 1,000 pF

TA, AMBIENT TEMPERATURE (°C)

CL = 10 pF

CL = 100 pF

CL = 10,000 pF

125

0

–55 –25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

Figure 26. Phase Margin and Gain Margin

versus Differential Source Resistance

12 10

8.0

6.0

4.0

2.0

m

A , GAIN MARGIN (dB)

R

1

V

O

– +

R

2

VCC = +15 V VEE = –15 V RT = R1 + R AV = +100

0

VO = 0 V TA = 25°C

1.0 100 1.0 k 10 k10 100 k

2

RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)

Gain

Phase

70 60 50 40 30 20

, PHASE MARGIN (DEGREES)φ

m

10 0

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SR,

SLE

RA

E

(

OR

ALI

E

)

C

R,

CO

O

E

RE

EC

IO

(

B)

MC34071,2,4,A MC33071,2,4,A

Figure 27. Normalized Slew Rate

versus T emperature

1.15

D Z

M N

T W

1.1

1.05

1.0

0.95

VCC = +15 V VEE = –15 V AV = +1.0 RL = 2.0 k CL = 500 pF

0.9

0.85 –55 –25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

10

5.0

0

–5.0

O

V , OUTPUT VOLTAGE SWING FROM 0 V (V)

–10

∆

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Figure 29. Small Signal Transient Response Figure 30. Large Signal Transient Reponse

Figure 28. Output Settling Time

10 mV

1.0 mV

ts, SETTLING TIME (µs)

VCC = +15 V VEE = –15 V AV = –1.0 TA = 25°C

Compensated

Uncompensated

0

50 mV/DIV

VCC = +15 V VEE = –15 V AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25°C

2.0 µs/DIV

Figure 31. Common Mode Rejection

versus Frequency

100 d N

T J

TA = 25°C

80

TA = –55°C

60

D N M

40

∆V

MM

M

20

CM

CMR = 20 Log

0

0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M

TA = 125°C

– A

DM

+

∆V

CM

∆V

x A

O

f, FREQUENCY (Hz)

VCC = +15 V VEE = –15 V VCM = 0 V ∆VCM = ±1.5 V

O

DM

VCC = +15 V VEE = –15 V AV = +1.0 RL = 2.0 k CL = 300 pF

0

TA = 25°C

5.0 V/DIV

1.0 µs/DIV

Figure 32. Power Supply Rejection

versus Frequency

100

80

∆V

CC

60

40

20

PSR, POWER SUPPLY REJECTION (dB)

0

–

A

DM

+

+PSR = 20 Log

–PSR = 20 Log

∆V

O

EE

∆VO/A

DM

∆V

CC

∆VO/A

DM

∆V

EE

0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M f, FREQUENCY (Hz)

VCC = +15 V VEE = –15 V TA = 25°C

(∆VCC = +1.5 V)

–PSR

(∆VEE = +1.5 V)

+PSR

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9

MC34071,2,4,A MC33071,2,4,A

Figure 33. Supply Current versus

Supply V oltage

9.0

8.0

7.0

6.0

CC

5.0

I , SUPPLY CURRENT (mA)

4.0 0 5.0 10 15 20 25

TA = –55°C

TA = 25°C

TA = 125°C

VCC, |VEE|, SUPPLY VOLTAGE (V)

105

95

85

75

PSR, POWER SUPPLY REJECTION (dB)

65

–55 –25 0 25 50 75 100 125

Figure 34. Power Supply Rejection

versus T emperature

(∆VEE = +1.5 V)

–PSR

(∆VCC = +1.5 V)

+PSR

∆VO/A

+PSR = 20 Log

–PSR = 20 Log

TA, AMBIENT TEMPERATURE (°C)

∆V

∆VO/A

∆V

DM

CC

DM

EE

Figure 35. Channel Separation versus Frequency Figure 36. Input Noise versus Frequency

120

VCC = +15 V

100

VEE = –15 V TA = 25°C

80

60

40

CHANNEL SEPARATION (dB)

20

0

10 20 30 50 70 100 200 300

f, FREQUENCY (kHz)

70

Hz )

60

√

nV

50 40 30 20 10

n

e , INPUT NOICE VOLTAGE (

0

10 100 1.0 k 10 k 100 k

Voltage

Current

f, FREQUENCY (kHz)

VCC = +15 V VEE = –15 V VCM = 0 TA = 25°C

VCC = +15 V VEE = –15 V

∆V

–

A

DM

+

∆V

CC

EE

∆V

2.8

2.4

2.0

1.6

1.2

0.8

0.4 0

O

Hz

√

n

i , INPUT NOISE CURRENT (pA )

APPLICATIONS INFORMATION

CIRCUIT DESCRIPTION/PERFORMANCE FEA TURES

Although the bandwidth, slew rate, and settling time of the MC34071 amplifier series are similar to op amp products utilizing JFET input devices, these amplifiers offer other additional distinct advantages as a result of the PNP transistor differential input stage and an all NPN transistor output stage.

Since the input common mode voltage range of this input stage includes the VEE potential, single supply operation is feasible to as low as 3.0 V with the common mode input voltage at ground potential.

The input stage also allows differential input voltages up to ±44 V, provided the maximum input voltage range is not exceeded. Specifically, the input voltages must range between VEE and VCC supply voltages as shown by the maximum rating table. In practice, although not recommended, the input voltages can exceed the V voltage by approximately 3.0 V and decrease below the V

CC

EE

voltage by 0.3 V without causing product damage, although output phase reversal may occur. It is also possible to source

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up to approximately 5.0 mA of current from VEE through either inputs clamping diode without damage or latching, although phase reversal may again occur.

If one or both inputs exceed the upper common mode voltage limit, the amplifier output is readily predictable and may be in a low or high state depending on the existing input bias conditions.

Since the input capacitance associated with the small geometry input device is substantially lower (2.5 pF) than the typical JFET input gate capacitance (5.0 pF), better frequency response for a given input source resistance can be achieved using the MC34071 series of amplifiers. This performance feature becomes evident, for example, in fast settling D–to–A current to voltage conversion applications where the feedback resistance can form an input pole with the input capacitance of the op amp. This input pole creates a 2nd order system with the single pole op amp and is therefore detrimental to its settling time. In this context, lower input capacitance is desirable especially for higher

10

MC34071,2,4,A MC33071,2,4,A

values of feedback resistances (lower current DACs). This input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. For 2.0 kΩ of feedback resistance, the MC34071 series can settle to within 1/2 LSB of 8 bits in 1.0 µs, and within 1/2 LSB of 12–bits in 2.2 µs for a 10 V step. In a inverting unity gain fast settling configuration, the symmetrical slew rate is ±13 V/µs. In the classic noninverting unity gain configuration, the output positive slew rate is +10 V/µs, and the corresponding negative slew rate will exceed the positive slew rate as a function of the fall time of the input waveform.

Since the bipolar input device matching characteristics are superior to that of JFETs, a low untrimmed maximum offset voltage of 3.0 mV prime and 5.0 mV downgrade can be economically offered with high frequency performance characteristics. This combination is ideal for low cost precision, high speed quad op amp applications.

The all NPN output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. A 10 kΩ load resistance can swing within 1.0 V of the positive rail (VCC), and within 0.3 V of the negative rail (VEE), providing a 28.7 Vpp swing from ±15 V supplies. This large output swing becomes most noticeable at lower supply voltages.

The positive swing is limited by the saturation voltage of the current source transistor Q7, and VBE of the NPN pull up transistor Q17, and the voltage drop associated with the short circuit resistance, R7. The negative swing is limited by the saturation voltage of the pull–down transistor Q16, the voltage drop ILR6, and the voltage drop associated with resistance R7, where IL is the sink load current. For small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of VEE. For large valued sink currents (>5.0 mA), diode D3 clamps the voltage across R6, thus limiting the negative swing to the saturation voltage of Q16, plus the forward diode drop of D3 (≈VEE +1.0 V). Thus for a given supply voltage, unprecedented peak–to–peak output voltage swing is possible as indicated by the output swing specifications.

If the load resistance is referenced to VCC instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to VCC during the positive swing and the output will pull the load resistance near ground during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull up capability.

Because the PNP output emitter–follower transistor has been eliminated, the MC34071 series offers a 20 mA

minimum current sink capability, typically to an output voltage of (VEE +1.8 V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for fast high current switching applications.

In addition, the all NPN transistor output stage is inherently fast, contributing to the bipolar amplifier’s high gain bandwidth product and fast settling capability. The associated high frequency low output impedance (30 Ω typ @ 1.0 MHz) allows capacitive drive capability from 0 pF to 10,000 pF without oscillation in the unity closed loop gain configuration. The 60° phase margin and 12 dB gain margin as well as the general gain and phase characteristics are virtually independent of the source/sink output swing conditions. This allows easier system phase compensation, since output swing will not be a phase consideration. The high frequency characteristics of the MC34071 series also allow excellent high frequency active filter capability, especially for low voltage single supply applications.

Although the single supply specifications is defined at

5.0 V, these amplifiers are functional to 3.0 V @ 25°C although slight changes in parametrics such as bandwidth, slew rate, and DC gain may occur.

If power to this integrated circuit is applied in reverse polarity or if the IC is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction.

Special static precautions are not necessary for these bipolar amplifiers since there are no MOS transistors on the die.

As with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input–output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous “pick up” at this node. Supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature.

The output of any one amplifier is current limited and thus protected from a direct short to ground. However, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. T ypically for ±15 V supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating.

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11

MC34071,2,4,A MC33071,2,4,A

(T ypical Single Supply Applications VCC = 5.0 V)

Figure 37. AC Coupled Noninverting Amplifer Figure 38. AC Coupled Inverting Amplifier

V

CC

V

5.1 M

20 k

in

36.6 mV

C

in

1.0 M

pp

1.0 k

V

O

0

+

MC34071

–

100 k

AV = 101

BW (–3.0 dB) = 45 kHz

3.7 V

pp

V

CC

0

100 k

C

V

O

10 k

R

L

68 k

C

in

Vin 370 mV

10 k

pp

+

MC34071

–

100 k

C

O

AV = 10 BW (–3.0 dB) = 450 kHz

3.7 V

10 k

R

L

pp

V

O

Figure 39. DC Coupled Inverting Amplifer

Maximum Output Swing

V

O

2.63 V

4.75 V

pp

91 k

5.1 k

V

in

100 k

+

MC34071

–

BW (–3.0 dB) = 450 kHz

Figure 41. Active High–Q Notch Filter

Vin ≥ 0.2 Vdc

V

in

16 k

2.0 C

0.02

0.01

32 k

RR

16 k

C

2.0 R

2.0 C

0.02

–

MC34071

+

1.0 M

AV = 10

fo = 1.0 kHz

fo =

1

4πRC

V

5.1 k R

L

O

Figure 40. Unity Gain Buffer TTL Driver

2.5 V

V

CC

V

O

0 0 to 10,000 pF

V

+

in

MC34071

–

Cable

MC54/74XX

TTL Gate

Figure 42. Active Bandpass Filter

2H

R3

2.2 k –

MC34071

+

V

CC

fo = 30 kHz

Qof

Ho = 10 Ho = 1.0

o

0.4 V

CC

o

4Q2R1–R3

GBW

< 0.1

V

O

C

R2

0.047

C

0.047

R1

V

in

1.1 k

5.6 k

Given fo = Center Frequency AO = Gain at Center Frequency Choose Value fo, Q, Ao, C

Then:

Q R3 R1 R3

R3 = R1 = R2 =

πfoC

For less than 10% error from operational amplifier where fo and GBW are expressed in Hz.

GBW = 4.5 MHz Typ.

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12

MC34071,2,4,A MC33071,2,4,A

Figure 43. Low Voltage Fast D/A Converter Figure 44. High Speed Low Voltage Comparator

C

F

V

in

Bit

Switches

10 k

10 k 10 k

(R–2R) Ladder Network Settling Time

1.0 µs (8–Bits, 1/2 LSB)

Figure 45. LED Driver Figure 46. Transistor Driver

V

in

V

ref

5.0 k5.0 k

+

MC34071

–

5.0 k

R

F

–

MC34071

+

V

CC

“ON” Vin < V

“ON” Vin > V

V

O

V

CC

ref

V

in

+

MC34071

–

2.0 k R

1.0 V

+

MC34071 MC34071

–

L

V

CC

(A) PNP (B) NPN

2.0 V

V

O

V

O

4.0 V 13 V/µs

0.1 Delay

1.0 µs

+ –

R

L

t

0.2 µs Delay

25 V/µs

V

R

L

t

CC

Figure 47. AC/DC Ground Current Monitor Figure 48. Photovoltaic Cell Amplifier

I

Load

R

F

–

MC34071

+

VO = I

Cell RF

VO > 0.1 V

Ground Current

Sense Resistor

+

MC34071

–

R

S

R1

R2

VO = I

BW ( –3.0 dB) = GBW

Load RS

For VO > 0.1V

V

O

R1

1+

R2

R1+R2

I

Cell

V

= 0 V

Cell

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13

V

O

MC34071,2,4,A MC33071,2,4,A

Figure 49. Low Input Voltage Comparator

with Hysteresis

V

R2

V

R1

ref

MC34071

V

in

V

VH =(V

R1

=(V

inL

R1+R2

=(VOH–V

inH

R1+R2

R1

R1+R

OL–Vref

R1

OH

+ –

ref

–VOL)

)+V

V

OH

V

OL

ref

Figure 51. High Input Impedance

Differential Amplifier

R1 R2

–

1/2

MC34072

+V1 +V2

R2 R4

=

VO = 1 V2–V1

For (V2 ≥ V1), V > 0

+

(Critical to CMRR)

R3R1

R4

+

R3

R4 R3

O

R4

–

1/2

MC34072

+

Hysteresis

V

inLVinH

V

ref

Figure 50. High Compliance V oltage to

Sink Current Converter

I

out

V

in

V

in

I

out

=

+

MC34071

–

Vin±V

R

IO

R

Figure 52. Bridge Current Amplifier

+V

ref

R

F

RR

V

O

R = ∆R

∆R < < R RF > > R

R

F

–

MC34071

+

VO = V

(VO ≥ 0.1 V)

V

O

∆R R

F

ref

2

2R

Figure 53. Low V oltage Peak Detector

V

in

+

MC34071

–

V

R

L

in

V

P

t

VO = Vin (pk)

+

10,000 pF

P

f

OSC

Figure 54. High Frequency Pulse

Width Modulation

0.85

^

RC

V

P

t

R

–

1/2

OSC

MC34072

100 k

47 k

V

P

Comparator

C

V+

100 k

+

I

B

0

–

+

1/2

MC34072

–+

Control Group

I

SC

±I

B

Pulse Width

High Current

+

t

Base Charge

Removal

I

out

Output

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14

MC34071,2,4,A MC33071,2,4,A

GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = ±15.0 V

Figure 55. Second Order Low–Pass Active Filter Figure 56. Second Order High–Pass Active Filter

R1

560 510

C1

0.44

R2 =

R3

Ǹ

2

C2

0.02

R2

5.6 k

–

MC34071

+

Choose: fo, Ho, C2 Then: C1 = 2C2 (Ho+1)

R2

R3 = R1 =

Ho+14πfoC2

fo = 1.0 kHz

Ho = 10

R2 H

o

C2

0.05

C1

1.0

Choose: fo, Ho, C1

R2

1.1 k

C1

1.0

R1

46.1 k –

MC34071

+

Then: R1 =

R2 =

C2 =

Figure 57. Fast Settling Inverter Figure 58. Basic Inverting Amplifier

CF*

VO = 10 V

Step

R1

V

O

in

V

R2

O

=

V

R1

in

+

MC34071

–

R2

BW (–3.0 dB) = GBW

I

High Speed

DAC

R

F

2.0 k

–

MC34071

+

Uncompensated

Compensated

ts = 1.0 µs to 1/2 LSB (8–Bits)

ts = 2.2 µs to 1/2 LSB (12–Bits)

fo = 100 Hz Ho = 20

Ho+0.5

πfoC1

Ǹ

2

2πfoC1 (1/Ho+2)

C

H

o

R1

R1 +R2

SR = 13 V/µs

Ǹ

2

V

O

R

L

*Optional Compensation

SR = 13 V/µs

Figure 59. Basic Noninverting Amplifier Figure 60. Unity Gain Buffer (AV = +1.0)

+

MC34071

V

in

R1

–

R2

V

O

=

1 +

V

in

BW (–3.0 dB) = GBW

R

R2 R1

R1

R1 +R2

V

O

L

V

in

+

MC34071

–

BWp = 200 kHz VO = 20 V SR = 10 V/µs

pp

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15

V

O

MC34071,2,4,A MC33071,2,4,A

Figure 61. High Impedance Differential Amplifier

+

MC34074

–

R

E

R

–

MC34074

+

R

–

MC34074

+

Example: Let: R = RE = 12 k Then: AV = 3.0 BW = 1.5 MHz

V

O

AV = 1 + 2

R

E

Figure 62. Dual V oltage Doubler

+V

O

220 pF

R

+V

L

18.93 –18.78

∞

10 k 18 –18

5.0 k 15.4 –15.4

–V

O

100 k

+10

–

MC34074

+

–10

O

100 k

+

MC34074

–

+

MC34074

–

+

10

+

10

+

10

+

10

R

L

R

L

–V

O

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16

Op Amp

Function

Single MC34071P, MC34071AP

MC34071D, MC34071AD MC34071DR2, MC34071ADR2

MC33071P, MC33071AP MC33071D, MC33071AD MC33071DR2, MC33071ADR2

Dual MC34072P , MC34072AP

MC34072D, MC34072AD MC34072DR2, MC34072ADR2

MC33072P, MC33072AP MC33072D, MC33072AD MC33072DR2, MC33072ADR2

MC34072VD MC34072VDR2

Quad MC34074P , MC34074AP

MC34074D, MC34074AD MC34074DR2, MC34074ADR2

MC33074P, MC33074AP MC33074D, MC33074AD MC33074DR2, MC33074ADR2 MC33074DTB, MC33074ADTB MC33074DTBR2, MC33074ADTBR2

MC34074VD MC34074VDR2

Device

MC34071,2,4,A MC33071,2,4,A

ORDERING INFORMATION

Operating

Temperature Range

TA = 0° to +70°C

TA = –40° to +85°C

TA = 0° to +70°C

TA = –40° to +85°C

TA = –40° to +125°C

TA = 0° to +70°C

TA = –40° to +85°C

TA = –40° to +125°C

Package Shipping

SO–8 / Tape & Reel

TSSOP–14

TSSOP–14 / Tape & Reel

SO–8 / Tape & Reel

DIP–8

SO–8

DIP–8

SO–8

DIP–8

SO–8

DIP–8

SO–8

DIP–8

SO–8

DIP–8

SO–8