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MC33067
User Manual
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ON Semiconductor MC33067, MC34067 User Manual

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© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 13
1 Publication Order Number:
MC34067/D
MC34067, MC33067
High Performance Resonant Mode Controllers
Also included are protective features consisting of a high speed fault comparator and latch, programmable soft−start circuitry, input undervoltage lockout with selectable thresholds, and reference undervoltage lockout. These devices are available in dual−in−line and surface mount packages.
Features
• Zero Voltage Switch Resonant Mode Operation
• Variable Frequency Oscillator with a Control Range
Exceeding 1000:1
• Precision One−Shot Timer for Controlled Off−Time
• Internally Trimmed Bandgap Reference
• 4.0 MHz Error Amplifier
• Dual High Current Totem Pole Outputs
• Selectable Undervoltage Lockout Thresholds with Hysteresis
• Enable Input
• Programmable Soft−Start Circuitry
• Low Startup Current for Off−Line Operation
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Figure 1. Simplified Block Diagram
Noninverting
Input
11
8
6
16
3
2
1
OSC Charge
Enable /
UVLO Adjust
V
CC
15
5
14
12
13
V
ref
UVLO
Error Amp
V
CC
UVLO /
Enable
Fault Detector/
Latch
2.5 V
Clamp
Soft-Start
One-Shot
Output B
Inverting Input
Soft-Start
7
Error Amp
Output
One-Shot
Oscillator
Control Current
OSC RC
9
Ground4
Fault Input
10
Pwr GND
Output A
V
ref
Variable
Frequency
Oscillator
Steering
Flip-Flop
5.0 V
Reference
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
MARKING
DIAGRAMS
x = 3 or 4 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package
PDIP−16
P SUFFIX
CASE 648
1
16
SOIC−16W DW SUFFIX CASE 751G
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PIN CONNECTIONS
(Top View)
V
ref
OSC Charge
OSC RC
OSC Control Current
GND
Error Amp Out
Inverting Input
Noninverting Input
One-Shot RC
V
CC
Drive Output B
C
Soft-Start
Enable/UVLO Adjust
Drive Output A
Power GND
Fault Input
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16
1
MC3x067DW
AWLYYWWG
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
16
1
MC3x067P
AWLYYWWG
16
1
MC34067, MC33067
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2
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage V
CC
20 V
Drive Output Current, Source or Sink (Note 1)
− Continuous
− Pulsed (0.5 ms), 25% Duty Cycle
I
O
0.3
1.5
A
Error Amplifier, Fault, One−Shot, Oscillator and Soft−Start Inputs V
in
− 1.0 to + 6.0 V
UVLO Adjust Input V
in(UVLO)
− 1.0 to V
CC
V
Power Dissipation and Thermal Characteristics
DW Suffix, Plastic Package, Case 751G
T
A
= 25°C
Thermal Resistance, Junction−to−Air
P Suffix, Plastic Package, Case 648
T
A
= 25°C
Thermal Resistance, Junction−to−Air
P
D
R
q
JA
P
D
R
q
JA
862 145
1.25 100
mW
°C/W
W
°C/W
Operating Junction Temperature T
J
+ 150 °C
Operating Ambient Temperature
MC34067 MC33067
T
A
0 to + 70
− 40 to + 85
°C
Storage Temperature T
stg
− 55 to + 150 °C
ESD Capability, HBM Model − 2.0 kV
ESD Capability, MM Model − 200 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
Device Package Shipping
†
MC33067DWG SOIC−16W
(Pb−Free)
47 Units / Rail
MC33067DWR2G SOIC−16W
(Pb−Free)
1000 / Tape & Reel
MC33067PG PDIP−16
(Pb−Free)
25 Units / Rail
MC34067DWG SOIC−16W
(Pb−Free)
47 Units / Rail
MC34067DWR2G SOIC−16W
(Pb−Free)
1000 / Tape & Reel
MC34067PG PDIP−16
(Pb−Free)
25 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
ELECTRICAL CHARACTERISTICS
(VCC = 12 V [Note 2], R
OSC
= 18.2 k, R
VFO
= 2940 W, C
OSC
= 300 pF, R
T
= 2370 W, CT = 300 pF, CL = 1.0 nF. For typical values
T
A
= 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 3), unless otherwise noted.)
Characteristic
Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (I
O
= 0 mA, TJ = 25°C) V
ref
5.0 5.1 5.2 V
Line Regulation (VCC = 10 V to 18 V) Reg
line
− 1.0 20 mV
Load Regulation (IO = 0 mA to 10 mA) Reg
load
− 1.0 20 mV
Total Output Variation Over Line, Load, and Temperature V
ref
4.9 − 5.3 V
Output Short Circuit Current
(0°C to 70°C) (−40°C to 85°C)
I
O
30 25
100 100
190 225
mA
Reference Undervoltage Lockout Threshold V
th
3.8 4.3 4.8 V
ERROR AMPLIFIER
Input Offset Voltage (V
CM
= 1.5 V) V
IO
− 1.0 10 mV
Input Bias Current (VCM = 1.5 V) I
IB
− 0.2 1.0
mA
Input Offset Current (VCM = 1.5 V) I
IO
− 0 0.5
mA
Open Loop Voltage Gain (VCM = 1.5 V, VO = 2.0 V) A
VOL
70 100 − dB
Gain Bandwidth Product (f = 100 kHz)
T
A
= 25°C
T
A
= T
low
to T
high
GBW
3.0
2.7
5.0
−
−
−
MHz
Input Common Mode Rejection Ratio (VCM = 1.5 V to 5.0 V) CMR 70 95 − dB
Power Supply Rejection Ratio (VCC = 10 V to 18 V, f = 120 Hz) PSR 80 100 − dB
Output Voltage Swing
High State (I
source
= 2.0 mA)
Low State (I
sink
= 4.0 mA)
V
OH
V
OL
2.8
−
3.2
0.6
−
0.8
V
1. Maximum package power dissipation limits must be observed.
2. Adjust V
CC
above the Startup Threshold voltage before setting to 12 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
4. T
low
=0°C for MC34067 = − 40°C for MC33067
T
high
=+70°C for MC34067 =+85°C for MC33067
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4
ELECTRICAL CHARACTERISTICS (continued) (V
CC
= 12 V [Note 6], R
OSC
= 18.2 k, R
VFO
= 2940 W, C
OSC
= 300 pF,
R
T
= 2370 W, CT = 300 pF, CL = 1.0 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range
that applies (Note 7), unless otherwise noted.)
Characteristic
Symbol Min Typ Max Unit
OSCILLATOR
Frequency (Error Amp Output Low)
Total Variation (V
CC
= 10 V to 18 V, TA = T
Low
to T
High
) f
OSC(low)
490 525 550
kHz
Frequency (Error Amp Output High)
Total Variation (V
CC
= 10 V to 18 V, TA = T
Low
to T
High
) f
OSC(high)
1850 2050 2200
kHz
Oscillator Control Input Voltage, Pin 3 V
in
− 2.5 − V
ONE−SHOT
Drive Output Off−Time
T
A
= 25°C
Total Variation (V
CC
= 10 V to 18 V, TA = T
Low
to T
High
)
t
Blank
235 225
250
−
270 280
ns
DRIVE OUTPUTS
Output Voltage
Low State (I
Sink
= 20 mA)
Low State (I
Sink
= 200 mA)
High State (I
Source
= 20 mA)
High State (I
Source
= 200 mA)
V
OL
V
OH
−
−
9.5
9.0
0.8
1.5
10.3
9.7
1.2
2.0
−
−
V
Output Voltage with UVLO Activated (VCC = 6.0 V, I
Sink
= 1.0 mA) V
OL(UVLO)
− 0.8 1.2 V
Output Voltage Rise Time (CL = 1.0 nF) t
r
− 20 50 ns
Output Voltage Fall Time (CL = 1.0 nF) t
f
− 15 50 ns
FAULT COMPARATOR
Input Threshold V
th
0.93 1.0 1.07 V
Input Bias Current (V
Pin 10
= 0 V) I
IB
− − 2.0 − 10
mA
Propagation Delay to Drive Outputs (100 mV Overdrive) t
PLH(In/Out)
− 60 100 ns
SOFT−START
Capacitor Charge Current (V
Pin 11
= 2.5 V) I
chg
4.5 9.0 14
mA
Capacitor Discharge Current (V
Pin 11
= 2.5 V) I
dischg
3.0 8.0 − mA
UNDERVOLTAGE LOCKOUT
Startup Threshold, V
CC
Increasing Enable/UVLO Adjust Pin Open Enable/UVLO Adjust Pin Connected to V
CC
V
th(UVLO)
14.8
8.0
16
9.0
17.2 10
V
Minimum Operating Voltage After Turn−On, VCC Decreasing
Enable/UVLO Adjust Pin Open Enable/UVLO Adjust Pin Connected to V
CC
V
CC(min)
8.0
7.6
9.0
8.6
10
9.6
V
Enable/UVLO Adjust Shutdown Threshold Voltage V
th(Enable)
6.0 7.0 − V
Enable/UVLO Adjust Input Current (Pin 9 = 0 V) I
in(Enable)
− − 0.2 − 1.0 mA
TOTAL DEVICE
Power Supply Current (Enable/UVLO Adjust Pin Open)
Startup (V
CC
= 13.5 V)
Operating (f
OSC
= 500 kHz) (Note 6)
I
CC
−
−
0.5 27
0.8 35
mA
5. Maximum package power dissipation limits must be observed.
6. Adjust V
CC
above the Startup Threshold voltage before setting to 12 V.
7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
8. T
low
=0°C for MC34067 = − 40°C for MC33067
T
high
=+70°C for MC34067 =+85°C for MC33067
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5
A
VOL
, OPEN LOOP VOLTAGE GAIN (dB)
R
T
Ω, TIMING RESISTOR (k )
R
OSC
Ω, OSCILLATOR TIMING RESISTOR (k )
One-Shot Period is Measured at the Drive Outputs.
Oscillator Discharge Time is Measured at the Drive Outputs.
f
OSC
C
OSC
= 200 pF
60
30
20
10
6.0
3.0
500
0
, OSCILLATOR FREQUENCY (kHz)
t
dischg
, OSCILLATOR DISCHARGE TIME (ms)
3500
3000
2500
2000
1500
1000
I
OSC
, OSCILLATOR CONTROL CURRENT (mA)
0.35
0.30
0.25
0.20
0.15
0.10
I
OSC
, OSCILLATOR CONTROL CURRENT (mA)
t
OS
, ONE-SHOT PERIOD (ms)
0
0.05
200
VCC = 12 V T
A
= 25°C
R
OSC
= 18.2 k
400
300
100
500
C
OSC
= 300 pF
0
-10
-20
-30
-40
-50
50
40
30
20
10
0
f, FREQUENCY (Hz)
, REFERENCE OUTPUT VOLTAGE CHANGE (mV)
TA, AMBIENT TEMPERATURE (°C)
-20
∇
-10
Gain
V
ref
50
60
70
80
90
100
120
110
0, EXCESS PHASE (DEGREES)
C
OSC
= 500 pF
C
OSC
= 300 pF
VCC = 12 V R
VFO
= ∞
R
T
= ∞ CT = 500 pF T
A
= 25°C
Figure 2. Oscillator Timing Resistor
versus Discharge Time
Figure 3. Oscillator Frequency versus
Oscillator Control Current
Figure 4. Error Amp Output Low State Voltage
versus Oscillator Control Current
Figure 5. One−Shot Timing Resistor
versus Period
Figure 6. Open Loop Voltage Gain and Phase
versus Frequency
Figure 7. Reference Output Voltage Change
versus Temperature
0 400 800 1200 1600 200
0
0 20406080100
0 0.5 1.0 1.5 2.0 2.5 3.0 0.1 0.3 0.6 1.0 3.0 6.0 10
10 k 100 k 1.0M 10M
-55 -25 0 25 50 75 125100
VCC = 12 V V
O
= 2.0 V
R
L
= 100 k
T
A
= 25°C
VCC = 12 V R
L
= ∞
*V
ref at
TA = 25°C
VCC = 12 V C
OSC
= 500 pF
R
OSC
= 100 k
T
A
= 25°C
Phase Margin
= 64°
*V
ref
= 5.1 V
CT = 200 pF
CT = 300 pF CT = 500 pF
Phase
*V
ref
= 5.2 V
*V
ref
= 5.0 V
V
OL
, OUTPUT LOW STATE VOLTAGE (V)
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24
2.0
, REFERENCE OUTPUT VOLTAGE CHANGE (mV)
∇
V
ref
V
sat
3.2
2.4
1.6
0.8
0
0
-50
, OUTPUT SATURATION VOLTAGE (V)
Figure 8. Reference Output Voltage Change
versus Source Current
I
ref
, REFERENCE SOURCE CURRENT (mA)
Figure 9. Drive Output Saturation Voltage
versus Load Current
0
-1.0
-2.0
-3.0
3.0
I
O
, OUTPUT LOAD CURRENT (A)
Figure 10. Drive Output Waveform
90%
10%
20 ns/DIV
V , SOFT-START SATURATION VOLTAGE (V)
Figure 11. Soft−Start Saturation Voltage
versus Capacitor Discharge Current
I
dchg
, CAPACITOR DISCHARGE CURRENT (mA)
0
-30
-10
-20
-40
1.0
2000
1600
1200
800
400
0
f, OPERATING FREQUENCY (kHz)
Figure 12. Operating Frequency
versus Supply Current
ICC, SUPPLY CURRENT (mA)
Source Saturation
(Load to Ground)
Source Saturation
(Load to V
CC
)
OL
GND
TA = -40°C
TA = 25°C
Figure 13. Supply Current versus Supply Voltage
TA = 25°C
TA = -40°C
VCC, SUPPLY VOLTAGE (V)
20
12
4.0
0
I , SUPPLY CURRENT (mA)
CC
16
8.0
VCC = 12 V
80 ms Pulsed Load
120 Hz Rate
TA = -40°C
CL = 1.0 nF
T
A
= 25 °C
0 0.2 0.4 0.6 0.8 1.00 20 40 60 80 100
0 2.0 4.0 6.0 8.0 10
30 40 50 60 70 80 90 0 4.0 8.0 12 16 20
VCC = 12 V C
L
= 1.0 nF
TA = 25 °C
VCC = 12 V Pin 10 = V
ref
TA = 25 °C
TA = -20°C
TA = -125°C
VCC = 12 V
V
CC
TA = 25 °C
Enable/UVLO
Adjust Pin
to V
CC
(Dashed Line)
Enable/UVLO
Adjust Pin
Open
(Solid Line)
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3
Figure 14. MC34067 Representative Block Diagram
12
Output B
13
14
8
7
Inverting Input
Oscillator
Control Current
16
9
8.0 V
Q2
R
R
T
C
T
R
OSC
C
OSC
R
VFO
V
ref
4.9V/3.6 V
15
V
CC
Enable /
UVLO Adjust
OSC Charge
OSC RC
One-Shot RC
Error Amp Output
Noninverting Input
Soft-Start
Ground4
Fault Input
Power Ground
Output A
V
ref
D1
Q1
I
OSC
Oscillator
One-Shot
Error Amp
Clamp
3.1V
Error Amp
9.0 mA
1.0 V
Q
Q
T
Steering
Flip-Flop
4.2/4.0 V
V
ref
UVLO
V
CC
UVLO
7.0k
50k 7.0k
50k
4.9 V/3.6 V
V
ref
5.1 V
Reference
1
2
6
11
5
10
Figure 15. Timing Diagram
5.1 V
3. 6 V
C
OSC
5.1 V
3.6 V
One-Shot
Output A
Output B
t
OS
t
OS
t
OS
t
OS
t
OS
t
OS
High State Error Amp output, minimum I
OSC
current
occurring at minimum input voltage, maximum load.
Low State Error Amp output, maximum I
OSC
current
occurring at maximum input voltage, minimum load.
Fault Comparator
I
OSC
Fault
Latch
S
R
Q
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8
OPERATING DESCRIPTION
Introduction
As power supply designers have strived to increase power conversion efficiency and reduce passive component size, high frequency resonant mode power converters have emerged as attractive alternatives to conventional pulse−width modulated control. When compared to pulse−width modulated converters, resonant mode control offers several benefits including lower switching losses, higher efficiency, lower EMI emission, and smaller size. A new integrated circuit has been developed to support this trend in power supply design. The MC34067 Resonant Mode Controller is a high performance bipolar IC dedicated to variable frequency power control at frequencies exceeding 1.0 MHz. This integrated circuit provides the features and performance specifically for zero voltage switching resonant mode power supply applications.
The primary purpose of the control chip is to provide a fixed off−time to the gates of external power MOSFETs at a repetition rate regulated by a feedback control loop. Additional features of the IC ensure that system startup and fault conditions are administered in a safe, controlled manner.
A simplified block diagram of the IC is shown on the front page, which identifies the main functional blocks and the block−to−block interconnects. Figure 14 is a detailed functional diagram which accurately represents the internal circuitry. The various functions can be divided into two sections. The first section includes the primary control path which produces precise output pulses at the desired frequency. Included in this section are a variable frequency Oscillator, a One−Shot, a pulse Steering Flip−Flop, a pair of power MOSFET Drivers, and a wide bandwidth Error Amplifier. The second section provides several peripheral support functions including a voltage reference, undervoltage lockout, soft−start circuit, and a fault detector.
Primary Control Path
The output pulse width and repetition rate are regulated through the interaction of the variable frequency Oscillator, One−Shot timer and Error Amplifier. The Oscillator triggers the One−Shot which generates a pulse that is alternately steered to a pair of totem pole output drivers by a toggle Flip−Flop. The Error Amplifier monitors the output of the regulator and modulates the frequency of the Oscillator. High speed Schottky logic is used throughout the primary control channel to minimize delays and enhance high frequency characteristics.
Oscillator
The characteristics of the variable frequency Oscillator are crucial for precise controller performance at high operating frequencies. In addition to triggering the One−Shot timer and initiating the output deadtime, the oscillator also determines the initial voltage for the one−shot capacitor. The Oscillator is designed to operate at
frequencies exceeding 1.0 MHz. The Error Amplifier can control the oscillator frequency over a 1000:1 frequency range, and both the minimum and maximum frequencies are easily and accurately programmed by the proper selection of external components.
The functional diagram of the Oscillator and One−Shot
timer is shown in Figure 16. The oscillator capacitor (C
OSC
)
is initially charged by transistor Q1. When C
OSC
exceeds the
4.9 V upper threshold of the oscillator comparator, the base of Q1 is pulled low allowing C
OSC
to discharge through the
external resistor, (R
OSC),
and the oscillator control current,
(I
OSC
). When the voltage on C
OSC
falls below the 3.6 V lower threshold of the comparator, Q1 turns on and again charges C
OSC
.
C
OSC
charges from 3.6 V to 5.1 V in less than 50 ns. The
high slew rate of C
OSC
and the propagation delay of the comparator make it difficult to control the peak voltage. This accuracy issue is overcome by clamping the base of Q1 through a diode to a voltage reference. The peak voltage of the oscillator waveform is thereby precisely set at 5.1 V.
Figure 16. Oscillator and One−Shot Timer
Oscillator
Control Current
C
OSC
R
T
C
T
R
OSC
4.9 V/3.6 V
1
2
10
3
OSC Charge
OSC RC
One-Shot RC
D1
Q1
I
OSC
Oscillator
One-Shot
3.1 V
4.9V/3.6V
V
ref
Error Amp Output
6
Error Amp Clamp
R
VFO
I
OSC
V
CC
V
CC
The frequency of the Oscillator is modulated by varying the current flowing out of the Oscillator Control Current (I
OSC
) pin. The I
OSC
pin is the output of a voltage regulator. The input of the voltage regulator is tied to the variable frequency oscillator. The discharge current of the Oscillator increases by increasing the current out of the I
OSC
pin.
Resistor R
VFO
is used in conjunction with the Error Amp
output to change the I
OSC
current. Maximum frequency occurs when the Error Amplifier output is at its low state with a saturation voltage of 0.1 V at 1.0 mA.
The minimum oscillator frequency will result when the
I
OSC
current is zero, and C
OSC
is discharged through the
external resistor (R
OSC
). This occurs when the Error Amplifier output is at its high state of 2.5 V. The minimum and maximum oscillator frequencies are programmed by the proper selection of resistor R
OSC
and R
VFO
.
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9
The minimum frequency is programmed by R
OSC
using
Equation 1:
ȏ
ǒǓ
C
OSC
where t
PD
is the internal propagation delay.
(eq. 1)
R
1
ƒ
t
PD
nC
t
70 ns
0.348
−
=
=
−
OSC
(min)
(max)
OSC
5.1
3.6
The maximum oscillator frequency is set by the current
through resistor R
VFO
. The current required to discharge
C
OSC
at the maximum oscillator frequency can be calculated
by Equation 2:
C
OSC
1.5C
(eq. 2)
OSC
I
1
ƒ
5.1 − 3.6
=
=
(max)
(max)
ƒ
(max)
The discharge current through R
OSC
must also be known
and can be calculated by Equation 3:
ƒ
(min)
C
OSC
R
OSC
1.5
εI
1
ƒ
5.1 − 3.6
=
(min)
R
R
OSC
C
OSC
R
OSC
=
R
OSC
ε
1
−
−
ǒǓ
ǒǓ
OSC
(eq. 3)
Resistor R
VFO
can now be calculated by Equation 4:
R=
VFO
I
(max)IR
−
2.5 − V EAsat
OSC
(eq. 4)
One−Shot Timer
The One−Shot is designed to disable both outputs simultaneously providing a deadtime before either output is enabled. The One−Shot capacitor (C
T
) is charged concurrently with the oscillator capacitor by transistor Q1, as shown in Figure 16. The one−shot period begins when the oscillator comparator turns off Q1, allowing C
T
to
discharge. The period ends when resistor R
T
discharges C
T
to the threshold of the One−Shot comparator. The lower threshold of the One−Shot is 3.6 V. By choosing C
T
, RT can
by solved by Equation 5:
ǒǓ
5.1
3.6
C
T
R
t
OS
C
0.348
=
=
T
T
t
OS
ȏ
n
(eq. 5)
Errors in the threshold voltage and propagation delays through the output drivers will affect the One−Shot period. To guarantee accuracy, the output pulse of the control chip is trimmed to within 5% of 250 ns with nominal values of R
T
and CT.
The outputs of the Oscillator and One−Shot comparators are OR’d together to produce the pulse t
OS
, which drives the
Flip−Flop and output drivers. The output pulse (t
OS
) is initiated by the Oscillator and terminated by the One−Shot comparator. With zero voltage resonant mode converters, the oscillator discharge time should never be set less than the one−shot period.
Error Amplifier
A fully accessible high performance Error Amplifier is provided for feedback control of the power supply system. The Error Amplifier is internally compensated and features dc open loop gain greater than 70 dB, input offset voltage of less than 10 mV and a guaranteed minimum gain−bandwidth product of 2.5 MHz. The input common mode range extends from 1.5 V to 5.1 V, which includes the reference voltage.
Figure 17. Error Amplifier and Clamp
R
VFO
Oscillator
Control Current
3.1 V
Error Amp Output
Noninverting Input
Inverting Input
Error Amp
I
OSC
7
8
6
3
Error Amp
Clamp
When the Error Amplifier output is coupled to the I
OSC
pin by R
VFO
, as illustrated in Figure 17, it provides the
Oscillator Control Current, I
OSC
. The output swing of the Error Amplifier is restricted by a clamp circuit to improve its transient recovery time.
Output Section
The pulse(tOS), generated by the Oscillator and One−Shot timer is gated to dual totem−pole output drives by the Steering Flip−Flop shown in Figure 18. Positive transitions of t
OS
toggle the Flip−Flop, which causes the pulses to alternate between Output A and Output B. The flip−flop is reset by the undervoltage lockout circuit during startup to guarantee that the first pulse appears at Output A.
Figure 18. Steering Flip−Flop and Output Drivers
Output A
R
12
13
14
Output B
Power Ground
Q
Q
T
Steering
Flip-Flop
PWR
GND
V
CC
V
CC
PWR
GND
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The totem−pole output drivers are ideally suited for driving
power MOSFETs and are capable of sourcing and sinking
1.5 A. Rise and fall times are typically 20 ns and 15 ns respectfully when driving a 1.0 nF load. High source/sink capability in a totem−pole driver normally increases the risk of high cross conduction current during output transitions.
The MC34067 utilizes a unique design that virtually eliminates cross conduction, thus controlling the chip power dissipation at high frequencies. A separate power ground pin is provided to isolate the sensitive analog circuitry from large transient currents.
Figure 19. Undervoltage Lockout and Reference
8.0 V
V
ref
15
9
V
CC
5
V
ref
4.2/4.0 V
V
ref
UVLO
V
CC
UVLO
7.0k
50k
7.0k
50k
5.1 V
Reference
Enable /
UVLO Adjust
UVLO
PERIPHERAL SUPPORT FUNCTIONS
The MC34067 Resonant Controller provides a number of support and protection functions including a precision voltage reference, undervoltage lockout comparators, soft−start circuitry, and a fault detector. These peripheral circuits ensure that the power supply can be turned on and off in a controlled manner and that the system will be quickly disabled when a fault condition occurs.
Undervoltage Lockout and Voltage Reference
Separate undervoltage lockout comparators sense the input V
CC
voltage and the regulated reference voltage as
illustrated in Figure 19. When V
CC
increases to the upper
threshold voltage, the V
CC
UVLO comparator enables the
Reference Regulator. After the V
ref
output of the Reference
Regulator rises to 4.2 V, the V
ref
UVLO comparator switches the UVLO signal to a logic zero state enabling the primary control path. Reducing V
CC
to the lower threshold voltage
causes the V
CC
UVLO comparator to disable the Reference
Regulator. The V
ref
UVLO comparator then switches the
UVLO output to a logic one state disabling the controller.
The Enable/UVLO Adjust pin allows the power supply
designer to select the V
CC
UVLO threshold voltages. When this pin is open, the comparator switches the controller on at 16 V and off at 9.0 V. If this pin is connected to the V
CC
terminal, the upper and lower thresholds are reduced to
9.0 V and 8.6 V, respectively. Forcing the Enable/UVLO Adjust pin low will pull the V
CC
UVLO comparator input
low (through an internal diode) turning off the controller.
The Reference Regulator provides a precise 5.1 V
reference to internal circuitry and can deliver up to 10 mA
to external loads. The reference is trimmed to better than 2% initial accuracy and includes active short circuit protection.
Fault Detection
Converter protection from adverse operating conditions can be implemented with proper use of the Fault Comparator and Latch blocks that are illustrated in Figure 20. The Fault Comparator has an input threshold of 1.0 V and when exceeded, sets the Fault Latch and generates two logic signals that simultaneously disable the primary control path. The signal line labeled “Fault” connects directly to two gates that control the output drivers. This direct path reduces the driver turn−off propagation delay to approximately 70 ns. The Fault Latch output is OR’ed with the UVLO output that is derived from the V
ref
UVLO comparator, to produce the logic output labeled “UVLO+Fault”. This signal disables the Oscillator and the One−Shot by forcing both the C
OSC
and CT capacitors to be continually charged.
The Fault Latch is automatically reset during startup by a
logic “1” that appears at the V
ref
UVLO comparator output. The latch can also be reset after startup by momentarily pulling the Enable/UVLO Adjust pin low to disable the Reference. Note that after activation, the Fault Latch will remain in a set state only as long as V
CC
is provided to the MC34067. Also, Drive Output B will assume a high state if the Fault input signal drops below the 1.0 V threshold level even after the Fault Latch has been set. In some applications this characteristic could be problematic but it can be easily remedied by AC coupling Drive Output B.
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Fault
Latch
S
R
Q
Figure 20. Fault Detector and Soft−Start
C
Soft-Start
Fault Input
10
9.0 mA
1.0 V
11
6 Ground
Soft-Start
Buffer
Error Amp
Clamp
UVLO + Fault
UVLO
Fault
Comparator
Fault
Soft−Start Circuit
The Soft−Start circuit shown in Figure 20 forces the variable frequency Oscillator to start at the maximum frequency and ramp downward until regulated by the feedback control loop. The external capacitor at the C
Soft−Start
terminal is initially discharged by the UVLO+Fault signal. The low voltage on the capacitor passes through the Soft−Start Buffer to hold the Error Amplifier output low. After UVLO+Fault switches to a logic zero, the soft−start capacitor is charged by a 9.0 mA current source. The buffer allows the Error Amplifier output to follow the soft−start capacitor until it is regulated by the Error Amplifier inputs. The soft−start function is generally applicable to controllers operating below resonance and can be disabled by simply opening the C
Soft−Start
terminal.
APPLICATIONS INFORMATION
The MC34067 is specifically designed for zero voltage switching (ZVS) quasi−resonant converter (QRC) applications. The IC is optimized for double−ended push−pull or bridge type converters operating in continuous conduction mode. Operation of this type of ZVS with resonant properties is similar to standard push−pull or bridge circuits in that the energy is transferred during the transistor on−time. The difference is that a series resonant tank is usually introduced to shape the voltage across the power transistor prior to turn−on. The resonant tank in this topology is not used to deliver energy to the output as is the case with zero current switch topologies. When the power transistor is enabled the voltage across it should already be zero, yielding minimal switching loss. Figure 21 shows a timing diagram for a half−bridge ZVS QRC. An application circuit is shown in Figure 22. The circuit built is a dc to dc half−bridge converter delivering 75 W to the output from a 48 V source.
When building a zero voltage switch (ZVS) circuit, the objective is to waveshape the power transistor’s voltage waveform so that the voltage across the transistor is zero when the device is turned on. The purpose of the control IC is to allow a resonant tank to waveshape the voltage across the power transistor while still maintaining regulation. This is accomplished by maintaining a fixed deadtime and by varying the frequency; thus the effective duty cycle is changed.
Primary side resonance can be used with ZVS circuits. In the application circuit, the elements that make the resonant tank are the primary leakage inductance of the transformer (L
L
) and the average output capacitance (C
OSS
) of a power
MOSFET (C
R
).
The desired resonant frequency for the application circuit
is calculated by Equation 6:
LL2C
R
1
=
π2
ƒ
r
(eq. 6)
In the application circuit, the operating voltage is low and
the value of C
OSS
versus Drain Voltage is known. Because
the C
OSS
of a MOSFET changes with drain voltage, the
value of the C
R
is approximated as the average C
OSS
of the
MOSFET. For the application circuit the average C
OSS
can
be calculated by Equation 7:
measured at
C
R
1 2
2 * C
OSS
=
in
V
(eq. 7)
The MOSFET chosen fixes CR and that LL is adjusted to
achieve the desired resonant frequency.
However, the desired resonant frequency is less critical than the leakage inductance. Figure 21 shows the primary current ramping toward its peak value during the resonant transition. During this time, there is circulating current flowing through the secondary inductance, which effectively makes the primary inductance appear shorted. Therefore, the current through the primary will ramp to its peak value at a rate controlled by the leakage inductance and the applied voltage. Energy is not transferred to the secondary during this stage, because the primary current has not overcome the circulating current in the secondary. The larger the leakage inductance, the longer it takes for the primary current to slew. The practical effect of this is to lower the duty cycle, thus reducing the operating range.
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The maximum duty cycle is controlled by the leakage inductance, not by the MC34067. The One−Shot in the MC34067 only assures that the power switch is turned on under a zero voltage condition. Adjust the one−shot period
so that the output switch is activated while the primary current is slewing but before the current changes polarity. The resonant stage should then be designed to be as long as the time for the primary current to go to 0 A.
Figure 21. Application Timing Diagram
0 A
+ I
primary
- I
primary
Output Rectifier Voltage
0 V
1/2 V
in
V
in
Drive Output B
Drive Output A
One-Shot
3.6 V
5.1 V
C
OSC
3.6 V
5.1 V
Vin/Turns Ratio
Primary Current
Input Voltage
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Inductance = 1.8 Hμ
MBR2535
330pF
100pF
16k
1.6k
330pF
1500pF
220pF
0.01
10k
1.1k
2.7k
18k
10
V
CC
15
9
1
2
16
3
6
8
7
11
4
Reference
5
14
13
12
10
470pF
470
3.9k
1N5819
T2
MTP33N10E
100
1.0
1.0
T3
1.0k
1.0k
100
1N5819 x 4
V
in
500pF
51/0.5W
CTL
230
V
out
L1 L2
Figure 22. Application Circuit
Line Regulation
Load Regulation
Output Ripple
Efficiency
Test Conditions Results
V
in
= 40 V to 56 V, I
O
=15 A
V
in
= 48 V, I
O
= 10 A to 15 A
V
in O
= 48 V, I = 15 A, f
20 mV =
switch
= 1.0 MHz
V
in O
= 48 V, I = 10 A, f
switch
= 1.7 MHz
V
in O
= 48 V, I = 15 A, f
switch
= 1.0 MHz
±0.198%
4.0 mV = ±0.039%
25 mV
p−p
83.5%
84.2%
T1 = Primary: 12 turns #48 AWG (1300 strands litz wire)
Secondary: 6 turns center tapped #48 AWG (1300 strands litz wire)
Core: Philips 3F3 4312 020 4124
Bobbin: Philips 4322 021 3525
Primary Leakage Inductance = 1.0 Hμ
T2 = All windings: 8 turns #36 AWG
Core: Philips 3F3 EP7−3F3
Bobbin: Philips EP7PCB1−6
T3 = Coilcraft D1870 (100 turns)
L1 = 2 turns #48 AWG (1300 strands litz wire)
Core: Philips 3F3 EP10−3F3
Bobbin: Philips EP10PCB1−8
L2 = 5 turns #48 AWG (1300 strands litz wire)
Core: 0.5
Inductance = 100 nH
″ diameter air code
Heatsinks = AAVID Engineering Inc. 533402B02552 with clip
MC34067−5803
Insulators = Berquist Sil−Pad 1500
5.0 V
36 V to 56 V
T1
1N5819
500pF
51/0.5W
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5.0″
(Bottom View)
Figure 23. Printed Circuit Board and Component Layout
(Top View)
3.875″
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PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
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PACKAGE DIMENSIONS
SOIC−16W
DW SUFFIX
CASE 751G−03
ISSUE C
D
14X
B16X
SEATING PLANE
S
A
M
0.25 B
S
T
16 9
81
h X 45
_
M
B
M
0.25
H8X
E
B
A
e
T
A1
A
L
C
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0 7
__
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