MC14012B
B−Suffix Series CMOS Gates
The B Series logic gates are constructed with P−Channel and
N−Channel enhancement mode devices in a single monolithic
structure (Complementary MOS). Their primary use is where low
power dissipation and/or high noise immunity is desired.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
• Pin−for−Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
Symbol Parameter Value Unit
V
Vin, V
Iin, I
P
T
T
T
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
DC Supply Voltage Range −0.5 to +18.0 V
DD
Input or Output Voltage Range
out
out
D
A
stg
L
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range −55 to +125 °C
Storage Temperature Range −65 to +150 °C
Lead Temperature
(8−Second Soldering)
)
SS
−0.5 to VDD + 0.5 V
±10 mA
500 mW
260 °C
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MARKING
DIAGRAMS
14
PDIP−14
P SUFFIX
CASE 646
SOIC−14
D SUFFIX
CASE 751A
SOEIAJ−14
F SUFFIX
CASE 965
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MC14012BCP
AWLYYWW
1
14
14012B
AWLYWW
1
14
MC14012B
AWLYWW
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 6
(Vin or V
SS
or VDD). Unused outputs must be left open.
SS
) VDD.
out
and V
in
should be constrained
out
1 Publication Order Number:
MC14012B/D
MC14012B
MC14012B
Dual 4−Input NAND Gate
1
OUT
A
2
IN 1
A
3
IN 2
A
4
IN 3
A
IN 4
A
6
NC
V
7
SS
NC = NO CONNECTION
14
13
12
11
105
V
DD
OUT
B
IN 4
B
IN 3
B
IN 2
B
IN 1
9
B
8
NC
10
11
12
2
3
4
1
5
9
13
NC = 6, 8
V
= PIN 14
DD
V
= PIN 7
SS
Figure 1. Pin Assignment Figure 2. Logic Diagram
ORDERING INFORMATION
Device Package Shipping
MC14012BCP PDIP−14 500 Units / Rail
MC14012BCPG PDIP−14
500 Units / Rail
(Pb−Free)
MC14012BD SOIC−14 55 Units / Rail
MC14012BDG SOIC−14
55 Units / Rail
(Pb−Free)
MC14012BDR2 SOIC−14 2500 Units / Tape & Reel
MC14012BDR2G SOIC−14
2500 Units / Tape & Reel
(Pb−Free)
MC14012BFEL SOEIAJ−14 2000 Units / Tape & Reel
MC14012BFELG SOEIAJ−14
2000 Units / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
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2
MC14012B
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
V
Characteristic
ОООООООО
Output Voltage “0” Level
V
= VDD or 0
in
ОООООООО
“1” Level
V
= 0 or V
in
ОООООООО
DD
Input Voltage “0” Level
(V
= 4.5 or 0.5 Vdc)
ОООООООО
O
= 9.0 or 1.0 Vdc)
(V
O
ОООООООО
(V
= 13.5 or 1.5 Vdc)
O
“1” Level
(V
= 0.5 or 4.5 Vdc)
O
ОООООООО
= 1.0 or 9.0 Vdc)
(V
O
ОООООООО
(V
= 1.5 or 13.5 Vdc)
O
Output Drive Current
(V
= 2.5 Vdc) Source
OH
ОООООООО
ОООООООО
ОООООООО
(V
OH
(V
OH
(V
OH
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(V
= 0.5 Vdc)
OL
ОООООООО
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
= 0)
in
ОООООООО
Quiescent Current
(Per Package)
ОООООООО
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
ОООООООО
Per Gate, C
= 50 pF)
L
Symbol
ÎÎ
V
OL
ÎÎ
V
OH
ÎÎ
V
IL
ÎÎ
ÎÎ
V
IH
ÎÎ
ÎÎ
I
OH
ÎÎ
ÎÎ
ÎÎ
I
OL
ÎÎ
I
in
C
in
ÎÎ
I
DD
ÎÎ
I
T
ÎÎ
DD
Vdc
Î
5.0
10
15
Î
5.0
10
Î
15
5.0
Î
10
Î
15
5.0
Î
10
Î
15
5.0
Î
5.0
Î
10
15
Î
5.0
10
Î
15
15
−
Î
5.0
10
Î
15
5.0
10
Î
15
Min
Î
Î
4.95
9.95
Î
14.95
Î
Î
3.5
Î
7.0
Î
11
– 3.0
Î
– 0.64
Î
– 1.6
– 4.2
Î
0.64
1.6
Î
4.2
Î
Î
ООООООООООООООО
− 55C
−
−
−
−
−
−
−
−
−
−
−
SS
)
Max
Î
0.05
0.05
0.05
Î
Î
1.5
Î
3.0
Î
4.0
Î
Î
Î
Î
Î
Î
± 0.1
Î
0.25
0.5
Î
1.0
Min
ÎÎ
−
−
−
ÎÎ
−
4.95
−
9.95
ÎÎ
−
14.95
−
ÎÎ
−
ÎÎ
−
−
−
−
−
−
−
−
−
−
−
3.5
ÎÎ
7.0
ÎÎ
11
– 2.4
ÎÎ
– 0.51
ÎÎ
– 1.3
– 3.4
ÎÎ
0.51
1.3
ÎÎ
3.4
−
−
−
ÎÎ
−
−
ÎÎ
−
IT = (0.3 A/kHz) f + IDD/N
I
= (0.6 A/kHz) f + IDD/N
T
= (0.9 A/kHz) f + IDD/N
I
T
25C
Typ
(Note 2)
Î
0
0
0
Î
5.0
10
Î
15
2.25
Î
4.50
Î
6.75
2.75
Î
5.50
Î
8.25
– 4.2
Î
– 0.88
Î
– 2.25
– 8.8
Î
0.88
2.25
Î
8.8
±0.00001
5.0
Î
0.0005
0.0010
Î
0.0015
Max
ÎÎ
0.05
0.05
0.05
ÎÎ
−
−
ÎÎ
−
1.5
ÎÎ
3.0
ÎÎ
4.0
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
± 0.1
7.5
ÎÎ
0.25
0.5
ÎÎ
1.0
Min
Î
−
−
−
Î
4.95
9.95
Î
14.95
−
Î
−
Î
−
3.5
Î
7.0
Î
11
– 1.7
Î
– 0.36
Î
– 0.9
– 2.4
Î
0.36
0.9
Î
2.4
−
−
Î
−
−
Î
−
125C
Max
Î
0.05
0.05
0.05
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
± 1.0
Î
Î
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25C.
4. To calculate total supply current at loads other than 50 pF:
) = IT(50 pF) + (CL − 50) Vfk
I
T(CL
where: I
gates per package.
is in A (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised
T
1.5
3.0
4.0
7.5
15
30
Unit
Î
Vdc
Î
−
Vdc
−
Î
−
Vdc
Î
Î
Vdc
−
Î
−
Î
−
mAdc
−
Î
−
Î
−
−
Î
−
mAdc
−
Î
−
Adc
−
pF
Î
Adc
Î
Adc
Î
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3
MC14012B
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
SWITCHING CHARACTERISTICS (Note 5) (C
= 50 pF, T
L
Characteristic
ООООООООООООО
Output Rise Time
t
= (1.35 ns/pF) CL + 33 ns
TLH
= (0.60 ns/pF) CL + 20 ns
t
ООООООООООООО
TLH
t
= (0.40 ns/PF) CL + 20 ns
TLH
ООООООООООООО
Output Fall Time
= (1.35 ns/pF) CL + 33 ns
t
THL
ООООООООООООО
t
= (0.60 ns/pF) CL + 20 ns
THL
t
= (0.40 ns/pF) CL + 20 ns
THL
ООООООООООООО
Propagation Delay Time
t
, t
PLH
ООООООООООООО
t
PLH
t
PLH
ООООООООООООО
= (0.90 ns/pF) CL + 115 ns
PHL
, t
= (0.36 ns/pF) CL + 47 ns
PHL
, t
= (0.26 ns/pF) CL + 37 ns
PHL
= 25C)
A
Symbol
ÎÎÎ
t
TLH
ÎÎÎ
ÎÎÎ
t
THL
ÎÎÎ
ÎÎÎ
t
, t
PLH
PHL
ÎÎÎ
ÎÎÎ
V
DD
Vdc
ÎÎ
5.0
ÎÎ
10
15
ÎÎ
5.0
ÎÎ
10
15
ÎÎ
5.0
ÎÎ
10
15
ÎÎ
Min
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
Typ
(Note 6)
ÎÎ
100
ÎÎ
50
40
ÎÎ
100
ÎÎ
50
40
ÎÎ
160
ÎÎ
65
50
ÎÎ
Max
ÎÎ
200
ÎÎ
100
80
ÎÎ
200
ÎÎ
100
80
ÎÎ
300
ÎÎ
130
100
ÎÎ
5. The formulas given are for the typical characteristics only at 25C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
14
DD
PULSE
GENERATOR
INPUT
*
OUTPUT
C
L
V
7
SS
*All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to V
SS
.
INVERTING
OUTPUT
NON−INVERTING
20 ns 20 ns
INPUT
t
PHL
OUTPUT
t
THL
t
PLH
t
TLH
90%
50%
10%
90%
50%
10%
90%
50%
10%
t
PLH
t
TLH
t
PHL
t
THL
Unit
Î
ns
Î
Î
ns
Î
Î
ns
Î
Î
V
0 V
V
V
V
V
DD
OH
OL
OH
OL
Figure 3. Switching Time Test Circuit and Waveforms
V
DD
14
V
DD
2, 9
3, 10
4, 11
5, 12
V
SS
SAME AS
ABOVE
*Inverter omitted
*
1, 13
7
V
SS
Figure 4. Circuit Schematic − One of Two Gates Shown
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4
MC14012B
TYPICAL B−SERIES GATE CHARACTERISTICS
5.0
4.0
3.0
2.0
DRAIN CURRENT (mA)
D
I ,
1.0
20
18
16
14
12
8.0
DRAIN CURRENT (mA)
6.0
D
I ,
4.0
2.0
N−CHANNEL DRAIN CURRENT (SINK) P−CHANNEL DRAIN CURRENT (SOURCE)
−10
−9.0
−8.0
TA = −55°C
−40°C
+85°C
0
1.0 3.0 5.04.02.00
VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc) VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)
+25°C
+125°C
−7.0
−6.0
−5.0
−4.0
DRAIN CURRENT (mA)
−3.0
D
I ,
−2.0
−1.0
0
0
−1.0 −3.0 −5.0−4.0−2.0
TA = −55°C
−40°C
+85°C
+125°C
+25°C
Figure 5. VGS = 5.0 Vdc Figure 6. VGS = − 5.0 Vdc
−50
TA = −55°C
−40°C
+25°C
10
0
0
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
5.03.01.0 108.06.04.02.0
+85°C
+125°C
9.07.0 −5.0−3.0−1.0 −10−8.0−6.0−4.0−2.0 −9.0−7.0
−45
−40
−35
−30
−25
−20
DRAIN CURRENT (mA)
−15
D
I ,
−10
−5.0
TA = −55°C
+ 25°C
0
0
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
−40°C
+85°C
+125°C
Figure 7. VGS = 10 Vdc Figure 8. VGS = − 10 Vdc
50
45
40
35
30
25
20
15
DRAIN CURRENT (mA)
D
I ,
10
5.0
− 100
− 90
− 80
TA = −55°C
−40°C
+25°C
+85°C
+125°C
0
0
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
106.02.0 2016128.04.0 1814
− 70
− 60
− 50
− 40
− 30
DRAIN CURRENT (mA)
D
I ,
− 20
− 10
TA = −55°C
−40°C
+25°C
+85°C
+125°C
0
0
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
−10−6.0−2.0
−16−12−8.0−4.0 −18−14
−20
Figure 9. VGS = 15 Vdc Figure 10. VGS = − 15 Vdc
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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5
MC14012B
A
VOLTAGE TRANSFER CHARACTERISTICS
5.0
4.0
3.0
OUTPUT VOLTAGE (Vdc)
2.0
out
V ,
1.0
0
0
16
14
12
10
8.0
6.0
OUTPUT VOLTAGE (Vdc)
4.0
out
V ,
2.0
0
0
1.0 3.0 5.04.02.0
V
2.0 6.0 108.04.0
V
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
, INPUT VOLTAGE (Vdc)
in
10
8.0
6.0
OUTPUT VOLTAGE (Vdc)
4.0
out
V ,
2.0
0
0
2.0 6.0 108.04.0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
V
, INPUT VOLTAGE (Vdc)
in
Figure 11. VDD = 5.0 Vdc Figure 12. VDD = 10 Vdc
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
The DC noise margin is defined as the input voltage range
DC NOISE MARGIN
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND,
values of the input values VIL and VIH for the output(s) to
be at a fixed voltage VO are given in the Electrical
Characteristics table. V
and VIH are presented graphically
IL
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
, INPUT VOLTAGE (Vdc)
in
Figure 13. VDD = 15 Vdc
out
V
DD
O
O
0
V
IL
V
V
V
(a) Inverting Function (b) Non−Inverting Function
V
out
V
O
V
O
V
DD
V
in
V
IH
VSS = 0 VOLTS DC
Figure 14. DC Noise Immunity
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6
V
DD
V
DD
0
V
IL
V
V
in
IH
−T−
SEATING
PLANE
14 8
17
N
HG
MC14012B
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646−06
ISSUE N
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
B
A
F
L
C
D
14 PL
0.13 (0.005)
K
J
M
M
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
0.290 0.310 7.37 7.87
M −−− 10 −−− 10
N 0.015 0.039 0.38 1.01
MILLIMETERSINCHES
−T−
SEATING
PLANE
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A−03
ISSUE G
−A−
14
1
G
D 14 PL
0.25 (0.010) A
8
−B−
P
7 PL
M
0.25 (0.010) B
7
C
R X 45
K
M
S
B
T
S
M
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
F
CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
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7
14 8
1
Z
D
e
b
0.13 (0.005)
M
E
7
A
0.10 (0.004)
H
A
1
MC14012B
PACKAGE DIMENSIONS
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 965−01
ISSUE O
L
E
E
VIEW P
M
L
DETAIL P
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Q
1
c
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5 THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MIN MAX MIN MAX
−−− 2.05 −−− 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.18 0.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
0.50
L
1.10 1.50 0.043 0.059
E
0
M
Q
0.70 0.90 0.028 0.035
1
−−− 1.42 −−− 0.056
Z
INCHES
10
10
0
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MC14012B/D
8
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