The MC10/100LVEP16 is a world class differential receiver/driver.
The device is functionally equivalent to the EL16, EP16 and LVEL16
devices. With output transition times significantly faster than the EL16
and LVEL16, the LVEP16 is ideally suited for interfacing with high
frequency and low voltage (2.5 V) sources. Single−ended CLK input
operation is limited to a VCC w 3.0 V in PECL mode, or VEE v−3.0 V
in NECL mode.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple V
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
BB
8
1
SOIC−8
D SUFFIX
CASE 751
http://onsemi.com
MARKING DIAGRAMS*
8
HVP16
AYWWX
1
8
KVP16
AYWWX
1
• 240 ps Propagation Delay
• Maximum Frequency > 4 GHz Typical
• PECL Mode Operating Range: V
with VEE = 0 V
• NECL Mode Operating Range: V
with VEE = −2.375 V to −3.8 V
• V
Output
BB
= 2.375 V to 3.8 V
CC
= 0 V
CC
• Open Input Default State
• LVDS Input Compatible
• Pb−Free Packages are Available
8
1
TSSOP−8
DT SUFFIX
CASE 948R
H = MC10
K = MC100
A = Assembly Location
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
8
HU16
ALYW
1
8
KU16
ALYW
1
L = Wafer Lot
Y = Year
W = Work Week
Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 6
1Publication Order Number:
MC10LVEP16/D
MC10LVEP16, MC100LVEP16
1
NC
2
D
3
45
V
BB
78Q
6
V
CC
QD
V
EE
Figure 1. 8−Lead Pinout (Top View) and Logic
Diagram
Table 2. ATTRIBUTES
CharacteristicsValue
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD ProtectionHuman Body Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)Level 1
Flammability RatingOxygen Index: 28 to 34UL 94 V−0 @ 0.125 in
Transistor Count167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 1. PIN DESCRIPTION
PinFunction
D*, D**ECL Data Inputs
Q, QECL Data Outputs
V
BB
V
CC
V
EE
NCNo Connect
* Pins will default LOW when left open.
**Pins will default to VCC/2 when left open.
Machine Model
Charged Device Model
Ref. Voltage Output
Positive Supply
Negative Supply
75 kW
37.5 kW
> 4 kV
> 200 V
> 2 kV
Table 3. MAXIMUM RATINGS
SymbolParameterCondition 1Condition 2RatingUnit
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
T
sol
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
PECL Mode Power SupplyVEE = 0 V6V
NECL Mode Power SupplyVCC = 0 V−6V
PECL Mode Input Voltage
NECL Mode Input Voltage
Output CurrentContinuous
VEE = 0 V
VCC = 0 V
Surge
VI v V
VI w V
CC
EE
6
−6
50
100
V
V
mA
mA
VBB Sink/Source± 0.5mA
Operating Temperature Range−40 to +85°C
Storage Temperature Range−65 to +150°C
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
Thermal Resistance (Junction−to−Case)Standard BoardSOIC−841 to 44°C/W
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
Thermal Resistance (Junction−to−Case)Standard BoardTSSOP−841 to 44°C/W
Output HIGH Voltage (Note 3)136514901615143015551680149016151740mV
Output LOW Voltage (Note 3)565740865630805930690865990mV
Input HIGH Voltage Common Mode
1.22.51.22.51.22.5V
Range (Differential Configuration)
(Notes 4, 5)
I
IH
I
IL
Input HIGH Current150150150
Input LOW CurrentDD0.5
−150
0.5
−150
0.5
−150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V.
3. All loading with 50 W to VCC − 2.0 V.
4. Do not use VBB at VCC < 3.0 V. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
5. V
Table 5. 10EP DC CHARACTERISTICS, PECL V
min varies 1:1 with VEE, V
IHCMR
input signal.
max varies 1:1 with VCC. The V
IHCMR
CC
range is referenced to the most positive side of the differential
Output HIGH Voltage (Note 7)216522902415223023552480229024152540mV
Output LOW Voltage (Note 7)136515401665143016051730149016651790mV
Input HIGH Voltage (Single Ended)209024152155248022152540mV
Input LOW Voltage (Single Ended)136516901430175514901815mV
Output Voltage Reference (Note 8)179018901990185519552055191520152115mV
Input HIGH Voltage Common Mode
1.23.31.23.31.23.3V
Range (Differential Configuration)
(Note 9)
I
IH
I
IL
Input HIGH Current150150150
Input LOW CurrentDD0.5
−150
0.5
−150
0.5
−150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V.
7. All loading with 50 W to VCC − 2.0 V.
8. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
9. V
min varies 1:1 with VEE, V
IHCMR
input signal.
max varies 1:1 with VCC. The V
IHCMR
range is referenced to the most positive side of the differential
VEE+1.20.0VEE+1.20.0VEE+1.20.0V
Range (Differential Configuration)
(Note 13)
I
IH
I
IL
Input HIGH Current150150150
Input LOW CurrentDD0.5
−150
0.5
−150
0.5
−150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with VCC.
11.All loading with 50 W to VCC − 2.0 V.
12.Single ended input CLK pin operation is limited to VEE −3.0 V in NECL mode.
13.V
min varies 1:1 with VEE, V
IHCMR
input signal.
max varies 1:1 with VCC. The V
IHCMR
range is referenced to the most positive side of the differential
Output HIGH Voltage (Note 15)135514801605135514801605135514801605mV
Output LOW Voltage (Note 15)555730900555730900555730900mV
Input HIGH Voltage Common Mode
1.23.31.23.31.23.3V
Range (Differential Configuration)
(Notes 16, 17)
I
IH
I
IL
Input HIGH Current150150150
Input LOW CurrentDD0.5
−150
0.5
−150
0.5
−150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V.
15.All loading with 50 W to VCC − 2.0 V.
16.Do not use VBB at VCC < 3.0 V. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
17.V
min varies 1:1 with VEE, V
IHCMR
input signal.
max varies 1:1 with VCC. The V
IHCMR
range is referenced to the most positive side of the differential
Output HIGH Voltage (Note 19)215522802405215522802405215522802405mV
Output LOW Voltage (Note 19)135515301700135515301700135515301700mV
Input HIGH Voltage (Single Ended)213524202135242021352420mV
Input LOW Voltage (Single Ended)135517001355170013551700mV
Output Voltage Reference (Note 20)177518751975177518751975177518751975mV
Input HIGH Voltage Common Mode
1.23.31.23.31.23.3V
Range (Differential Configuration)
(Note 21)
I
IH
I
IL
Input HIGH Current150150150
Input LOW CurrentDD0.5
−150
0.5
−150
0.5
−150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
18.Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V.
19.All loading with 50 W to VCC − 2.0 V.
20.Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
21.V
min varies 1:1 with VEE, V
IHCMR
input signal.
max varies 1:1 with VCC. The V
IHCMR
range is referenced to the most positive side of the differential
VEE+1.20.0VEE+1.20.0VEE+1.20.0V
Range (Differential Configuration)
(Note 25)
I
IH
I
IL
Input HIGH Current150150150
Input LOW CurrentDD0.5
−150
0.5
−150
0.5
−150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
22.Input and output parameters vary 1:1 with VCC.
23.All loading with 50 W to VCC − 2.0 V.
24.Single ended input CLK pin operation is limited to VEE −3.0 V in NECL mode.
25.V
min varies 1:1 with VEE, V
IHCMR
input signal.
max varies 1:1 with VCC. The V
IHCMR
range is referenced to the most positive side of the differential
IHCMR
http://onsemi.com
5
MC10LVEP16, MC100LVEP16
Table 10. AC CHARACTERISTICSV
= 0 V; VEE = −3.8 V to −2.375 V or VCC = 2.375 V to 3.8 V; V
CC
= 0 V (Note 26)
EE
−40°C25°C85°C
SymbolCharacteristic
f
max
t
PLH
t
PHL
t
SKEW
t
JITTER
V
PP
t
r
t
f
Maximum Frequency
(See Figure 2. F
,
Propagation Delay to
max
/JITTER)
Output Differential
Duty Cycle Skew (Note 27)5.0205.0205.020ps
CLOCK Random Jitter (RMS)
(See Figure 2. F
max
/JITTER)
Input Voltage Swing
(Differential Configuration)
Output Rise/Fall TimesQ, Q
(20% − 80%)
MinTy pMaxMinTypMaxMinTy pMax
Unit
> 4> 4> 4GHz
150220300170240320190260330ps
0.2< 10.2< 10.2< 1ps
150800120015080012001508001200mV
7012017080130180100150200ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
27.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
900
800
700
600
(mV)
500
OUTpp
V
400
300
200
100
0
(JITTER)
0100020003000400050006000
FREQUENCY (MHz)
Figure 2. F
max
/Jitter
9
8
7
6
5
4
3
2
1
ps (RMS)
OUT
JITTER
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6
MC10LVEP16, MC100LVEP16
Zo = 50 W
Zo = 50 W
50 W50 W
V
VTT = VCC − 2.0 V
TT
Receiver
Device
Driver
Device
QD
QD
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
DevicePackageShipping
MC10LVEP16DSOIC−898 Units / Rail
MC10LVEP16DR2SOIC−82500 / Tape & Reel
MC10LVEP16DTTSSOP−8100 Units / Rail
MC10LVEP16DTR2TSSOP−82500 / Tape & Reel
MC100LVEP16DSOIC−898 Units / Rail
MC100LVEP16DGSOIC−8
(Pb−Free)
MC100LVEP16DR2SOIC−82500 / Tape & Reel
MC100LVEP16DTTSSOP−8100 Units / Rail
MC100LVEP16DTGTSSOP−8
(Pb−Free)
MC100LVEP16DTR2TSSOP−82500 / Tape & Reel
MC100LVEP16DTR2GTSSOP−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
98 Units / Rail
100 Units / Rail
2500 / Tape & Reel
†
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7
MC10LVEP16, MC100LVEP16
Resource Reference of Application Notes
AN1405/D− ECL Clock Distribution Techniques
AN1406/D− Designing with PECL (ECL at +5.0 V)
AN1503/D−
AN1504/D− Metastability and the ECLinPS Family
AN1568/D− Interfacing Between LVDS and ECL
AN1642/D− The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
ECLinPSt I/O SPiCE Modeling Kit
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8
−Y−
−Z−
MC10LVEP16, MC100LVEP16
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AE
−X−
B
H
A
58
1
4
G
D
0.25 (0.010)Z
M
S
Y
0.25 (0.010)
C
SEATING
PLANE
SXS
M
0.10 (0.004)
M
Y
K
N
X 45
_
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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For additional information, please contact your
local Sales Representative.
MC10LVEP16/D
10
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