ON Semiconductor AR0330CS, AR0330SR User Manual

AR0330CS

AR0330CS and AR0330SR 1/3-Inch CMOS Digital Image Sensor

General Description

The AR0330CS can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 2304 x 1296 image at 30 frames per second (fps). The sensor outputs 10− or 12−bit raw data, using either the parallel or serial (MIPI) output ports.

The ON Semiconductor AR0330CS is a 1/3−inch CMOS digital image sensor with an active−pixel array of 2304 (H) x1536 (V). It can support 3.15 megapixel (2048H x 1536 V) digital still image capture and a 1080p30 +20%EIS (2304H x 1296 V) digital video mode. It incorporates sophisticated on−chip camera functions such as windowing, mirroring, column and row subsampling modes, and snapshot modes.

Table 1. KEY PARAMETERS

Parameter Typical Value

Optical Format 1/3−inch (6.0 mm)

Entire Array: 6.09 mm Still Image: 5.63 mm (4:3) HD Image: 5.82 mm (16:9)

Active Pixels 2304(H) x 1536(V): (Entire Array):

5.07 mm (H) x 3.38 mm (V) 2048(H) x 1536(V) (4:3, Still Mode) 2304(H) x 1296(V) (16:9, sHD Mode)

Pixel Size

Color Filter Array RGB Bayer

Shutter Type ERS and GRR

Input Clock Range 6 – 27 MHz

Output Clock Maximum (CLK_OP)

Responsivity 2.0 V/lux−sec

Power Consumption

SNR

MAX

Dynamic Range 69.5 dB

Supply Voltage

Operating Temperature (junction) −T

Package Options 6.28 mm x 6.65 mm CSP

I/O/Digital 1.7–1.9 V (1.8 V Nominal) or

Digital 1.7–1.9 V (1.8 V Nominal)

Analog 2.76–2.9 V

2.2 mm x 2.2 mm

98 Mp/s (Parallel, MIPI)

1080P30 MIPI Mode: 282 mW

1080P30 Parallel Mode: 252 mW

39 dB

2.4–3.1 V (2.8 V Nominal)

–30°C to + 70° C

11.43 mm x 11.43 mm PLCC

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PLCC48

11.43x11.43

CASE 776AM

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of this data sheet.

Features (continued)

ODCSP64

6.278x6.648

CASE 570BH

• 2.2 mm Pixel with ON Semiconductor

A−Pix

™ technology

• Superior Low−light Performance

• 3.5 Mp Active Array, 2.9 Mp (16:9) Video

3.4 Mp (3:2) and 3.15 Mp (4:3) Still Images

• Support for External Mechanical Shutter

• Support for External LED or Xenon Flash

• Data Interfaces: Two−lane Serial MIPI or

Parallel Interface

• On−chip phase−locked Loop (PLL)

Oscillator

• Integrated Position−based Color and Lens

Shading Correction

• Simple Two−wire Serial Interface

• Auto Black Level Calibration

• 12−to−10 bit Output A−Law Compression

• Slave Mode for Precise Frame−rate Control

and for Synchronizing Two Sensors

Applications

• 1080P30 High−definition Digital Video

Camcorder

• Web Cameras and Video Conferencing

Cameras

• Security

January, 2019 − Rev. 8

1 Publication Order Number:

AR0330CS/D

AR0330CS

ORDERING INFORMATION

Table 2. AVAILABLE PART NUMBERS

Part Number

AR0330CS1C12SPKA0−CP 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, MIPI, CSP Tray, Protective Film

AR0330CS1C12SPKA0−CR 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, MIPI, CSP Tray, No Protective Film

AR0330CSSC12SPBA0−DR 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, PLCC Tray, No Protective Film

AR0330SR1C00SUKA0−CP 3.5 MP, 1/3−inch, 0 Deg CRA, Parallel, CSP Tray, Protective Film

AR0330SR1C00SUKA0−CR 3.5 MP, 1/3−inch, 0 Deg CRA, Parallel, CSP Tray, No Protective Film

AR0330CS1C12SPKAH3−GEVB 3.5 MP, 1/3− inch, 12 Deg CRA, Parallel, MIPI, CSP Evaluation board

FUNCTIONAL OVERVIEW

The AR0330CS is a progressive−scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on−chip, phase−locked loop (PLL) that can generate all internal clocks from a single master input clock running

Ext

Clock

Analog Core

PLL

Timing

and

Control

Registers

Pixel Array

Row Drivers

Column

Amplifiers

ADC

12−bit

Product Description Orderable Product Attribute Description

between 6 and 27 MHz. The maximum CLK_OP is 98 Mp/s using MIPI serial interface and 98 Mp/s using the parallel interface.

Test Pattern

Generator

Digital Core

Row Noise Correction

Black Level Correction

Lens Shading Correction

Digital Gain

Data Pedestal

12−bit

Output Data−Path

Compression (optional)

12−bit

8, 10, or

12−bit

Two−wire serial I/F

Figure 1. Block Diagram

User interaction with the sensor is through the two−wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 3.5 Mp active− pixel sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is

Parallel I/O: PIXCLK, FV, LV, D

OUT [11:0]

Ma x 98 Mp/s

MIPI I/O: CLK P/N,

1. Two lane data paths only 2. 98 Mp/sec

Max CLK_OP 98 Mp/s

controlled by varying the time interval between reset and readout. Once a row has been read, the signal from the column is amplified in a column amplifier and then digitized in an analog−to−digital converter (ADC). The output from the ADC is a 12−bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain).

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AR0330CS

WORKING MODES

The AR0330CS sensor working modes are specified from the following aspect ratios:

Table 3. AVAILABLE ASPECT RATIOS IN THE AR0330CS SENSOR

Aspect Ratio Sensor Array Usage

3:2 Still Format #1 2256(H) x 1504(V)

4:3 Still Format #2 2048 (H) x 1536 (V)

16:10 Still Format #3 2256 (H) x 1440 (V)

16:9 FHD Format 2304 (H) x 1296 (V)

The AR0330CS supports the following working modes. To operate the sensor at full speed 98Mp/s the sensor must

operate at full−speed (98 Mp/s) when using the parallel interface.

use 2−Lane MIPI or parallel interface. The sensor will

Table 4. AVAILABLE WORKING MODES IN THE AR0330CS SENSOR

Active

Readout

Mode Aspect Ratio

1080p + EIS 16:9 2304 x 1296 2304 x 1296 30 30 – 100%

3M Still

WVGA + EIS 16:9 2304 x 1296 1152 x 648 60 60 2 x 2 100%

4:3 2048 x 1536 2048 x 1536 30 25 – 100%

3:2 2256 x 1504 2256 x 1504 30 25 – 100%

Window

Sensor Output

Resolution

FPS

(2 lane MIPI,

12 bit)

FPS (Parallel

Interface)

Subsampling FOV

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Digital

I/O

power

AR0330CS

Digital

Core

power

PLL

power

Analog power

Analog

power

Master clock

(6–27MHz)

From

controller

3, 4

1.5kΩ

3, 4

VDD_IO

1.5kΩ

EXTCLK

TRIGGER

SADDR

SCLK

SDATA

RESET_BAR

TEST

VDD_IO VDD_PLLVDD

0.1 μF10 μF

VDD

VAA VAA_PIX

DATA1_P

V DD_MIPI

VDD_PLL

DATA1_N

DATA2_P

DATA2_N

CLK_P

CLK_N

To controller (MIPI − serial interface)

SHUTTER

FLASH

GND AGND

Digital

ground

0.1 μF10 μF

10 μF

0.1 μF

Analog ground

VAA

0.1 μF10 μF

10 μF

VAA_PIX

0.1 μF

1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 10 mF and 0.1 mF decoupling capacitors for every power supply. If space is a concern, then priority must be given in the following order: V

DD. Actual values and results may vary depending on layout and design considerations.

and V

AA, VAA_PIX, VDD_PLL, VDD_MIPI, VDD_IO,

2. To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the pads as possible. In addition, place a 10 mF capacitor for each supply off−module but close to each supply.

3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.

4. The pull−up resistor is not required if the controller drives a valid logic level on S

CLK at all times.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized.

6. TEST pin must be tied to D

7. ON Semiconductor recommends that GND_MIPI be tied to D

DD_MIPI is tied to VDD_PLL in the CSP package. ON Semiconductor strongly recommends that VDD_MIPI must be connected to a

8. V

DD_PLL in a module design since VDD_PLL and VDD_MIPI are tied together in the die.

GND for the MIPI configuration.

GND.

9. The package pins or die pads used for the parallel interface must be left floating.

10.If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.

11.If the TRIGGER or OE_BAR pin or pad is not used, then it should be tied to D

GND.

Figure 2. Typical Configuration: Serial MIPI

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Master clock

(6–27 MHz)

From

Controller

3, 4

AR0330CS

Digital

core

I/O

power

VDD_IO

3, 4

1.5k

VDD

EXTCLK

OE_BAR

TRIGGER

SADDR

SCLK SDATA

RESET_BAR

TEST

PLL

GND

power

V DD_PLL

VDD_MIPI

Analog

power

VAA_PIX

VAA

DOUT [11:0]

PIXCLK

LINE_VALID

FRAME_VALID

FLASH

SHUTTER

AGND

To controller

10 μF

DD_IO VDD_PLLVDD

0.1 μF

10 μF

Digital

ground

10 μF

0.1 μF

10 μF

Analog ground

0.1 μF

VAA

VAA_PIX

10 μF0.1 μF

0.1 μF

12.All power supplies must be adequately decoupled. ON Semiconductor recommends having 10 mF and 0.1 mF decoupling capacitors for every power supply. If space is a concern, then priority must be given in the following order: V

AA, VAA_PIX, VDD_PLL, VDD_IO, and VDD.

Actual values and results may vary depending on layout and design considerations.

13.To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the pads as possible. In addition, place a 10 mF capacitor for each supply off−module but close to each supply.

14.ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.

15.The pull−up resistor is not required if the controller drives a valid logic level on S

CLK at all times.

16.ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized.

17.TEST pin should be tied to the ground.

18.The data and clock package pins or die pads used for the MIPI interface must be left floating.

19.The V

DD_MIPI package pin and sensor die pad should be connected to a 2.8 V supply as it is tied to the VDD_PLL supply both in the

package routing and also within the sensor die itself.

20.If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.

21.If the TRIGGER or OE_BAR pin or pad is not used, then it should be tied to D

GND.

Figure 3. Typical Configuration: Parallel Pixel Data Interface

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AR0330CS

PIN DESCRIPTIONS

Table 5. PIN DESCRIPTIONS

Name Type Description

RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default

EXTCLK Input Master input clock, range 6 − 27 MHz

TRIGGER Input Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame

SADDR Input Two−wire serial address select

SCLK Input Two−wire serial clock input

TEST Input Enable manufacturing test modes. Tie to DGND for normal sensor operation

OE_BAR Input Parallel port output enable, active low

SDATA I/O Two−wire serial data I/O

PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock

DOUT[11:0] Output Parallel pixel data output

FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used

FRAME_VALID Output Asserted when DOUT data is valid

LINE_VALID Output LINE_VALID output asserted when DOUT data is valid

SHUTTER Output Control for external mechanical shutter. Can be left floating if not used

DATA1_P Output MIPI serial data, lane 1, differential P

DATA1_N Output MIPI serial data, lane 1, differential N

DATA2_P Output MIPI serial data, lane 2, differential P

DATA2_N Output MIPI serial data, lane 2, differential N

CLK_P Output Output MIPI serial clock, differential P

CLK_N Output Output MIPI serial clock, differential N

VDD_MIPI Power MIPI power supply

VAAHV_NPIX Power Power supply pin used to program the sensor OTPM (one−time programmable memory). This pin

VDD Power Digital power

VDD_IO Power IO supply power

VDD_PLL Power PLL power supply

DGND Power Digital GND

VAA Power Analog power

VAA_PIX Power Pixel power

AGND Power Analog GND

should be open if OTPM is not used

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AR0330CS

Table 6. AR0330CS CSP (PARALLEL/MIPI) PACKAGE PINOUT

1 2 3 4 5 6 7 8

22.NC = Do not connect. For manufacturing test purpose only.

VAA VAAHV_NPIX AGND NC VAA_PIX VAA VDD_IO VDD

VDD SDATA FRAME_VALID DGND AGND DGND TEST SHUTTER

SADDR FLASH LINE_VALID DGND DGND DGND TRIGGER RESET_BAR

SCLK VDD_IO DOUT10 DGND VDD_IO VDD_IO EXTCLK DATA_N

PIXCLK DOUT11 DOUT9 DOUT7 VDD_IO DGND CLK_N DATA_P

– – DOUT8 DOUT6 DOUT4 VDD_IO CLK_P VDD_PLL

DGND VDD DOUT5 DOUT3 DOUT1 DOUT0 DATA2_N VDD

– DGND DGND DOUT2 VDD_IO VDD_MIPI DATA2_P VDD_MIPI

Table 7. AR0330SR CSP (PARALLEL) PACKAGE PINOUT

1 2 3 4 5 6 7 8

VAA VAAHV_NPIX AGND NC VAA_PIX VAA VDD_IO VDD

VDD SDATA FRAME_VALID DGND AGND DGND TEST SHUTTER

SADDR FLASH LINE_VALID DGND DGND DGND TRIGGER RESET_BAR

SCLK VDD_IO DOUT10 DGND VDD_IO VDD_IO EXTCLK –

PIXCLK DOUT11 DOUT9 DOUT7 VDD_IO DGND – –

– – DOUT8 DOUT6 DOUT4 VDD_IO – VDD_PLL

DGND VDD DOUT5 DOUT3 DOUT1 DOUT0 – VDD

23.NC = Do not connect. For manufacturing test purpose only.

– DGND DGND DOUT2 VDD_IO VDD_PLL – VDD_PLL

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AR0330CS

GND

DD_IO 7

DD_IO 8

CLK 9

ADDR 10

EXTCLK 11

PIXCLK 12

FLASH 13

DATA 14

FRAME_VALID 15

LINE_VALID 16

OUT 11 17

DOUT10 18

6 DGND

5 DGND

4 VDD

3 VDD

2 D

1 V DD _PLL

48 AGND

47 AGND

46 VAA

45 VAA

44 VAA

43 AGND

42 AGND

41 VAA_PIX

AA_PIX

40 V

39 AGND

38 AGND

37 NC

AA HV_NPIX

36 V

35 NC

34 V

33 TRIGGER

32 OE_BAR

31 TEST

OUT 9 19

OUT 4 24

OUT 5 23

OUT 6 22

OUT 7 21

OUT 8 20

TOP VIEW

Figure 4. PLCC Pinout

Table 8. AR0330CS PLCC PACKAGE THERMAL RESISTANCE

Junction to ambient air thermal resistance (qJA) (°C/W)

Junction to board thermal resistance (qJB) (°C/W)

OUT 3 25

NC 29

OUT 0 28

OUT 1 27

OUT 2 26

RESET_BAR 30

Using JEDEC 1S0P Board Using JEDEC 2S2P Board

51.47 36.92

22.16 21.73

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AR0330CS

SENSOR INITIALIZATION

Power−Up Sequence

The recommended power−up sequence for the AR0330CS is shown in Figure 5. The available power supplies (V must have the separation specified below.

DD_IO, VDD_PLL, VDD_MIPI, VAA, VAA_PIX)

1. Turn on V

2. After 100 μs, turn on V

DD_PLL and VDD_MIPI power supplies

AA and VAA_PIX power

supply

3. After 100 μs, turn on V

4. After 100 μs, turn on V

DD power supply DD_IO power supply

5. After the last power supply is stable, enable EXTCLK

6. Assert RESET_BAR for at least 1ms

_MIPI (2.8)

(2.8)

7. Wait 150,000 EXTCLKs (for internal initialization into software standby

8. Write R0x3052 = 0xA114 to configure the internal register initialization process

9. Write R0x304A = 0x0070 to start the internal register initialization process

10. Wait 150,000 EXTCLK periods

11. Configure PLL, output, and image settings to desired values

12. Wait 1 ms for the PLL to lock

13. Set streaming mode (R0x301A[2] = 1)

(1.8)

_IO (1.8/2.8)

EXTCLK

RESET_BAR

24.A software reset (R0x301A[0] = 1) is not necessary after the procedure described above since a Hard Reset will automatically triggers a software reset. Independently executing a software reset, should be followed by steps seven through thirteen above

25.The sensor must be receiving the external input clock (EXTCLK) before the reset pin is toggled. The sensor will begin an internal initialization sequence when the reset pin toggle from LOW to HIGH. This initialization sequence will run using the external input clock. Power on default state is software standby state, need to apply two−wire serial commands to start streaming. Above power up sequence is a general power up sequence. For different interface configurations, MIPI, and Parallel, some power rails are not needed. Those not needed power rails should be ignored in the general power up sequence..

Software

Standby PLL Clock

Figure 5. Power Up

Table 9. POWER−UP SEQUENCE

Definition Symbol Min Ty p Max Unit

VDD_PLL, VDD_MIPI to VAA/VAA_PIX (Note 28)

VAA/VAA_PIX to VDD t1 0 100 –

VDD to VDD_IO t2 0 100 –

External clock settling time tx – 30 (Note 26) – ms

Hard Reset t3 1 (Note 27) – – ms

Internal Initialization t4 150000 – – EXTCLKs

Internal Initialization t5 150000 – – EXTCLKs

PLL Lock Time t6 1 – – ms

t0 0 100 –

Streaming

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AR0330CS

26.External clock settling time is component−dependent, usually taking about 10 – 100 ms.

27.Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time.

28.It is critical that V others. If the case happens that V current draw on this supply.

DD_MIPI is tied to VDD_PLL in the CSP package and must be powered to 2.8 V.

29.V

Power−Down Sequence

The recommended power−down sequence for the AR0330CS is shown in Figure 6. The available power supplies (V must have the separation specified below.

1. Disable streaming if output is active by setting standby R0x301a[2] = 0

VDD_HiSPi_TX (0.4)

_IO (1.8/2.8)

DD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the

DD_PLL is powered after other supplies then sensor may have functionality issues and will experience high

2. The soft standby state is reached after the current row or frame, depending on configuration, has

DD_IO, VDD_PLL, VDD_MIPI., VAA, VAA_PIX)

ended

3. Turn off V

4. Turn off V

DD_IO

5. Turn off VAA/VAA_PIX

_HiSPi (1.8)

6. Turn off V

DD_PLL, VDD_MIPI

VAA_PIX, VAA (2.8)

_MIPI (2.8)

EXTCLK

Power Down until Next

Power Up Cycle

Figure 6. Power Down

Table 10. POWER−DOWN SEQUENCE

Definition Symbol Minimum Typical Maximum Unit

VDD_IO t0 0 – –

VDD_IO to VDD t1 0 – –

VDD to VAA/VAA_PIX t2 0 – –

VAA/VAA_PIX to VDD_PLL t3 0 – –

PwrDn until Next PwrUp Time t4 100 – – ms

30.t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.

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STANDBY MODE

AR0330CS

Soft Standby

1. Disable streaming by setting standby R0x301a[2] = 0

2. Delay 10 ms

3. Stop EXTCLK; pull EXTCLK pin LOW

Hard Standby

1. Disable streaming by setting standby R0x301a[2] = 0

2. Delay 10 ms

3. Pull RESET_BAR to LOW

ELECTRICAL CHARACTERISTICS

Table 11. DC Electrical Definitions and Characteristics (MIPI Mode)

EXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;

DD_PLL = 2.8 V; Output load = 68.5 pF; T

Definition

Core digital voltage VDD 1.7 1.8 1.9 V

I/O digital voltage VDD_IO

Analog voltage VAA 2.76 2.8 2.9 V

Pixel supply voltage VAA_PIX 2.76 2.8 2.9 V

PLL supply voltage VDD_PLL 2.7 2.8 2.9 V

MIPI supply voltage VDD_MIPI 2.7 2.8 2.9 V

Digital operating current − 114 − mA

I/O digital operating current − 0 − mA

Analog operating current − 41 − mA

Pixel supply current − 9.9 − mA

PLL supply current − 15 − mA

MIPI digital operating current − 35 − mA

= 60°C; Data Rate = 588 Mbps; DLL set to 0; 2304 x 1296 at 30 fps

Symbol Min Typ Max Unit

1.7 1.8 1.9 V

2.4 2.8 3.1 V

Table 12. DC Electrical Definitions and Characteristics (Parallel Mode)

= 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;

EXTCLK

DD_PLL = 2.8 V; Output load = 68.5 pF; TJ = 60°C; 2304 x 1296 at 30 fps

Definition

Core digital voltage VDD 1.7 1.8 1.9 V

I/O digital voltage VDD_IO

Analog voltage VAA 2.76 2.8 2.9 V

Pixel supply voltage VAA_PIX 2.76 2.8 2.9 V

PLL supply voltage VDD_PLL 2.7 2.8 2.9 V

Digital operating current I(VDD) 66.5 75 mA

I/O digital operating current I(VDD_IO) 24 35 mA

Analog operating current I(VAA) 36 44 mA

Pixel supply current I(VAA_PIX) 10.5 18 mA

PLL supply current I(VDD_PLL) 6 11 mA

Symbol Min Typ Max Unit

1.7 1.8 1.9 V

2.4 2.8 3.1 V

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AR0330CS

Table 13. STANDBY POWER

= 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;

EXTCLK

DD_PLL = 2.8 V; Output load = 68.5 pF; TJ = 60°C

Power Typical Max Unit

Hard Standby (CLK OFF)

Soft Standby (CLK OFF)

Soft Standby (CLK ON)

Table 14. ABSOLUTE MAXIMUM RATINGS

Symbol Definition Min Max Unit

VDD_MAX Core digital voltage –0.3 2.4 V

VDD_IO_MAX I/O digital voltage –0.3 4 V

VAA_MAX Analog voltage –0.3 4 V

VAA_PIX Pixel supply voltage –0.3 4 V

VDD_PLL PLL supply voltage –0.3 4 V

VDD_MIPI MIPI supply voltage –0.3 4 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

31.Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Digital 19.8 35.8

Analog 5.8 7.0

Digital 23.5 39.7

Analog 5.4 5.9

Digital 15700 16900

Analog 5.5 5.7

Storage temperature –40 85 °C

SCLK

DATA

SCLK

SDATA

SRTH

SCLK

Write Address

Bit 7

SDH

SDS

Write Address

Bit 0

Write Start ACK

SHAR

Read Address

Bit 7

Read Address

Bit 0

Read Start

Figure 7. Two−Wire Serial Bus Timing Parameter

SHAW

ACK

tr_clk tf_clk

90%

10%

AHSW t

Bit 7

AHSR

Bit 7

SDHR

SDSR

Bit 0

90%

10%

STPS

tf_sdattr_sdat

STPH

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AR0330CS

Table 15. TWO−WIRE SERIAL BUS CHARACTERISTICS

= 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25°C

EXTCLK

Standard Mode Fast Mode

Parameter

SCLK Clock Frequency f

Symbol

SCL

Hold time (repeated) START condition

After this period, the first clock pulse is generated

LOW period of the SCLK clock t

HD;STA

LOW

HIGH period of the SCLK clock tHIGH 4.0 − 0.6 −

Set−up time for a repeated START condi-

tSU;STA 4.7 − 0.6 −

tion

Data hold time tHD;DAT 0

Data set−up time tSU;DAT 250 − 100

Rise time of both SDATA and SCLK signals tr − 1000 20 + 0.1Cb

Fall time of both SDATA and SCLK signals tf − 300 20 + 0.1Cb

Set−up time for STOP condition tSU;STO 4.0 − 0.6 − ?s

Bus free time between a STOP and START

tBUF 4.7 − 1.3 − ?s

condition

Capacitive load for each bus line Cb − 400 − 400 pF

Serial interface input pin capacitance C

SDATA max load capacitance C

IN_SI

LOAD_SD

SDATA pull−up resistor RSD 1.5 4.7 1.5 4.7 K?

32.This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

33.Two−wire control is I

34.All values referred to V

35. A device must internally provide a hold time of at least 300 ns for the S

36.The maximum

37.A Fast−mode I

C−compatible.

= 0.9 VDD and V

IHmin

HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.

C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU; DAT 250 ns must then be met.

= 0.1VDD levels. Sensor EXCLK = 27 MHz.

ILmax

This will automatically be the case if the device does not stretch the LOW period of the S period of the S Standard−mode I

CLK signal, it must output the next data bit to the SDATA line

C−bus specification) before the SCLK line is released.

38.Cb = total capacitance of one bus line in pF.

Min Max Min Max

0 100 0 400 KHz

4.0 − 0.6 −

4.7 − 1.3 −

3.45

0.9

− ns

300 ns

− 3.3 − 3.3 pF

− 30 − 30 pF

DATA signal to bridge the undefined region of the falling edge of SCLK.

r max + tSU;DAT = 1000 + 250 = 1250 ns (according to the

CLK signal. If such a device does stretch the LOW

Unit

Table 16. I/O PARAMETERS

EXTCLK = 24 MHz; VDD = 1.8V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output load = 68.5 pF; TJ = 60°C; CLK_OP = 98 MPixel/s

Symbol Definition Conditions Min Max Units

VIH Input HIGH voltage

VDD_IO = 1.8 V 1.4

VDD_IO + 0.3

VDD_IO = 2.8 V 2.4

VIL Input LOW voltage

VDD_IO = 1.8 V GND – 0.3 0.4

VDD_IO = 2.8 V GND – 0.3 0.8

IIN Input leakage current No pull−up resistor; VIN = VDD OR DGND –20 20

VOH Output HIGH voltage At specified IOH VDD_IO − 0.4V – V

VOL Output LOW voltage At specified IOL – 0.4 V

IOH Output HIGH current At specified VOH – –12 mA

IOL Output LOW current At specified VOL – 9 mA

IOZ Tri−state output leakage current – 10

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AR0330CS

EXTCLK

90 %

10 %

90 %

10 %

EXTCLK

PIXCLK

FRAME_VALID trails LINE_VALID by 16 PIXCLKs.

Data[11:0]

AME_VALID/

LINE_VALID

*PLL disabled for

Pxl _ 0 Pxl _ 1 Pxl _ 2 Pxl _ n

PFH

PLH

FRAME_VALID leads LINE_VALID by 609 PIXCLKs.

Figure 8. I/O Timing Diagram (Parallel Mode)

Table 17. I/O TIMING

EXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V;

Output load = 68.5 pF; T

Symbol

fEXTCLK Input clock frequency PLL enabled 6 24 27 MHz

tEXTCLK Input clock period PLL enabled 166 41 20 ns

tR Input clock rise time 0.1 – 1 V/ns

tF Input clock fall time 0.1 – 1 V/ns

Clock duty cycle 45 50 55 %

tJITTER Input clock jitter – – 0.3 ns

Output pin slew Fastest CLOAD = 15 pF – 0.7 – V/ns

fPIXCLK PIXCLK frequency Default – 80 – MHz

tPD PIXCLK to data valid Default – – 3 ns

tPFH PIXCLK to FRAME_VALID HIGH Default – – 3 ns

tPLH PIXCLK to LINE_VALID HIGH Default – – 3 ns

tPFL PIXCLK to FRAME_VALID LOW Default – – 3 ns

tPLL PIXCLK to LINE_VALID LOW Default – – 3 ns

= 60°C; CLK_OP = 98 MPixel/s

Definition Conditions Min Typ Max Units

PFL

PLL

Table 18. PARALLEL I/O RISE SLEW RATE

EXTCLK = 24 MHz; VDD = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output load = 68.5 pF;

= 60°C; CLK_OP = 98 MPixel/s

Parallel Slew Rate (R0x306E[15:13])

DD_IO

0 1 2 3 4 5 6 7

1.70V 0.069 0.115 0.172 0.239 0.325 0.43 0.558 0.836

1.80V 0.078 0.131 0.195 0.276 0.375 0.507 0.667 1.018

1.95V 0.093 0.156 0.233 0.331 0.456 0.62 0.839 1.283

2.50V 0.15 0.252 0.377 0.539 0.759 1.07 1.531 2.666

2.80V 0.181 0.305 0.458 0.659 0.936 1.347 1.917 3.497

3.10V 0.212 0.361 0.543 0.78 1.114 1.618 2.349 4.14

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Units

V/ns

ELECTRICAL DEFINITIONS

Figure 9 is the diagram defining differential amplitude

, V

Single−ended signal

and rise and fall times. To measure VOD and

CM,

use the DC test circuit shown in Figure 10 and set the

o a

o b

Differential signal

0 V

O D_ A C

diff

o b

O D

– V

o a

AR0330CS

MIPI PHY to constant Logic 1 and Logic 0. Measure V V

and VCM with voltmeters for both Logic 1 and Logic 0.

diff

O D

o a

_ pkpk

– V

= (V

C M

8 0%

o b

2 0%

o a

+ V

o b

) / 2

Figure 9. Single−Ended and Differential Signals

o a

o b

5 0 Ω

C M

Figure 10. DC Test Circuit

VOD(m) +ŤVoa(m) * Vob(m)Ťwhere ȀmȀ is either ″ 1″ for logic 1 or ″ 0″ for logic 0

(1) ) VOD(0)

+ VOD(1) ) VOD(0)

diff

DVOD+ŤVOD(1) * VOD(0)

(eq. 1)

(eq. 2)

(eq. 3)

(eq. 4)

(1) ) VCM(0)

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(eq. 5)

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ON Semiconductor AR0330CS, AR0330SR User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual