ON Semiconductor AND9902, AX5045 User Manual

AND9902/D

AX5045 Programming

Manual

Ultra-Low Power Narrow-Band Sub GHz (60−1050 MHz) RF Transceiver with Integrated +23 dBm High Power Amplifier

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OVERVIEW

AX5045 is a true single chip low-power CMOS transceiver for narrow band applications. A fully integrated VCO support most carrier frequencies from 60 MHz to 1050 MHz. The on-chip transceiver consists of a fully integrated RF front-end with modulator, and demodulator. Base band data processing is implemented in an advanced and flexible communication controller that enables user friendly communication via the SPI interface.

APPLICATION NOTE

An on-chip low power oscillator as well as Wake-on-radio enable very low power standby applications. Figure 1 shows the block diagram of the AX5045.

<![if ! IE]> <![endif]>GPADC1

<![if ! IE]> <![endif]>GPADC2

<![if ! IE]> <![endif]>DATA

<![if ! IE]> <![endif]>DCLK

25

26

AX5045

11

12

RX_P

5

Mixer

Digital IF

De-

ADC

channel

<![if ! IE]> <![endif]>erControllRadioll

<![if ! IE]> <![endif]>packetandtiming packettiminghandling

<![if ! IE]> <![endif]>ErrorForward Correction

Modulator

<![if ! IE]> <![endif]>Encoder

<![if ! IE]> <![endif]>Framing

<![if ! IE]> <![endif]>FIFO

IF Filter &

filter

modulator

LNA

RX_N

6

AGC PGAs

AGC

TX_P

3

TX_N

4

PA

VCHOKE

<![if ! IE]> <![endif]>Voltage

<![if ! IE]> <![endif]>Regulator

27

Chip configuration

VDD_IO

FOUT

Communication Controller &

Serial Interface

1,23

POR

FXTAL

RF Frequency

References

Registers

Generation

Subsystem

Low Power

SPI

RF Output

Oscillator

Wake on Radio

640 Hz/10kHz

60 MHz –

1.05 GHz

Crystal

Oscillator

Divider

typ.

16 MHz

Voltage

Regulator

27

19

20

21

28

13

8

7

23,1

14

15

16 17

<![if ! IE]> <![endif]>CLKP

<![if ! IE]> <![endif]>CLKN

<![if ! IE]> <![endif]>SYSCLK

<![if ! IE]> <![endif]>FILT

<![if ! IE]> <![endif]>VDD ANA

<![if ! IE]> <![endif]>VDD IO

<![if ! IE]> <![endif]>IRQ

<![if ! IE]> <![endif]>PWRAMP

<![if ! IE]> <![endif]>ANTSEL

<![if ! IE]> <![endif]>SEL

<![if ! IE]> <![endif]>CLK

<![if ! IE]> <![endif]>MISO

<![if ! IE]> <![endif]>MOSI

Figure 1. Functional Block Diagram of the AX5045

♥ Semiconductor Components Industries, LLC, 2019	1	Publication Order Number:
March, 2021 − Rev. 1		AND9902/D

AND9902/D

Table of Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Programming the Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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AND9902/D

Connecting the AX5045 to an AX8052F100 or other Microcontroller

The AX5045 can easily be connected to an AX8052F100 or any other microcontroller. The microcontroller communicates with the AX5045 via a register file that is implemented in the AX5045 and that can be accessed serially via an industry standard Serial Peripheral Interface (SPI) protocol.

Reset is performed by the integrated power-on-reset (POR) block and can be performed manually via the register file.

The AX5045 sends and receives data via the SPI port in frames. This standard operation mode is called frame mode.

In frame mode, the internal communication controller performs frame delimiting, and data is received and transmitted via a 256 Byte FIFO, accessible via the register file. The FIFO is shared between receive and transmit. Figure 2 shows the corresponding diagram. Connecting the interrupt line is highly recommended, though not strictly required. It is also recommended to connect the SYSCLK line, which can be programmed to provide a copy of the precise crystal clock of the AX5045. Once set up, the Microcontroller can directly run on that clock or use it to calibrate its internal oscillators.

			<![if ! IE]> <![endif]>CLKP			<![if ! IE]> <![endif]>CLKN		<![if ! IE]> <![endif]>GPADC2		<![if ! IE]> <![endif]>GPADC1		<![if ! IE]> <![endif]>NC		<![if ! IE]> <![endif]>VDD IO			<![if ! IE]> <![endif]>NC
			28			27		26		25		24		23			22
VDD_IO						AX5045
	1
VCHOKE
	2
TX_P
	3
TX_N									GND
	4							center pad
RX_P	5
RX_N
	6
VDD_ANA
	7
	8			9			10		11			12		13	14
			<![if ! IE]> <![endif]>FILT			<![if ! IE]> <![endif]>NC		<![if ! IE]> <![endif]>NC		<![if ! IE]> <![endif]>DATA		<![if ! IE]> <![endif]>DCLK		<![if ! IE]> <![endif]>SYSCLK		<![if ! IE]> <![endif]>SEL

21	ANTSEL
20	PWRAMP
19	IRQ	IRQ	RIRQ/PR5
18	NC		VDD_CORE
17	MOSI	MOSI	RMOSI/PR4
16	MISO	MISO	RMISO/PR3
15	CLK	CLK	RCLK/PR2
		SEL	RSEL/PR0
		SYSCLKRSYSCLK/PR1

		<![if ! IE]> <![endif]>PA5/ADC5/IC0/U1TX/COMPI10	<![if ! IE]> <![endif]>PA4/ADC4/T1CLK/COMPO0/LPXTA	<![if ! IE]> <![endif]>PA3/ADC3/T1OUT/LPXTALP	<![if ! IE]> <![endif]>PA2/ADC2/OC0/U1RX/COMPI00	<![if ! IE]> <![endif]>PA1/ADC1/T0CLK/OC1/XTALP	<![if ! IE]> <![endif]>PA0/ADC0/T0OUT/IC1/XTALN	<![if ! IE]> <![endif]>VDD IO
	28		27	26	25	24	23	22
1									21	RESET_N
2									20	DBG_EN
3		AX8052F100							19	PB7/DBG_CLK
4					or				18	PB6/DBG_DATA
5			other			mC			17	PB5/U0RX/T1OUT
6									16	PB4/U0TX/T1CLK
7									15	PB3/OC0/T2CLK/EXTIRQ1/DSWAKE
	8		9	10	11	12	13	14
		<![if ! IE]> <![endif]>OMPO0/U0RX/SMISO/PC3	<![if ! IE]> <![endif]>U0TX/SMOSI/PC2	<![if ! IE]> <![endif]>OMPO1/T0CLK/SSCK/PC1	<![if ! IE]> <![endif]>XTIRQ0/T0OUT/SSEL/PC0	<![if ! IE]> <![endif]>EXTIRQ0/IC1/U1TX/PB0	<![if ! IE]> <![endif]>OC1/U1RX/PB1	<![if ! IE]> <![endif]>T2OUT/IC0/PB2

Figure 2. Connecting AX5045 to AX8052F100 or other mC

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				AND9902/D
Pin Function Descriptions
Table 1. PIN FUNCTION DESCRIPTION
Symbol	Pin(s)		Type	Description
VDD_IO	1		P	Power supply 3.0 V – 3.6 V
VCHOKE	2		P	Regulator Output to External PA choke inductors
TX_P	3		A	Differential TX antenna output
TX_N	4		A	Differential TX antenna output
RX_P	5		A	Differential RX antenna input
RX_N	6		P	Differential RX antenna input
VDD_ANA	7		P	Analog power output, decoupling
FILT	8		A	Optional synthesizer filter
NC	9		A	Not used
NC	10		A	Not used
DATA	11		I/O	In wire mode: Data input/output
				Can be programmed to be used as a general purpose I/O pin Selectable
				internal 65 kW pull−up resistor
DCLK	12		I/O	In wire mode: Clock output
				Can be programmed to be used as a general purpose I/O pin Selectable
				internal 65 kW pull−up resistor
SYSCLK	13		I/O	Default functionality: Crystal oscillator (or divided) clock output Can be pro-
				grammed to be used as a general purpose I/O pin Selectable internal 65 kW
				pull−up resistor
SEL	14		I	Serial peripheral interface select
CLK	15		I	Serial peripheral interface clock
MISO	16		O	Serial peripheral interface data output
MOSI	17		I	Serial peripheral interface data input
NC	18		N	Must be left unconnected
IRQ	19		I/O	Default functionality: Transmit and receive interrupt
				Can be programmed to be used as a general purpose I/O pin Selectable
				internal 65 kW pull−up resistor
PWRAMP	20		I/O	Default functionality: Power amplifier control output
				Can be programmed to be used as a general purpose I/O pin Selectable
				internal 65 kW pull−up resistor
ANTSEL	21		I/O	Default functionality: Diversity antenna selection output
				Can be programmed to be used as a general purpose I/O pin Selectable
				internal 65 kW pull−up resistor
NC	22		N	Must be left unconnected
VDD_IO	23		P	Power supply 3.0 V – 3.6 V
NC	24		N	Must be left unconnected
GPADC1	25		A	GPADC input, must be connected to GND if not used
GPADC2	26		A	GPADC input, must be connected to GND if not used
CLKN	27		A	Crystal oscillator input/output. Leave unconnected when using TCXO
CLKP	28		A	Crystal oscillator input/output. TCXO input.
GND	Center pad		P	Ground on center pad of QFN, must be connected

NOTE: All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible and 5 V tolerant. A = analog input

I = digital input signal O = digital output signal

I/O = digital input/output signal N = not to be connected

P = power or ground

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SPI Register Access

Registers are accessed via a synchronous Serial Peripheral Interface (SPI). Most Registers are 8 bits wide and accessed using the waveforms as detailed in Figure 3. These

waveforms are compatible to most hardware SPI master controllers, and can easily be generated in software. MISO changes on the falling edge of CLK, while MOSI is latched on the rising edge of CLK.

SS

SCK

MOSI

R/W 1

1

1

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

MISO

S14

S13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

S1

S0

D7

D6

D5

D4

D3

D2

D1

D0

Figure 3. SPI 8bit Long Address Read/Write Access

The most important registers are at the beginning of the address space, i.e. at addresses less than 0x70. These

registers can be accessed more efficiently using the short address form, which is detailed in Figure 4.

Figure 4. SPI 8bit Read/Write Access

Some registers are longer than 8 bits. These registers can be accessed more quickly than by reading and writing individual 8 bit parts. This is illustrated in Figure 5. Accesses are not limited by 16 bits either, reading and writing data

bytes can be continued as long as desired. After each byte, the address counter is incremented by one. Also, this access form also works with long addresses.

SS

SCK

MOSI

R/W A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

MISO

S14

S13

S12

S11

S10

S9

S8

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

A

A+1

Figure 5. SPI 16bit Read/Write Access

During the address phase of the access, the chip outputs the most important status bits. This feature is designed to speed up software decision on what to do in an interrupt

handler. The table below shows which register bit is transmitted during the status timeslots.

Table 2. SPI STATUS BITS

SPI Bit Cell	Status	Register Bit
0	−	1 (when transitioning out of deep sleep, this bit transitions from 0→1 when the power becomes ready)
1	S14	PLL LOCK
2	S13	FIFO OVER
3	S12	FIFO UNDER
4	S11	THRESHOLD FREE ( FIFO Free > FIFO threshold)
5	S10	THRESHOLD COUNT (FIFO count > FIFO threshold)
6	S9	FIFO FULL
7	S8	FIFO EMPTY
8	S7	PWRGOOD (not BROWNOUT)
9	S6	PWR INTERRUPT PENDING
10	S5	RADIO EVENT PENDING
11	S4	XTAL OSCILLATOR RUNNING

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AND9902/D

Table 2. SPI STATUS BITS (continued)

SPI Bit Cell	Status	Register Bit

12S3 WAKEUP INTERRUPT PENDING

13S2 LPOSC INTERRUPT PENDING

14S1 GPADC INTERRUPT PENDING

15S0 undefined

Note that bit cells 8−15 (S7…S0) are only available in two address byte SPI access formats.

Deep Sleep

The chip can be programmed into deep sleep mode. In deep sleep mode, the chip is completely switched off, which results in very low leakage power. All registers loose their programming.

To enter deep sleep mode, write the deep sleep encoding into bits 3:0 of PWRMODE. At the rising edge of the SEL line, the chip will enter deep sleep mode.

To exit deep sleep mode, lower the SEL line. This will initiate startup and reset of the chip. Then poll the MISO line. The MISO line will be held low during initialization, and will rise to high at the end of the initialization, when the chip becomes ready for further operation.

Address Space

The address space has been allocated as follows. Addresses from 0x000 to 0x06F are reserved for “dynamic registers”, i.e. registers that are expected to be frequently accessed during normal operation, as they can be efficiently accessed using single address byte SPI accesses. Addresses from 0x070 to 0x0FF have been left unused (they could only be accessed using the two address byte SPI format). Addresses from 0x100 to 0x1FF have been reserved for physical layer parameter registers, for example receiver, transmitter, PLL, crystal oscillator. Addresses from 0x200 to 0x2FF have been reserved for medium access parameters, such as framing, packet handling. Addresses from 0x300 to 0x3FF have been reserved for special functions, such as GPADC.

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AND9902/D

FIFO OPERATION

The AX5045 features a 256 Byte FIFO. The same FIFO is used for both reception and transmission. During transmit, only the write port is accessible by the microcontroller. During receive, only the read port is accessible by the microcontroller. Otherwise, both ports are accessible through the register file.

In order to prevent transmitting premature data, the FIFO contains three pointers. Data is read at the read pointer, up to the write pointer. Data is written to the write ahead pointer. The write pointer is not updated when data is written, therefore, new data is not immediately visible to the consumer. Writing the COMMIT command to the FIFOSTAT register copies the write ahead pointer to the write pointer, thus making the written data visible to the

receiver. Writing the ROLLBACK command to the FIFOSTAT register sets the write ahead pointer to the write pointer, thus discarding data written to the FIFO. During transmit, this means that the transmitter will only consider data written to the FIFO after the commit command. During receive, this feature is used by the receiver to store packet data before it is known whether the CRC check passes. FIFOCOUNT reports the number of bytes that can be read without causing an underflow. FIFOFREE reports the number of bytes that can be written without causing an overflow. FIFOCOUNT and FIFOFREE do not add up to 256 Bytes whenever there are uncommitted bytes in the FIFO. Figure 6 illustrates this.

Write ahead pointer

Write pointer

256−FIFOFREE

FIFOCOUNT

Read pointer

Figure 6. FIFO Pointer

FIFO Chunk Encoding

In order to distinguish meta-data (such as RSSI) from receive or transmit data, FIFO contents are organized as chunks. Chunks consist of a header that encodes the chunk length as well as the payload data format.

Each chunk starts with a single byte header. The header encodes the length of a chunk, and indicates the data it contains. The top 3 bits encode the length (or optionally refer to an additional length byte after the header byte), and the bottom 5 bits indicate what payload data the chunk contains. The following table lists the encoding of the length bits (top 3 bits of the first chunk header byte). Figure 7 shows the chunk header byte encoding.

Table 3. CHUNK PAYLOAD SIZE ENCODING

7 6 5 4 3 2 1 0

Chunk	Chunk
payload	payload
size	data format

Figure 7. FIFO Header byte Format

The following table lists the chunk payload size encoding:

Top Bits	Chunk Payload Size
000	No payload
001	Single byte payload
010	Two byte payload
011	Three byte payload

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	AND9902/D
Table 3. CHUNK PAYLOAD SIZE ENCODING (continued)
Top Bits	Chunk Payload Size
100	Invalid
101	Invalid
110	Invalid
111	Variable length payload; payload size is encoded in the following length byte the length byte is part of
	the header (and not included in length), everything after the length byte is included in the length

The following table lists the chunk types and their encodings. The Hdr Byte column lists the complete FIFO Chunk Header Byte, consisting of the length and data format encodings.

Table 4. CHUNK TYPES AND THEIR ENCODINGS

Name

Dir

Hdr. Byte

Description

7−0

No Payload Commands

NOP

T

00000000

No Operation

FIFOIRQ

T

00000011

Trigger a Radiocontrol

interrupt

One Byte Payload Commands

RSSI

R

00110001

RSSI

TXCTRL

T

00111100

Transmit Control

(Antenna, Power Amp)

Two Byte Payload Commands

FREQOFFS

R

01010010

Frequency Offset

ANTRSSI2

R

01010101

Background Noise

Calculation RSSI

Three Byte Payload Commands

REPEATDATA

T

01100010

Repeat Data

TIMER

TR

01110000

Timer

RFFREQOFFS

R

01110011

RF Frequency Offset

DATARATE

R

01110100

Datarate

ANTRSSI3

R

01110101

Antenna Selection RSSI

Variable Length Payload Commands

DATA

TR

11100001

Data

TXPWR

T

11111101

Transmit Power

Direction: T = Transmit, R = Receive

NOP Command

Table 5. NOP COMMAND

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

FIFOIRQ Command

Table 6. FIFOIRQ COMMAND

7	6	5	4	3	2	1	0
0	0	0	0	0	0	1	1

The FIFOIRQ command triggers an interrupt if bit IRQMRADIOCTRL is set in register IRQMASK0 and bit REVMFIFOIRQCMDDET is set in register RADIOEVENTMASK. This feature allows to track TX events as for example completion of preamble transmission.

To clear the interrupt, register RADIOEVENTREQ0 has to be read.

RSSI Command

Table 7. RSSI COMMAND

7	6	5	4		3	2	1	0
0	0	1	1		0	0	0	1
				RSSI

The RSSI command will only be generated by the receiver at the end of a packet if bit ST RSSI is set in register PKTSTOREFLAGS. The encoding is the same as that of the RSSI register.

TXCTRL Command

Table 8. TXCTRL COMMAND

7	6	5	4	3	2	1	0
0	0	1	1	1	1	0	0
0	SETTX	TXSE	TXDIFF	SETANT	ANTSTATE	SETPA	PASTATE

The TXCTRL command allows certain aspects of the transmitter to be changed on the fly. If SETTX is set, TXSE and TXDIFF are copied into the register MODCFGA. If SETANT is set, ANTSTATE is copied into register DIVERSITY. If SETPA is set, PASTATE is copied into register PWRAMP.

The NOP command will be discarded without effect by the transmitter. The receiver will not generate NOP commands.

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FREQOFFS Command

Table 9. FREQOFFS COMMAND

7	6	5	4	3	2	1	0
0	1	0	1	0	0	1	0
			FREQOFFS1
			FREQOFFS0

ANTRSSI2 Command

Table 10. ANTRSSI2 COMMAND

7	6	5	4		3	2	1	0
0	1	0	1		0	1	0	1
				RSSI
			BGNDNOISE

The FREQOFFS command will only be generated by the receiver at the end of a packet if bit ST FOFFS is set in register PKTSTOREFLAGS. The encoding is the same as that of the TRKFREQ register.

REPEATDATA Command

Table 11. REPEATDATA COMMAND

The ANTRSSI2 command will be generated by the receiver when it is idle if bit ST ANT RSSI is set in register PKTSTOREFLAGS. If DIVENA is set in register DIVERSITY, the ANTRSSI3 command is generated instead. The encoding of the RSSI field is the same as that of the RSSI register. The BGNDNOISE field contains an estimate of the background noise.

7	6	5	4	3	2	1	0
0	1	1	0	0	0	1	0
0	DIBITSYNC	UNENC	RAW	NOCRC	RESIDUE	PKTEND	PKTSTART

REPEATCNT

DATA

The REPEATDATA command allows the efficient transmission of repetitive data bytes. The DATA byte given in the payload is repeated REPEATCNT times. See DATA command for a description of the flag byte. This command is especially handy for constructing preambles.

TIMER Command

Table 12. TIMER COMMAND

7	6	5	4	3	2	1	0
0	1	1	1	0	0	0	0

TIMER2

TIMER1

TIMER0

This command enables exact packet timing, e.g. for frequency hopping systems.

In TX mode, upon detection of a TIMER command, the transmitter pauses until the internal timer (accessible via TIMER register) reaches the value given by the payload. A detailed documentation of this function can be found under the description of register RCTRLTIMESTAMP.

In RX mode, the TIMER command will be generated by the receiver at the start/end of a packet if bit ST TIMER and/or ST TIMER PKTEND is set in register PKTSTOREFLAGS. The payload is a copy of the internal timer (i.e. the current value of the TIMER register).

RFFREQOFFS Command

Table 13. RFFREQOFFS COMMAND

7	6	5	4	3	2	1	0
0	1	1	1	0	0	1	1

RFFREQOFFS2

RFFREQOFFS1

RFFREQOFFS0

The RFFREQOFFS command will only be generated by the receiver at the end of a packet if bit ST RFOFFS is set in register PKTSTOREFLAGS. The encoding is the same as that of the TRKRFFREQ register.

DATARATE Command

Table 14. DATARATE COMMAND

7	6	5	4	3	2	1	0
0	1	1	1	0	1	0	0

DATARATE2

DATARATE1

DATARATE0

The DATARATE command will only be generated by the receiver at the end of a packet if bit ST DR is set in register PKTSTOREFLAGS. The encoding is the same as that of the TRKDATARATE register.

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ANTRSSI3 Command

Table 15. ANTRSSI3 COMMAND

7	6	5	4	3	2	1	0
0	1	1	1	0	1	0	1

ANTORSSI2

ANTORSSI1

ANTORSSI0

The ANTRSSI3 command will be generated by the receiver when it is idle if bit ST ANT RSSI is set in register

Table 16. TRANSMIT DATA FORMAT

PKTSTOREFLAGS. If DIVENA is not set in register DIVERSITY, the ANTRSSI2 command is generated instead. The encoding of the ANT0RSSI and ANT1RSSI fields are the same as that of the RSSI register.

The BGNDNOISE field contains an estimate of the background noise.

DATA Command

The DATA command transports actual transmit and receive data. While the basic format is the same for transmit and receive, the semantics of the flag byte differs.

7	6	5	4		3	2	1	0
1	1	1	0		0	0	0	1
				LENGTH
0	DIBITSYNC	UNENC	RAW		NOCRC	RESIDUE	PKTEND	PKTSTART
				DATA

LENGTH includes the flags byte as well as all DATA bytes.

Setting RAW to one causes the DATA to bypass the framing mode, but still pass through the encoder.

Setting UNENC to one causes the DATA to bypass the framing mode, as well as the encoder, except for inversion. UNENC has priority over RAW.

Setting NOCRC suppresses the generation of the CRC bytes.

Setting RESIDUE allows the transmission of a number of data bits that is not a multiple of eight. All but the last data byte are transmitted as if RESIDUE was not set. The last byte however contains only 7 bits or less. The transmitter looks for the highest bit set. This is considered the stop bit. Only bits below the stop bit are transmitted. If the MSBFIRST in register PKTADDRCFG is set, the algorithm

is reversed, i.e. the lowest bit set is considered the stop bit and bits above the stop bit are transmitted.

PKTSTART and PKTEND bits enable the transmission of packets that are larger than the FIFO size. If PKTSTART is set, the radio packet starts at the beginning of the DATA command payload. If PKTEND is set, the radio packet ends at the end of the DATA command payload. If PKTSTART is not set, this command is the continuation of a previous DATA command. If PKTEND is not set, the packet is continued with the next DATA command.

Setting DIBITSYNC causes the DATA bytes to be aligned to DiBit boundaries in 4−FSK mode.

For example, to transmit 20 bits of an alternating 0−1 pattern as a preamble, the following bytes should be written to the FIFO (MSBFIRST = 0 in register PKTADDRCFG is assumed):

Table 17. FIFO COMMAND

0xE1	FIFO Command
0x04	Length Byte
0x24	Flag Byte: Unencoded, to ensure 0−1 remains 0−1, and Residue set, because the number of bits
	transmitted is not a multiple of 8
0xAA	Alternating 0−1 bits
0xAA	Alternating 0−1 bits
0x1A	Alternating 0−1 bits; Bit 4 is the “Stop” bit

Table 18. RECEIVE DATA FORMAT

7	6	5	4		3	2	1	0
1	1	1	0		0	0	0	1
			LENGTH
SYNCWD	ABORT	SIZEFAIL	ADDRFAIL		CRCFAIL	RESIDUE	PKTEND	PKTSTART
				DATA

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ABORT is set if the packet has been aborted. An ABORT sequence is a sequence of seven or more consecutive one bits when HDLC [1] framing is used. Note that if ACCPT ABRT is not set in register PKTACCEPTFLAGS, then aborted packets are silently dropped.

SIZEFAIL is set if the packet does not pass the size checks. Size checks are implemented using the PKTLENCFG, PKTLENOFFSET and PKTMAXLEN registers. Note that if ACCPT SZF is not set in register PKTACCEPTFLAGS, then packets with an invalid size are silently dropped.

ADDRFAIL is set if the packet does not pass the address checks. Address checks are implemented using the PKTADDRCFG, PKTADDRA, PKTADDRB, PKTADDRENA and PKTADDRMASK registers. Note that if ACCPTADDRF is not set in register PKTACCEPTFLAGS, then packets which do not match the programmed address are silently dropped.

CRCFAIL is set if the packet does not pass the CRC check. Note that if ACCPTCRCF is not set in register PKTACCEPTFLAGS, then packets which fail the CRC check are silently dropped.

RESIDUE, PKTEND and PKTSTART work identical as in transmit mode, see above.

The receiver generates chunks up to PKTCHUNKSIZE bytes. If PKTMAXLEN is larger than PKTCHUNKSIZE, multiple chunks may be generated for one packet. Since CRC and size checks may only be performed at the end of the packet, only the last chunk can be dropped at failure of one of those tests. It is therefore important that the microcontroller receiver routine clears its receive buffer at the beginning of DATA commands whose PKTSTART bit is set, as the buffer may still contain bytes from erroneous packets.

TXPWR Command

Table 19. TXPWR COMMAND

7	6	5	4	3	2	1	0
1	1	1	1	0	0	1	0

LENGTH = 10

TXPWRCOEFFA (7:0)

TXPWRCOEFFA (15:8)

TXPWRCOEFFB (7:0)

TXPWRCOEFFB (15:8)

TXPWRCOEFFC (7:0)

TXPWRCOEFFC (15:8)

TXPWRCOEFFD (7:0)

TXPWRCOEFFD (15:8)

TXPWRCOEFFE (7:0)

TXPWRCOEFFE (15:8)

The TXPWR command allows the transmit power to be changed on the fly. This command updates the TXPWRCOEFFA, TXPWRCOEFFB, TXPWRCOEFFC, TXPWRCOEFFD and TXPWRCOEFFE registers.

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PROGRAMMING THE CHIP

Power Modes

To enable the lowest possible application power consumption, the AX5045 allows to shut down its circuits

Table 20. PWRMODE REGISTER STATES

when not needed. This is controlled by the PWRMODE register. Idd values are typical; for exact values, please refer to the AX5045 datasheet [2].

PWRMODE register	Name	Description	Typical Idd
0000	POWERDOWN	Powerdown; all circuits powered down except for the register file	640 nA
0001	DEEPSLEEP	Deep Sleep Mode; Chip is fully powered down until SEL is lowered	121 nA
		again; looses all register contents
0101	STANDBY	Crystal Oscillator enabled	960 μA
0111	FIFOON	FIFO enabled (Crystal Oscillator enabled by setting bit XOEN in	1010 μA
		register PWRMODE)
1000	SYNTHRX	Synthesizer running, Receive Mode	7 mA
1001	FULLRX	Receiver Running	14-17 mA
1011	WORRX	Receiver Wake-on-Radio Mode	700 nA
1100	SYNTHTX	Synthesizer running, Transmit Mode	7 mA
1101	FULLTX	Transmitter Running at 23 dBm	255 mA

The following list explains the typical programming flow. Preparation:

1.Reset the Chip. Set SEL to high for at least 1μs, then low. Wait until MISO goes high. Set, and then clear, the RST bit of register PWRMODE.

2.Set the PWRMODE register to POWERDOWN.

3.Program parameters. It is recommended that suitable parameters are calculated using the AX−RadioLab tool available at onsemi.com.

4.Perform auto-ranging, to ensure the correct VCO

range setting.

The chip is now ready for transmit and receive operations.

FIFO Power Management

The FIFO is powered down during POWERDOWN and DEEPSLEEP modes (Register PWRMODE). Reads to register FIFOSTAT will provide bit FIFO EMPTY as one and bit FIFO FULL as zero. Registers FIFOCOUNT and FIFOFREE read zero as well. Reads from the FIFO will return undefined data, and writes to the FIFO will be lost.

In the receive case, the FIFO is automatically powered on when the chip PWRMODE is set to FULLRX. The FIFO should be emptied before the PWRMODE is set to POWERDOWN. In Wake-on-radio or POWERDOWN

mode, the FIFO is automatically kept powered on until it is emptied by the microprocessor.

In the transmit case, PWRMODE should first be set to FULLTX. Before writing to the FIFO, the microprocessor must ensure that the SVMODEM bit is high in Register POWSTAT, to ensure that the on-chip voltage regulator supplying the FIFO has finished starting up. The transmitter remains idle until the contents of the FIFO are committed (unless the FIFO AUTO COMMIT bit is set in Register FIFOSTAT).

Autoranging

Whenever the frequency changes, the synthesizer VCO should be set to the correct range using the built-in autoranging. A re-ranging of the VCO is required if the frequency change required is larger than 0.5 MHz divided by the RF Divider Ratio resulting from the RFDIV setting in register PLLVCODIV. Each individual chip must be auto-ranged. If both frequency register sets FREQA and FREQB are used, then both frequencies must be auto-ranged by first starting auto-ranging in PLLRANGINGA, waiting for its completion, followed by starting auto-ranging in PLLRANGINGB and waiting for its completion.

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Figure 8 shows the flow chart of the auto-ranging process.

Set PWRMODE to STANDBY

Enable TCXO if used

Wait until crystal oscillator is ready

Set RNGSTART of PLLRANGINGA/B

yes RNGSTART = 1?

no

yes

RNGERR = 1?

Error

no

Set PWRMODE to POWERDOWN

Disable TCXO if used

Figure 8. Autoranging Flow Chart

Before starting the auto-ranging, the appropriate frequency registers (FREQA or FREQB) need to be programmed. Auto-ranging starts at the VCOR (register PLLRANGINGA or PLLRANGINGB) setting;

if you already know the approximately correct synthesizer VCO range, you should set VCORA/VCORB to this value prior to starting auto-ranging; this can speed up the ranging process considerably. The autoranging feature will not increment/decrement the MSB so preset this to the appropriate range prior to setting the RNGSTART bit.

Hardware clears the RNG START bit automatically as soon as the ranging is finished; the device may be programmed to deliver an interrupt on resetting of the RNG START bit.

Waiting until auto-ranging terminates can be performed by either polling the register PLLRANGINGA1 or PLLRANGINGB1 for RNG START to go low, or by enabling the IRQMPLLRNGDONE interrupt in register IRQMASK1.

Choosing the Fundamental Communication Characteristics

The following table lists the fundamental communication characteristics that need to be chosen before the device can be programmed.

Table 21. FUNDAMENTAL COMMUNICATION CHARACTERISTIC

Parameter	Description
fXTAL	Frequency of the connected crystal/TCXO in Hz
modulation	PSK, ASK, FSK, MSK, OQPSK, 4−FSK or AFSK (for recommendations see below)
fCARRIER	Carrier frequency (i.e. center frequency of the signal) in Hz
BITRATE	Desired bit rate in bit/s
h	Modulation index, determines the frequency deviation for FSK
	32 > h ≥ 0.5 for FSK, 4−FSK or AFSK, fdeviation = 0.5 * h * BITRATE
	h = 0.5 for MSK and OQPSK
	(For AFSK, fdeviation is usually set according to the FM channel specification. For 25 kHz channels, it is
	often approximately 3 kHz)
encoding	Inversion, differential, Manchester, scrambled, for recommendations see the description of the register
	ENCODING.

The following table gives an overview of the trade-offs between the different modulations that AX5045 offers, they should be considered when making a choice.

Table 22. TRADE-OFFS BETWEEN THE DIFFERENT MODULATION

Modulation	Trade-offs
FSK	For bit rates up to 125 kbit/s; 200 kbit/s possible with some limitations*
	Frequency deviation is a free parameter
ASK	For bit rates up to 50 kbit/s;
	ASK is spectrally more efficient than FSK, but also more susceptible to noise and can only be
	demodulated with lower sensitivity.

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Table 22. TRADE-OFFS BETWEEN THE DIFFERENT MODULATION (continued)
Modulation	Trade-offs
MSK	For bit rates up to 125 kbit/s; 200 kbit/s possible with some limitations*
	Robust and spectrally efficient form of FSK (Modulation is the same as FSK with h = 0.5)
	Frequency deviation given by bit rate
	The advantage of MSK over FSK is that it can be demodulated with higher sensitivity.
	Slightly longer preambles required than for FSK
OQPSK	For bit rates up to 125 kbit/s; 200 kbit/s possible with some limitations*
	Very similar to MSK, with added precoding / postdecoding
	For new designs, use MSK instead
PSK	For bit rates up to 10 kbit/s;
	Spectrally efficient and high sensitivity
	Very accurate frequency reference (maximum carrier frequency deviation ±1/4 BITRATE) and long
	preambles required
4−FSK	For bit rates up to 100 kSymbols/s, or 200 kbit/s possible with some limitations*
	Similar to FSK, but four frequencies are used to transmit 2 bits simultaneously
	Very slightly more spectrally efficient compared to FSK
	((1 + 3 h/2) BITRATE versus (1 + h) BITRATE) for small h.
	Longer preambles required as frequency offset estimation needs to be more precise to successfully
	demodulate
	For new designs, use FSK instead
AFSK	For bit rates up to 25 kbit/s
	Bits are FSK modulated in the audio band, then frequency modulated on the carrier frequency.
	For legacy compatibility applications only.

*To receive at a data rate of 200 kbit/s, a reference clock between 32 and 50 MHz is required. The ADC clock needs to be configured to by 1/2 the reference clock. This causes the ADC to sample at 2 MSPS instead of 1 MSPS and is required for receiving at the higher data rates. The

ADC sample rate should still be configured as 2 MSPS in all setup configurations. Also, when receiving with higher datarates, care must be taken to increase the RX bandwidth accordingly (see BBTUNE Register). Also note that the higher sample rate will result in increased current consumption of 1−1.5 mA, due to increased clocking. In order to transmit at the higher data rates, care must be taken to ensure the PLL loop bandwidth is wide enough to handle the modulation properly.

Given these fundamental physical layer parameters, AX_RadioLab should be used to compute the register settings of the AX5045.

Framing

Figure 1 shows the block diagram of the AX5045. After the user writes a transmit packet into the FIFO, the Radio Controller sequences the transmitter start-up, and signals the Packet Controller to read the packet from the FIFO and add framing bits, allowing the receiver to lock to the transmit waveform, and to detect packet and byte boundaries. If MSB first is selected (register PKTADDRCFG), then the bits within each byte are swapped when the data is read out from the FIFO.

The Packet Controller also (optionally) adds cyclic redundancy check (CRC) bits at the end of the packet, to enable the receiver to detect transmission errors. Both 16 and 32 Bit CRC can be selected, as well as different generator polynomials. The CRC polynomial can be selected in register CRCCFG. The following polynomials are supported:

•CRC-CCITT (16bit):

x16+x12+x5 +1 (hexadecimal: 0x1021)

•CRC-16 (16bit):

x16+ x 15+ x2 + 1 (hexadecimal: 0x8005)

• CRC-DNP (16bit):

x 16+ x 13+ x12 + x 11+ x 10+ x 8 + x 6 + x 5+ x2 + 1

(hexadecimal: 0x3D65)

This polynomial is used for Wireless M-Bus.

• CRC-32 (32bit):

x 32+ x 26+ x 23 + x 22+ x 16+ x12 + x 11+ x 10+ x8 + x 7+ 5

x 5 + x 4 + x 2 + x + 1 (hexadecimal: 0x04C11DB7)

The CRC is always transmitted MSB first regardless of the MSB first setting of register PKTADDRCFG, to enable the receiver to process CRC bits as they arrive (otherwise, they would have to be stored and reordered). For an in-depth guide on how CRC’s are computed, see [3].

By default, the CRC bits are inverted so that erroneously appended zero−bits can be detected. Skipping this inversion is not recommended, but it can be achieved by setting bit CRCNOINV in register CRCCFG.

Finally, the encoder is able to perform certain bit-wise operations on the bit-stream:

•Manchester:

Manchester transmits a one bit as 10 and a zero bit as 01, i.e. it doubles the data rate on the radio channel. Its advantage is that the resulting bit-stream has many transitions and thus simplifies synchronizing to the

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transmission on the receiver side. The downside is that it now requires twice the amount of energy for the transmission. Manchester is not recommended, except for compatibility with legacy systems.

•Scrambler:

The scrambler ensures that even highly regular transmit data results in a seemingly random transmitted bit-stream. This avoids discrete tones in the spectrum. Three different scrambling polynomials can be selected (PN9, PN15, PN17) and it is possible to choose between additive or multiplicative (self−synchronizing) scrambling. Do not confuse the scrambler with encryption – it does not provide any secrecy, its actions are easily reversed. Its use is recommended, particularly multiplicative scrambling.

•Differential:

Differential transmits zero bits as constant level, and one bits as level change. This allows to accommodate modulations that can invert the bit-stream, such as PSK.

•Inversion:

If on, the bit-stream is inverted. Useful for example for compatibility with legacy systems, such as POCSAG, which differ from the usual convention that the higher FSK frequency signifies a one.

The encoder is controlled using the register ENCODING. It may be temporarily bypassed except for the inversion by setting the UNENC bit of the FIFO chunks DATA or REPEATDATA. This is useful for synthesizing preambles.

The receiver performs these tasks in reverse order.

Transmitter

Figure 9 shows the transmitter flow chart. The microprocessor first places the chip into FULLTX mode. This prepares the chip for a future transmission, enables the FIFO in transmit direction, but does not yet power-up the synthesizer or any other transmit circuitry.

The microprocessor can now write the preamble and the actual packet to the FIFO. The preamble is programmable to allow standards to be implemented that specify a specific preamble to be used. Otherwise, the recommendations for preambles can be found below.

Waiting for the crystal oscillator to start up may be performed by polling the register XTALSTATUS, or by enabling the IRQMXTALREADY interrupt in register IRQMASK1.

After the FIFO contents are committed (writing the Commit command to the FIFOSTAT register), the transmitter notices that the FIFO is no longer empty. It then

powers up the synthesizer and settles it (registers TMGTXBOOST and TMGTXSETTLE determine the timing). The Preamble and the Packet(s) are then transmitted, followed by the transmitter and synthesizer shut-down.

The transmitter is automatically ramped up and down smoothly, to prevent unwanted spurious emissions. The ramp time is normally one bit time, but may be longer by changing the SLOWRAMP field of register MODCFGA.

The PWRMODE register should stay at FULLTX until the transmission is fully completed. The end of the transmission may be determined by polling the register RADIOSTATE until it indicates idle, or by enabling the radio controller interrupt (bit IRQMRADIOCTRL) in register IRQMASK0 and setting the radio controller to signal an interrupt at the end of transmission (bit REVMDONE of register RADIOEVENTMASK0).

Set PWRMODE to FULLTX

Enable TCXO if used

Write Preamble to FIFO

Write Packet to FIFO

Wait until crystal oscillator is running

Commit FIFO

Wait until transmission is done

Set PWRMODE to POWERDOWN

Disable TCXO if used

Figure 9. Transmitter Flow Chart

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Recommended Preamble

The main purpose of the preamble is to allow for the receiver to acquire vital transmission parameters before the actual packet data starts. The minimum duration of the preamble is dependent on how much time the receiver needs to acquire these parameters to sufficient precision. More specifically, it depends on:

•The time needed for the receiver adaptive gain control (AGC) to acquire the signal strength.

•The time needed for the receiver to acquire the maximum possible frequency offset

(register MAXRFOFFSET).

•The time needed for the receiver to acquire the maximum possible data rate offset

(register MAXDROFFSET).

•The time needed for the receiver to acquire the exact bit sampling time (register TIMEGAIN).

•The time needed to acquire the actual frequency deviation in 4−FSK mode (register FSKDMAX).

On the AX5045, these loops run in parallel. An AGC that is significantly off however causes the received signal to fall outside the IF strip dynamic range, and thus prevents the other loops from working. And a frequency offset that is compensated insufficiently causes the received signal to fall (partially) outside the IF filter, thus also preventing the timing and 4−FSK loops from working.

The minimum possible preamble duration can be achieved under the following conditions:

•Use a transmitter with a sufficiently precise bit timing. If the maximum deviation of the transmitter data rate from the receiver data rate is less than approximately 0.1%, then the data rate acquisition loop should be switched off completely (setting register MAXDROFFSET to zero). The AX5045 is able to track the remaining small offset without the data rate offset loop. All ON Semiconductor transmitters of the

AX504x family derive the bit rate timing from the crystal reference and can therefore easily meet this requirement.

•Use an FSK frequency deviation that is larger than the maximum frequency offset between transmitter and receiver. In this case, receiver frequency offset acquisition is not needed. Do not use 4−FSK.

•Use the AX5045 receiver parameter set feature, below.

Finally, the frame synchronization word achieves byte synchronization.

The recommended preamble bit pattern is now discussed. If the standard to be implemented requires a specific

preamble, use it.

In FEC mode, HDLC [1] flags (pattern 01111110) must be transmitted. The convolutional encoder ensures enough bit transitions, and the AX5045 receiver needs flags to synchronize its interleaver.

If multiplicative scrambling or Manchester is enabled, send RAW bytes 00010001. The scrambler or Manchester encoder ensure enough transitions to acquire the bit timing.

In 4−FSK mode, send UNENCODED bytes 00010001. This ensures that the preamble toggles between the highest and the lowest frequency. The frequent transitions ensure the bit timing is acquired as quickly as possible, and the maximum and minimum frequencies allow the deviation to be acquired. If inversion is enabled, make sure to set a preamble that still results in toggling between DiBit symbols of 10 and 00.

Otherwise, use UNENCODED 01010101. This preamble ensures the maximum number of transitions for bit timing synchronization. This preamble could also be used with the multiplicative scrambler enabled; the main purpose of the scrambler is however to ensure no spectral lines (tones), this would be defeated by this preamble.

If MSBFIRST in register PKTADDRCFG is set, then the preamble sequences should be reversed.

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Receiver

Figure 10 shows the receiver flow chart. When the microprocessor places the chip into FULLRX mode, the AX5045 immediately powers up the synthesizer, settles it

(registers TMGRXBOOST and TMGRXSETTLE determine the timing) and starts receiving. The reception continues until the microprocessor changes the PWRMODE register.

Set PWRMODE to FULLRX

Enable TCXO if used

yes

Timeout?

no

no

Packet Received?

(FIFO not empty)

yes

Read Packet from FIFO

yes

Continue

Reception?

no

Set PWRMODE to POWERDOWN

Disable TCXO if used

Set PWRMODE to WORRX

TCXO controlled by PWRAMP or

ANTSEL if used

no

Packet Received?

(FIFO not empty)

yes

Read Packet from FIFO

yes

Continue

Reception?

no

Set PWRMODE to POWERDOWN Disable TCXO if used

Figure 10. Receiver Flow Chart

Figure 11. Wake-on-Radio Receiver Flow Chart

If antenna diversity is enabled, the AX5045 continuously switches between the antennas (controlled by the ANTSEL pin) to find the antenna with the better signal strength, until a valid preamble is detected. Antenna scanning is resumed after a packet is completed.

Actual packet data in the FIFO may be preceded and followed by meta-data. Meta-data may be a time stamp at the beginning and/or the end of the packet, and signal strength, frequency offset and data rate offset at the end of the packet. Which meta-data is written to the FIFO is controlled by the register PKTSTOREFLAGS.

Wake-on-Radio mode allows the AX5045 to periodically poll the radio channel for a transmission while using only very little power. Figure 11 shows the wake-on-radio flow

chart. The AX5045 periodically wakes up. The wake-up is controlled by the on-chip low-power 640 Hz/10 kHz RC oscillator and the period is programmed using the WAKEUPFREQ register.

After waking up, the AX5045 quickly settles the AGC and computes the channel RSSI. If it is below an absolute threshold (register RSSIABSTHR) and a dynamic threshold (register BGNDRSSITHR), it is switched off immediately. Otherwise, it looks for a valid preamble. If none is found within a preprogrammed time (registers TMGRXPREAMBLE1 and TMGRXPREAMBLE2), the receiver is powered down. Otherwise, it continues to receive the packet.

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If a packet is successfully received, the receiver may either be shut down again, or continue to run if WORMULTIPKT is set in register PKTMISCFLAGS.

In Wake-on-Radio mode, the AX5045 is completely autonomous until a packet is received. The microprocessor may be shut down and only wake up once the FIFO is no longer empty (IRQMFIFONOTEMPTY interrupt in register IRQMASK0).

Receiver State Machine

Figure 12 shows the receiver timing diagram. The actions in the first two lines are time controlled. The arrows below indicate which register controls the timing. The actions colored in a darker shade of blue are only performed when diversity mode is enabled (DIVENA is set in register DIVERSITY). The actions in the last line are detailed in the state diagram Figure 13.

SYNTHBOOST and SYNTHSETTLE form the two stage procedure to settle the synthesizer on the first LO frequency. During SYNTHBOOST, the synthesizer is operated at a higher loop bandwidth (register PLLLOOPBOOST), while during SYNTHSETTLE, the final settling is done at the nominal, lower noise, loop bandwidth (register PLLLOOP).

IFINIT settles the IF strip. COARSEAGC uses a fast AGC time constant to quickly settle the AGC to a value close to the correct one. This is especially important during wake-on-radio, as it is desirable to keep the receiver powered the shortest possible time to save power. AGC settles the AGC using a slower time constant. RSSI measures the received signal strength. This value is then used to determine whether the receiver should be kept running in wake-on-radio, or to select the antenna with the stronger signal in diversity mode.

Antenna #0

SYNTHBOOST	SYNTHSETTLE			IFINIT		COARSEAGC		AGC	RSSI
TMGRXBOOST	TMGRXSETTLE		TMGRXOFFSACQ		TMGRXCOARSEAGC			TMGRXAGC	TMGRXRSSI
		Antenna #1					Selected Antenna
IFINIT		COARSEAGC		AGC		RSSI		IFINIT
TMGRXOFFSACQ		TMGRXCOARSEAGC		TMGRXAGC		TMGRXRSSI	TMGRXOFFSACQ
PREAMBLE1		PREAMBLE2		PREAMBLE3		PACKET			Antenna
									Diversity only

MATCH1	MATCH0	SFD detected

Figure 12. Receiver Flow Chart

Once the receiver is initialized, PREAMBLE1, PREAMBLE2, PREAMBLE3, and PACKET coordinate the reception of packets. The receiver contains several loops that acquire and track transmission parameters the receiver needs to know in order to correctly receive a packet.

•The AGC acquires and tracks the signal strength

•The frequency tracking loop acquires and tracks the frequency offset

•The timing and data rate tracking loop acquires and tracks the sampling time and the data rate offset

The bandwidth of these loops is programmable. The bandwidth controls the acquisition time as well as the

noisiness of the parameter estimates. In order to allow both fast acquisition to enable short preambles and low steady state noise performance to enable high receiver sensitivity, the receiver supports multiple acquisition and tracking loop parameter sets. When the receiver searches for a transmission signal, it uses wide loop bandwidths. Once it detects a preamble with sufficient probability, it switches to a lower loop bandwidth. Once a frame start is detected, it switches to an even lower loop bandwidth. Figure 13 shows the state diagram that controls which receiver parameter set is used.

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Figure 13. Receiver State Diagram

Conditions are evaluated in priority order. The priority number is given in parentheses at the beginning of arrow labels.

In order to reduce the number of registers that need to be programmed if not all parameter sets are different, the parameter set number of Figure 13 is not directly used to address the parameter set. Instead, it indexes into register RXPARAMSETS, where the actual parameter set number is read out.

Low Power Oscillator Calibration

The low power oscillator is used to control the wake-up frequency, or polling period, during wake-on-radio mode. In

Crystal
or TCXO	LPOSCREF

order to increase the precision of the wake-up frequency, calibration logic allows the low power oscillator to be calibrated against the crystal oscillator or TCXO.

Figure 14 shows a block diagram of the calibration logic. It works similarly to a PLL. The reference frequency from the crystal or TCXO is divided by the value of the LPOSCREF register. This signal is then compared to the actual frequency of the Low Power Oscillator. The frequency difference is then low pass filtered (LPOSCKFILT register) and used to adjust the Low Power Oscillator frequency (LPOSCFREQ register).

LPOSCKFILT LPOSCFREQ

FD

Figure 14. Low Power Oscillator Calibration Logic

When enabled (LPOSCCALIBR or LPOSCCALIBF enabled in register LPOSCCONFIG), the calibration logic is only activated when the crystal oscillator or TCXO is

enabled as well. This allows “opportunistic” calibration – the Low Power Oscillator is calibrated whenever the reference frequency is enabled.

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Auxiliary DAC

The AX5045 contains an auxiliary DAC. It can be used to output various receiver signals, such as RSSI or Frequency Offset, or just a value under program control. The DAC signal can be output either on the PWRAMP or ANTSEL pad.

The DAC may be operated in two modes. ΣΔ mode employs a digital modulator to output a high resolution signal. Its output voltage range is ¼ VDDIO to ¾ VDDIO for a DACVALUE range from *2048 to 2047.

PWM mode outputs a pulse width modulated signal. It is only suitable for low frequency signals. Its output voltage range is 0 to VDDIO for a DACVALUE range from *2048 to 2047.

			R
PWRAMP						<![if ! IE]> <![endif]>e
						<![if ! IE]> <![endif]>g
or ANTSEL						<![if ! IE]> <![endif]>l t a
					C	<![if ! IE]> <![endif]>o
						<![if ! IE]> <![endif]>V
GND						<![if ! IE]> <![endif]>A C
						<![if ! IE]> <![endif]>D

Figure 15. DAC RC Filter

A low pass filter, such as a simple R-C filter as shown in Figure 15, must be used to obtain the analog voltage.

DACINPUT	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0001	15			TRK_AMPLITUDE + 0x8000												0	0	0	0	0	0	0	0	0
0010	19						TRK_RFFREQUENCY													0	0	0	0	0
0011	15					TRK_FREQUENCY										0	0	0	0	0	0	0	0	0
0100	13				TRK_FSKDEMOD									0	0 0 0 0 0 0 0 0 0 0
0110	7			RSSI		0			0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0111
	13					SOFTDATA								0	0	0	0	0	0	0	0	0	0	0
1000
	13						I							0	0	0	0	0	0	0	0	0	0	0
1001
	13						Q							0	0	0	0	0	0	0	0	0	0	0
1100
	13				GPADC + 0x2000									0	0	0	0	0	0	0	0	0	0	0

Shifter

		11	Limiter		0
0000
		11	DACVALUE		0
			to DAC
	Figure 16. DAC Signal Scaling

Figure 16 shows the DAC Signal scaling. DACINPUT in register DACCONFIG selects the source signal. The input signals are left aligned to 24 bits and padded with zeros. A signed shifter then shifts the selected value to the right by 0 to 15 digits as selected by the lower four bits of the DACVALUE register. The signal is then limited to the DAC

value range of *211 to 211*1. This signal is then sent to the DAC core. Note that if DACVALUE is selected as input, the register value is directly sent to the DAC, the shifter is not used. In fact, DACVALUE and DACSHIFT share the same register bits.

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REGISTER OVERVIEW

Table 23. CONTROL REGISTER MAP

Bit

Addr

Name

Dir

Ret

Reset

7

6

5

4

3

2

1

0

Description

Revision & Interface Probing

000

REVISION

R

R

01000110

SILICONREV(7:0)

Silicon Revision

001

SCRATCH

RW

R

11000101

SCRATCH(7:0)

Scratch Register

Operating Mode

002

PWRMODE

RW

R

000–0000

RST

XOEN

REFEN

WDS

PWRMODE(3:0)

Power Mode

Voltage Regulator

003

POWSTAT

R

R

––––––––

SSUM

SREF

SVREF

SVANA

SVMO

SBEVA

SBEVM

SVIO

Power

DEM

NA

ODEM

Management

Status

004

POWSTICKYSTAT

R

R

––––––––

SSSUM

SSREF

SSVRE

SSVAN

SSVM

SSBEV

SSBEV

SSVIO

Power

F

A

ODEM

ANA

MODEM

Management

Sticky Status

005

POWIRQMASK

RW

R

00000000

MPWR

MSREF

MSVR

MS

MS

MSBE

MSBE

MSVIO

Power

GOOD

EF

VANA

VMOD

VANA

VMOD

Management

EM

EM

Interrupt Mask

Interrupt Control

006

IRQMASK1

RW

R

00000000

IRQMASK(15:8)

IRQ Mask

007

IRQMASK0

RW

R

00000000

IRQMASK(7:0)

IRQ Mask

009

RADIOEVENTMASK

RW

R

––000000

–

–

RADIO EVENT MASK(5:0)

Radio Event

Mask

00A

IRQINVERSION1

RW

R

00000000

IRQINVERSION(15:8)

IRQ Inversion

00B

IRQINVERSION0

RW

R

00000000

IRQINVERSION(7:0)

IRQ Inversion

00C

IRQREQUEST1

R

R

––––––––

IRQREQUEST(15:8)

IRQ Request

00D

IRQREQUEST0

R

R

––––––––

IRQREQUEST(7:0)

IRQ Request

00F

RADIOEVENTREQ

R

––––––––

–

–

RADIO EVENT REQ(5:0)

Radio Event

Request

Modulation & Framing

010

MODULATION

RW

R

–––01000

–

–

–

RX

MODULATION(3:0)

Modulation

HALF

SPEED

011

ENCODING1

RW

R

–––––––0

–

–

–

–

–

–

–

ENC

Encoder/Decod

NOSY

er Settings

NC

012

ENCODING0

RW

R

00000100

ENC

ENC

ENC SCRPOLY(1:0)

ENC

ENC

ENC INV(1:0)

Encoder/Decod

ALTPN

SCRM

MANC

DIFF

er Settings

9

ODE

H

013

FRAMING

RW

R

––––0000

FRMR

–

–

–

FRMMODE(2:0)

FABOR

Framing settings

X

T

014

CRCCFG

RW

R

––––0000

–

–

–

–

CRCMODE(2:0)

CRCN

CRC settings

OINV

015

CRCINIT3

RW

R

11111111

CRCINIT(31:24)

CRC

Initialization

Data

016

CRCINIT2

RW

R

11111111

CRCINIT(23:16)

CRC

Initialization

Data

017

CRCINIT1

RW

R

11111111

CRCINIT(15:8)

CRC

Initialization

Data

018

CRCINIT0

RW

R

11111111

CRCINIT(7:0)

CRC

Initialization

Data

Forward Error Correction

019

FEC

RW

R

00000000

SHOR

RSTVI

FEC

FEC

FECINPSHIFT(2:0)

FEC

FEC (Viterbi)

T MEM

TERBI

NEG

POS

ENA

Configuration

01A

FECSYNC

RW

R

01100010

FECSYNC(7:0)

Interleaver

Synchronization

Threshold

01B

FECSTATUS

R

R

––––––––

FEC

MAXMETRIC(6:0)

FEC Status

INV

www.onsemi.com

21

AND9902/D

Table 23. CONTROL REGISTER MAP (continued)

Bit

Addr

Name

Dir

Ret

Reset

7

6

5

4

3

2

1

0

Description

Status

01C

RADIOSTATE

R

–

––––0000

–

–

–

–

RADIOSTATE(3:0)

Radio Controller

State

01D

XTALSTATUS

R

R

––––––––

–

–

–

–

–

–

–

XTAL

Crystal

RUN

Oscillator Status

Pin Configuration

020

PINSTATE

R

R

––––––––

–

–

PS

PS

PS IRQ

PS

PS

PS

Pinstate

PWR

ANT

DATA

DCLK

SYS

AMP

SEL

CLK

021

PINFUNCSYSCLK

RW

R

1––00010

PU

–

–

PFSYSCLK(4:0)

SYSCLK Pin

SYSCL

Function

K

022

PINFUNCDCLK

RW

R

00–––100

PU

PI

–

–

–

PFDCLK(2:0)

DCLK Pin

DCLK

DCLK

Function

023

PINFUNCDATA

RW

R

10–––111

PU

PI

–

–

–

PFDATA(2:0)

DATA Pin

DATA

DATA

Function

024

PINFUNCIRQ

RW

R

00–––011

PU

PI IRQ

–

–

–

PFIRQ(2:0)

IRQ Pin

IRQ

Function

025

PINFUNCANTSEL

RW

R

00–––110

PU

PI

–

–

–

PFANTSEL(2:0)

ANTSEL Pin

ANTSE

ANTSE

Function

L

L

026

PINFUNCPWRAMP

RW

R

00––0110

PU

PI

–

–

PFPWRAMP(3:0)

PWRAMP Pin

PWRA

PWRA

Function

MP

MP

027

PWRAMP

RW

R

–––––––0

–

–

–

–

–

–

–

PWRA

PWRAMP

MP

Control

FIFO

028

FIFOSTAT

R

R

0–––––––

FIFO

–

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO Control

AUTO

FREE

CNT

OVER

UNDE

FULL

EMPT

COMMI

THR

THR

R

Y

T

W

R

FIFOCMD(5:0)

029

FIFODATA

RW

––––––––

FIFODATA(7:0)

FIFO Data

02A

FIFOCOUNT1

R

R

–––––––0

–

–

–

–

–

–

–

FIFO

Number of

COUN

Words currently

T(8)

in FIFO

02B

FIFOCOUNT0

R

R

00000000

FIFOCOUNT(7:0)

Number of

Words currently

in FIFO

02C

FIFOFREE1

R

R

–––––––1

–

–

–

–

–

–

–

FIFO

Number of

FREE(

Words that can

8)

be written to

FIFO

02D

FIFOFREE0

R

R

00000000

FIFOFREE(7:0)

Number of

Words that can

be written to

FIFO

02F

FIFOTHRESH

RW

R

00000000

FIFOTHRESH(7:0)

FIFO Threshold

Synthesizer

030

PLLLOOP

RW

R

0–––1001

FREQ

–

–

–

DIREC

FILT

FLT(1:0)

PLL Loop Filter

B

T

EN

Settings

031

PLLCPI

RW

R

00001000

PLLCPI

PLL Charge

Pump Current

032

PLLRANGINGA1

RW

R

00000001

STICK

PLL

RNGE

RNG

STICK

VTUNE

–

VCOR

PLL

Y

LOCK

RR

START

Y

OFFR

A(8)

Autoranging

LOCK

OFFR

NG

NG

033

PLLRANGINGA0

RW

R

00000000

VCORA(7:0)

PLL

Autoranging

034

FREQA3

RW

R

00111001

FREQA(31:24)

Synthesizer

Frequency

035

FREQA2

RW

R

00110100

FREQA(23:16)

Synthesizer

Frequency

036

FREQA1

RW

R

11001100

FREQA(15:8)

Synthesizer

Frequency

037

FREQA0

RW

R

11001101

FREQA(7:0)

Synthesizer

Frequency

038

PLLLOOPBOOST

RW

R

0–––1011

FREQ

–

–

–

DIREC

FILT

FLT(1:0)

PLL Loop Filter

B

T

EN

Settings

(Boosted)

www.onsemi.com

22

AND9902/D

Table 23. CONTROL REGISTER MAP (continued)

Bit

Addr

Name

Dir

Ret

Reset

7

6

5

4

3

2

1

0

Description

039

PLLCPIBOOST

RW

R

11001000

PLLCPI

PLL Charge

Pump Current

(Boosted)

03A

PLLRANGINGB1

RW

R

00000001

STICK

PLL

RNGE

RNG

STICK

VTUNE

–

VCOR

PLL

Y

LOCK

RR

START

Y

OFFR

B(8)

Autoranging

LOCK

OFFR

NG

NG

03B

PLLRANGINGB0

RW

R

00000000

VCORB(7:0)

PLL

Autoranging

03C

FREQB3

RW

R

00111001

FREQB(31:24)

Synthesizer

Frequency

03D

FREQB2

RW

R

00110100

FREQB(23:16)

Synthesizer

Frequency

03E

FREQB1

RW

R

11001100

FREQB(15:8)

Synthesizer

Frequency

03F

FREQB0

RW

R

11001101

FREQB(7:0)

Synthesizer

Frequency

040

PLLVCODIV

RW

R

–––00000

–

–

–

RFDIV

REFDIV(1:0)

PLL Divider

Settings

Signal Strength

041

RSSI

R

R

––––––––

RSSI(7:0)

Received Signal

Strength

Indicator

042

BGNDRSSI

RW

R

00000000

BGNDRSSI(7:0)

Background

RSSI

043

DIVERSITY

RW

R

––––––00

–

–

–

–

–

–

ANT

DIV

Antenna

SEL

ENA

Diversity

Configuration

044

AGCCOUNTER

RW

R

––––––––

AGCCOUNTER(7:0)

AGC Current

Value

Receiver Tracking

045

TRKDATARATE2

R

R

––––––––

TRKDATARATE(23:16)

Datarate

Tracking

046

TRKDATARATE1

R

R

––––––––

TRKDATARATE(15:8)

Datarate

Tracking

047

TRKDATARATE0

R

R

––––––––

TRKDATARATE(7:0)

Datarate

Tracking

048

TRKAMPL1

R

R

––––––––

TRKAMPL(15:8)

Amplitude

Tracking

049

TRKAMPL0

R

R

––––––––

TRKAMPL(7:0)

Amplitude

Tracking

04A

TRKPHASE1

R

R

––––––––

–

–

–

–

TRKPHASE(11:8)

Phase Tracking

04B

TRKPHASE0

R

R

––––––––

TRKPHASE(7:0)

Phase Tracking

04D

TRKRFFREQ2

RW

R

––––––––

–

–

–

–

TRKRFFREQ(19:16)

RF Frequency

Tracking

04E

TRKRFFREQ1

RW

R

––––––––

TRKRFFREQ(15:8)

RF Frequency

Tracking

04F

TRKRFFREQ0

RW

R

––––––––

TRKRFFREQ(7:0)

RF Frequency

Tracking

050

TRKFREQ1

RW

R

––––––––

TRKFREQ(15:8)

Frequency

Tracking

051

TRKFREQ0

RW

R

––––––––

TRKFREQ(7:0)

Frequency

Tracking

052

TRKFSKDEMOD1

R

R

––––––––

–

–

TRKFSKDEMOD(13:8)

FSK

Demodulator

Tracking

053

TRKFSKDEMOD0

R

R

––––––––

TRKFSKDEMOD(7:0)

FSK

Demodulator

Tracking

054

TRKAFSKDEMOD1

R

R

––––––––

TRKAFSKDEMOD(15:8)

AFSK

Demodulator

Tracking

055

TRKAFSKDEMOD0

R

R

––––––––

TRKAFSKDEMOD(7:0)

AFSK

Demodulator

Tracking

Timer

059

TIMER2

R

–

––––––––

TIMER(23:16)

1MHz Timer

05A

TIMER1

R

–

––––––––

TIMER(15:8)

1MHz Timer

05B

TIMER0

R

–

––––––––

TIMER(7:0)

1MHz Timer

www.onsemi.com

23

AND9902/D

Table 23. CONTROL REGISTER MAP (continued)

Bit

Addr

Name

Dir

Ret

Reset

7

6

5

4

3

2

1

0

Description

05C

TIMERCLK

RW

R

––––––10

–

–

–

–

–

–

CLKMUX(1:0)

Internal Timer

Clock Setting

Time Stamp

060

RCTRLTIMESTAMP2

RW

R

00000000

RCTRLTIMESTAMP(23:16)

Radio Controller

Timestamp

Count

061

RCTRLTIMESTAMP1

RW

R

00000000

RCTRLTIMESTAMP(15:8)

Radio Controller

Timestamp

Count

062

RCTRLTIMESTAMP0

RW

R

00000000

RCTRLTIMESTAMP(7:0)

Radio Controller

Timestamp

Count

064

RCTRLTIMETXENA

RW

R

–––––––0

–

–

–

–

–

–

–

TIMET

Radio Controller

X ENA

Timestamp

Enable

Wakeup Timer

068

WAKEUPTIMER1

R

R

––––––––

WAKEUPTIMER(15:8)

Wakeup Timer

069

WAKEUPTIMER0

R

R

––––––––

WAKEUPTIMER(7:0)

Wakeup Timer

06A

WAKEUP1

RW

R

00000000

WAKEUP(15:8)

Wakeup Time

06B

WAKEUP0

RW

R

00000000

WAKEUP(7:0)

Wakeup Time

06C

WAKEUPFREQ1

RW

R

00000000

WAKEUPFREQ(15:8)

Wakeup

Frequency

06D

WAKEUPFREQ0

RW

R

00000000

WAKEUPFREQ(7:0)

Wakeup

Frequency

06E

WAKEUPXOEARLY

RW

R

00000000

WAKEUPXOEARLY(7:0)

Wakeup Crystal

Oscillator Early

Physical Layer Parameters

Receiver Parameters

100

IFFREQ1

RW

R

00010011

IFFREQ(15:8)

2nd LO / IF

Frequency

101

IFFREQ0

RW

R

00100111

IFFREQ(7:0)

2nd LO / IF

Frequency

102

DECIMATION1

RW

R

––––––00

–

–

–

–

–

–

DECIMATION(9:8)

Decimation

Factor

103

DECIMATION0

RW

R

00001101

DECIMATION(7:0)

Decimation

Factor

104

RXDATARATE2

RW

R

00000000

RXDATARATE(23:16)

Receiver

Datarate

105

RXDATARATE1

RW

R

00111101

RXDATARATE(15:8)

Receiver

Datarate

106

RXDATARATE0

RW

R

10001010

RXDATARATE(7:0)

Receiver

Datarate

107

MAXDROFFSET2

RW

R

00000000

MAXDROFFSET(23:16)

Maximum

Receiver

Datarate Offset

108

MAXDROFFSET1

RW

R

00000000

MAXDROFFSET(15:8)

Maximum

Receiver

Datarate Offset

109

MAXDROFFSET0

RW

R

10011110

MAXDROFFSET(7:0)

Maximum

Receiver

Datarate Offset

10A

MAXRFOFFSET2

RW

R

0–––0000

FREQ

–

–

–

MAXRFOFFSET(19:16)

Maximum

OFFS

Receiver RF

CORR

Offset

10B

MAXRFOFFSET1

RW

R

00010110

MAXRFOFFSET(15:8)

Maximum

Receiver RF

Offset

10C

MAXRFOFFSET0

RW

R

10000111

MAXRFOFFSET(7:0)

Maximum

Receiver RF

Offset

10D

FSKDMAX1

RW

R

00000000

FSKDEVMAX(15:8)

Four FSK Rx

Deviation

10E

FSKDMAX0

RW

R

10000000

FSKDEVMAX(7:0)

Four FSK Rx

Deviation

10F

FSKDMIN1

RW

R

11111111

FSKDEVMIN(15:8)

Four FSK Rx

Deviation

110

FSKDMIN0

RW

R

10000000

FSKDEVMIN(7:0)

Four FSK Rx

Deviation

111

AFSKSPACE1

RW

R

––––0000

–

–

–

–

AFSKSPACE(11:8)

AFSK Space (0)

Frequency

www.onsemi.com

24

AND9902/D

Table 23. CONTROL REGISTER MAP (continued)

Bit

Addr

Name

Dir

Ret

Reset

7

6

5

4

3

2

1

0

Description

112

AFSKSPACE0

RW

R

01000000

AFSKSPACE(7:0)

AFSK Space (0)

Frequency

113

AFSKMARK1

RW

R

––––0000

–

–

–

–

AFSKMARK(11:8)

AFSK Mark (1)

Frequency

114

AFSKMARK0

RW

R

01110101

AFSKMARK(7:0)

AFSK Mark (1)

Frequency

115

AFSKCTRL

RW

R

–––00100

–

–

–

AFSKSHIFT0(4:0)

AFSK Control

116

AMPLFILTER

RW

R

––––0000

–

–

–

–

AMPLFILTER(3:0)

Amplitude Filter

117

RFZIGZAGAMPL

RW

R

00000000

ZIGZAGAMPLEXP(3:0)

ZIGZAGAMPLMANT(3:0)

RF Zigzag

Scanner

Amplitude

Exponent and

Mantissa

118

RFZIGZAGFREQ

RW

R

00000000

ZIGZAGFREQ(7:0)

RF Zigzag

Scanner

Frequency

119

RFFREQUENCYLEAK

RW

R

–––

–

–

–

RFFREQUENCYLEAK(4:0)

RF Frequency

00000

Recovery Loop

Leakiness

11A

FREQUENCYLEAK

RW

R

0–––0000

PH

–

–

–

FREQUENCYLEAK(3:0)

Baseband

HALF

Frequency

ACC

Recovery Loop

Leakiness

11B

RXPARAMSETS

RW

R

00000000

RXPS3(1:0)

RXPS2(1:0)

RXPS1(1:0)

RXPS0(1:0)

Receiver

Parameter Set

Indirection

11C

RXPARAMCURSET

R

R

––––––––

–

–

–

RXSI(2

RXSN(1:0)

RXSI(1:0)

Receiver

)

Parameter

Current Set

11D

RSSIIRQTHRESH

RW

R

00000000

RSSIIRQTHRESH(7:0)

RSSI Interrupt

Threshold

11E

RSSIIRQDIR

RW

R

–––––––0

–

–

–

–

–

–

–

RSSIII

RSSI Interrupt

RQ

Threshold

DIR

Direction

F00

LNABIAS

RW

R

00000000

–

–

–

–

LNABIAS (3:0)

LNA Bias

(thermometer

encoded)

F44

ADCDCCFG0

RW

R

00001111

–

–

ADCS

–

–

–

–

−

For proper data

WAPIQ

demodulation,

set bit 5 of this

register to 1.

Leave all other

bits as already

programmed.

Receiver Parameter Set 0

120

AGCTARGET0

RW

R

10010110

AGCTARGET0(7:0)

AGC Target

121

AGCINCREASE0

RW

R

01011000

AGCDECAY0(4:0)

AGCMINDA0(2:0)

AGC Gain

Increase

Settings

122

AGCREDUCE0

RW

R

00100000

AGCATTACK0(4:0)

AGCMAXDA0(2:0)

AGC Gain

Reduce Settings

123

AGCAHYST0

RW

R

–––––000

–

–

–

–

–

AGCAHYST0(2:0)

AGC Digital

Threshold

Range

124

TIMEGAIN0

RW

R

11111000

TIMEGAIN0M(3:0)

TIMEGAIN0E(3:0)

Timing Gain

125

DRGAIN0

RW

R

11110010

DRGAIN0M(3:0)

DRGAIN0E(3:0)

Data Rate Gain

126

PHASEGAIN0

RW

R

11––0011

FILTERIDX0(1:0)

–

–

PHASEGAIN0(3:0)

Filter Index,

Phase Gain

127

FREQGAINA0

RW

R

00001111

FREQ

FREQ

FREQ

FREQ

FREQGAINA0(3:0)

Frequency Gain

LIM0

MODU

HALFM

AMPL

A

LO0

OD0

GATE0

128

FREQGAINB0

RW

R

00–11111

FREQ

FREQ

–

FREQGAINB0(4:0)

Frequency Gain

FREEZ

AVG0

B

E0

129

FREQGAINC0

RW

R

–––01010

–

–

–

FREQGAINC0(4:0)

Frequency Gain

C

12A

FREQGAIND0

RW

R

00–01010

RFFRE

ZIGZA

–

FREQGAIND0(4:0)

Frequency Gain

Q

G

D

FREEZ

FREEZ

E0

E0

12B

AMPLGAIN0

RW

R

010–0110

AMPL

AMPL

AMPL

–

AMPLGAIN0(3:0)

Amplitude Gain

AVG0

AGC0

HS0

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25