Onkyo SKW-320 Service Manual

BLOCK DIAGRAM

SKW-320 : POWERED SUBWOOFER

HTP-320

HTP-320

SCHEMATIC DIAGRAM

SKW-320: POWERED SUBWOOFER

HT-320FGH

LINE
INPUT

INPUT PC BOARD

U02

OUTPUT
LEVEL

VR / LED PC BOARD

U03

HTP-320

SPEAKER

MAIN PC BOARD

HTP-320

A

SCHEMATIC DIAGRAM

SKW-320: POWERED SUBWOOFER

1

2

BCDEFGH

SPEAKER

3

LINE
INPUT

OUTPUT
LEVEL

4

INPUT PC BOARD

U02

VR / LED PC BOARD

U03

LED
RED : STANDBY
GREEN : ON

U01

AC 120V / 60Hz

MAIN PC BOARD

5

PC BOARD CONNECTION DIAGRAM

SKW-320 : POWERED SUBWOOFER

INPUT PC BOARD

HTP320

MAIN PC BOARD

VR / LED PC BOARD

HTP-320

HTP-320

A

PRINTED CIRCUIT BOARD VIEW

SKW-320POWERED SUBWOOFER

MAIN PC BOARD

U01

1

2

BCD

3

4

INPUT PC BOARD

U02

5

VR / LED PC BOARD

U03

No PC board view
Look over the actual PC board on hand

®

TDA7293

120V - 100W DMOS AUDIO AMPLIFIER WITH MUTE/ST-BY

VERY HIG H OPERATI NG VOLTAGE R ANGE
(±50V)

DMOS POWER STAGE
HIGH OUTPUT POWER (100W @ THD =

10%, R

L

= 8Ω, VS = ±40V)
MUTING/STAND- BY FUNC TION S
NO SWITCH ON/OFF NOISE
VERY LOW DISTORTION
VERY LOW NOISE
SHORT CIRCUIT PROTECTED (WITH NO IN-

PUT SIGNAL APPLIED)
THERMAL SHUTDOWN
CLIP DETECTOR
MODULARITY (MORE DEVICES CAN BE

EASILY CONNECTED IN PARALLEL TO
DRIVE VERY LOW IMPEDANCES)

DESCRIPTION

The TDA7293 is a monolithic integrated circuit in
Multiwatt15 package, intended for use as audio
class AB amplifier in Hi-Fi field applications
(Home Stereo, self powered loudspeakers, Top-

Figure 1: Typical Application and Test Circuit

MULTIPOWER BCD TECHNOLOGY

Multiwatt15V Multiwatt15H

ORDERING NUMBERS:

TDA7293V TDA7293HS

class TV). Thanks to the wide voltage range and
to the high out current c apability it is able to sup­ply the highest power into both 4Ω and 8Ω loads.

The built in muting function with turn on delay
simplifies the remote operation avoiding switching
on-off noises.
Parallel mode is made possible by connecting
more device through of pin11. High out put power
can be delivered to very low impedance loads, so
optimizing the thermal dissipation of the system.

VMUTE

VSTBY

January 2003

R3 22K

C2

R2

22µF

680Ω

C1 470nF

R1 22K

R5 10K

R4 22K

C3 10µF C4 10µF

IN- 2

IN+

3

4

SGND
(**)

10

MUTE

9

STBY

(*) see Application note
(**) for SLAVE function

C7 100nF C6 1000µF

BUFFER DRIVER

11

713

-

+

MUTE

STBY

1
STBY-GND

THERMAL

SHUTDOWN

-Vs -PWVs

C9 100nF C8 1000µF

-Vs

+Vs

+PWVs+Vs

S/C

PROTECTION

158

14

12

6
5

D97AU805A

OUT

BOOT
LOADER

C5

22µF

BOOTSTRAP

CLIP DET

(*)

VCLIP

1/15

TDA7293

PIN CONNECTION (Top view)

-VS (POWER)
OUT
+V

(POWER)

S

BOOTSTRAP LOADER
BUFFER DRIVER
MUTE
STAND-BY

-V

(SIGNAL)

S

+V

(SIGNAL)

S

BOOTSTRAP
CLIP AND SHORT CIRCUIT DETECTOR
SIGNAL GROUND
NON INVERTING INPUT
INVERTING INPUT
STAND-BY GND

TAB CONNECTED TO PIN 8

15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

D97AU806

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

S

V

1

V

2

- V

V

2

V

3

V

4

V

5

V

6

V

9

V

10

V

11

V

12

I

O

P

tot

T

op

, T

T

stg

Supply Voltage (No Signal)
V

STAND-BY

GND Voltage Referred to -VS (pin 8) 90 V
Input Voltage (inverting) Referred to -VS 90 V
Maximum Differential Inputs

3

Input Voltage (non inverting) Referred to -VS 90 V
Signal GND Voltage Referred to -VS 90 V
Clip Detector Voltage Referred to -VS 120 V
Bootstrap Voltage Referred to -VS 120 V
Stand-by Voltage Referred to -VS 120 V
Mute Voltage Referred to -VS 120 V
Buffer Voltage Referred to -VS 120 V
Bootstrap Loader Voltage Referred to -VS 100 V
Output Peak Current 10 A
Power Dissipation T

= 70°C50W

case

Operating Ambient Temperature Range 0 to 70
Storage and Junction Temperature 150

j

60 V

±

30 V

±

C

°

C

°

THERMAL DATA

Symbol Description

Thermal Resistance Junction-case 1 1.5

2/15

R

th j-case

Typ

Max Unit

C/W

°

TDA7293

ELECTRICAL CHARACTERISTICS (Refer to the Test Circuit V

T

= 25°C, f = 1 kHz; unless otherwise specified).

amb

= ±40V, RL = 8Ω, Rg = 50 Ω;

S

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

I
I

V

I

OS

P

Supply Range

S

Quiescent Current 50 100 mA

q

Input Bias Current 0.3 1

b

Input Offset Voltage -10 10 mV

OS

Input Offset Current 0.2
RMS Continuous Output Power d = 1%:

O

R

= 4

VS = ± 29V,

Ω;

L

d = 10%

= 4Ω ; VS = ±29V

R

L

d Total Harmonic Distortion (**) PO = 5W; f = 1kHz

P

= 0.1 to 50W; f = 20Hz to 15kHz

O

I

SC

Current Limiter Threshold VS ≤ ± 40V 6.5 A

12

±

75 80

90 100

100

0.005

80

50 V

±

0.1

SR Slew Rate 5 10 V/µs

G
G
e

R

SVR Supply Voltage Rejection f = 100Hz; V

T

Open Loop Voltage Gain 80 dB

V

Closed Loop Voltage Gain (1) 29 30 31 dB

V

Total Input Noise A = curve

N

f = 20Hz to 20kHz

Input Resistance 100 k

i

= 0.5Vrms 75 dB

ripple

Thermal Protection DEVICE MUTED 150

S

1
310

DEVICE SHUT DOWN 160

STAND-BY FUNCTION

V
V

ATT

I

q st-by

ST on
ST off

Stand-by on Threshold 1.5 V
Stand-by off Threshold 3.5 V
Stand-by Attenuation 70 90 dB

st-by

Quiescent Current @ Stand-by 0.5 1 mA

MUTE FUNCTION

V
V

ATT

Mon
Moff

Mute on Threshold 1.5 V
Mute off Threshold 3.5 V
Mute AttenuatIon 60 80 dB

mute

(Ref: to pin 1)

(Ref: to pin 1)

CLIP DETECTOR

Duty Duty Cycle ( pin 5) THD = 1% ; RL = 10KΩ to 5V 10 %

THD = 10% ;

30 40 50 %

RL = 10KΩ to 5V

I

CLEAK

SLAVE FUNCTION pin 4

V

Slave

V

Master

Note (1):
Note:

Note (**):

SlaveThreshold 1V
Master Threshold 3 V

Vmin

G

26dB

≥

Pin 11 only for modular connection. Max external load 1MΩ/10 pF, only for test purpose

Tested with optimized Application Board (see fig. 2)

(Ref: to pin 8 -V

PO = 50W 3

)

S

A

µ

A

µ

W

W

%
%

V

µ

V

µ

Ω

C

°

C

°

A

µ

3/15

TDA7293

Figure 2: Typical Application P.C. Board and Component Layout (scale 1:1)

4/15

TDA7293

APPLICATION SUGGES TION S (see Test and Application Circuits of the Fig. 1)

The recommended values of t he external components are t hose shown on t he application circuit o f Fig­ure 1. Different values can be used; the following table can help the designer.

COMPONENTS SUGGESTED VALUE PURPOSE

LARGER THAN

SUGGESTED

R1 (*) 22k INPUT RESISTANCE INCREASE INPUT

IMPEDANCE

R2 680

Ω

CLOSED LOOP GAIN

DECREASE OF GAIN INCREASE OF GAIN

SMALLER THAN

SUGGESTED

DECREASE INPUT

IMPEDANCE

SET TO 30dB (**)

R3 (*) 22k INCREASE OF GAIN DECREASE OF GAIN

R4 22k ST-BY TIME

CONSTANT

LARGER ST-BY

ON/OFF TIME

SMALLER ST-BY

ON/OFF TIME;

POP NOISE

R5 10k MUTE TIME

CONSTANT

C1 0.47µF INPUT DC

DECOUPLING

LARGER MUTE

ON/OFF TIME

SMALLER MUTE

ON/OFF TIME
HIGHER LOW

FREQUENCY

CUTOFF

C2 22µF FEEDBACK DC

DECOUPLING

HIGHER LOW
FREQUENCY

CUTOFF

C3 10µF MUTE TIME

CONSTANT

C4 10µF ST-BY TIME

CONSTANT

LARGER MUTE

ON/OFF TIME

LARGER ST-BY

ON/OFF TIME

SMALLER MUTE

ON/OFF TIME

SMALLER ST-BY

ON/OFF TIME;

POP NOISE

C5 22µFXN (***) BOOTSTRAPPING SIGNAL

C6, C8 1000µF SUPPLY VOLTAGE

C7, C9 0.1µF SUPPLY VOLTAGE

(*) R1 = R3 for pop optimization
(**) Closed Loop Gain has to be ≥ 26dB
(***) Multiplay this value for the number of modular part connected

D98AU821

S

)

Slave function: pin 4 (Ref to pin 8 -V

+3V

-V

S

-V

+1V

S

-V

S

MASTER

UNDEFINED

SLAVE

DEGRADATION AT
LOW FREQUENCY

BYPASS

DANGER OF

BYPASS

OSCILLATION

Note:

If in the application, the speakers are connected
via long wires, it is a good rule to add between
the output and GND, a Boucherot Cell, in order to
avoid dangerous spurious oscillations when the
speakers terminal are shorted.

The suggested Boucherot Resistor is 3.9Ω/2W
and the capacitor is 1µF.

5/15

TDA7293

INTRODUCTION

In consumer electronics, an increasing demand
has arisen for very high power monolithic audio
amplifiers able to match, with a low cost, the per­formance obtained from the best discrete de­signs.

The task of realizing this linear integrated circuit
in conventional bipolar technology is made ex­tremely difficult by the occurence of 2nd break­down phoenomenon. It limits the safe operating
area (SOA) of the power devices, and, as a con­sequence, the maximum attainable output power,
especially in presence of highly reactive loads.

Moreover, full exploitation of the SOA translates
into a substantial increase in circuit and layout
complexity due to the need of sophisticated pro­tection circuits.

To overcome these substantial drawbacks, the
use of power MOS devices, which are immune
from secondary breakdown is highly desirable.

The device described has therefore been devel­oped in a mixed bipolar-MOS high voltage tech­nology called BCDII 100/120.

1) Output Stage

The main design task in developping a po wer op­erational amplifier, independently of the technol­ogy used, is that of realization of the output stage.

The solution shown as a principle shematic by
Fig3 represents the DMOS unity - gain output
buffer of the TDA7293.

This large-signal, high-power buffer must be ca­pable of handling extremely high current and volt­age levels while maintaining acceptably low har­monic distortion and good behaviour over

frequency response; moreover, an accurate con­trol of quiescent current is required.

A local linearizing feedback, provided by differen­tial amplifier A, is used to fullfil the above require­ments, allowing a simple and effective quiescent
current setting.

Proper biasing of the power output transistors
alone is however not enough to guarantee the ab­sence of crossover distortion.

While a linearization of the DC transfer charac­teristic of the stage is obtained, the dynamic be­haviour of the system must be taken into account.

A significant aid in keeping the distortion contrib­uted by the final stage as low as possible is pro­vided by the compensation scheme, which ex­ploits the direct connection of the Miller capacitor
at the amplifier’s output to introduce a local AC
feedback path enclosing the output stage itself.

2) Protections

In designing a power IC, particular attention must
be reserved to the circuits devoted to protection
of the device from short circuit or overload condi­tions.

Due to the absence of the 2nd breakdown phe­nomenon, the SOA of the power DMOS tr ansis­tors is delimited only by a maximum dissipation
curve dependent on the duration of the applied
stimulus.

In order to fully exploit the capabilities of the
power transistors, the protection scheme imple­mented in this device combines a conventional
SOA protection circuit with a novel local tempera­ture sensing technique which " dynamically" con­trols the maximum dissipation.

Figure 3: Principle Schematic of a DMOS unity-gain buffer.

6/15

Figure 4: Turn ON/OFF Suggested Sequence

+Vs

(V)

+40

-40

-Vs
V

IN

(mV)

V

ST-BY

PIN #9

(V)

5V

TDA7293

V

MUTE

PIN #10

(V)

I

Q

(mA)

V

OUT
(V)

OFF

ST-BY

5V

PLAY

MUTE MUTE

In addition to the overload protection described
above, the device features a thermal shutdown
circuit which initially puts the device into a muting
state (@ Tj = 150
Tj = 160

o

C).

o

C) and then into stand-by (@

Full protection against electrostatic discharges on
every pin is included.

Figure 5: Single Signal ST-BY/MUTE Control

Circuit

MUTE STBY

MUTE/

ST-BY

20K

10K 30K

1N4148

10µF10µF

D93AU014

3) Other Features
The device is provided with both stand-by and

ST-BY OFF

D98AU817

mute functions, independently driven by two
CMOS logic compatible input pins.

The circuits dedicated to the switching on and off
of the amplifier have been carefully optimized to
avoid any kind of uncontrolled audible transient at
the output.

The sequence that we recommend during the
ON/OFF transients is shown by Figure 4.

The application of figure 5 shows the possibility of
using only one command for both st-by and mute
functions. On both the pins, the maximum appli­cable range corresponds to the oper ating supply
voltage.

APPLICATION INFORMATION

HIGH-EFFICIENCY
Constraints of implementing high power solutions

are the power dissipation and the size of the
power supply. These are both due to the low effi­ciency of conventional AB class amplifier ap­proaches.

Here below (figure 6) is described a circuit pro­posal for a high efficiency amplifier which can be
adopted for both HI-FI and CAR-RADIO applica­tions.

7/15