Omron SYSMAC CV, CV2000, CVM1, CV500, CV1000 Operation Manual

SYSMAC CV-series
CV500/CV1000/CV2000/CVM1
Programmable Controllers

Operation Manual: Ladder Diagrams

Revised August 1998

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Notice:

OMRON products are manufactured for use according to proper procedures by a qualified operator
and only for the purposes described in this manual.

The following conventions are used to indicate and classify precautions in this manual. Always heed
the information provided with them. Failure to heed precautions can result in injury to people or dam­age to property.

DANGER Indicates an imminently hazardous situation which, if not avoided, will result in death or

serious injury.

WARNING Indicates a potentially hazardous situation which, if not avoided, could result in death or

serious injury.

Caution Indicates a potentially hazardous situation which, if not avoided, may result in minor or

moderate injury, or property damage.

OMRON Product References

All OMRON products are capitalized in this manual. The word “Unit” is also capitalized when it refers
to an OMRON product, regardless of whether or not it appears in the proper name of the product.

The abbreviation “Ch,” which appears in some displays and on some OMRON products, often means
“word” and is abbreviated “Wd” in documentation in this sense.

The abbreviation “PC” means Programmable Controller and is not used as an abbreviation for any­thing else.

Visual Aids

The following headings appear in the left column of the manual to help you locate different types of
information.

Note Indicates information of particular interest for efficient and convenient operation

of the product.

1, 2, 3...

1. Indicates lists of one sort or another, such as procedures, checklists, etc.

 OMRON, 1992

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any
form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permis­sion of OMRON.

No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is
constantly striving to improve its high-quality products, the information contained in this manual is subject to change
without notice. Every precaution has been taken in the preparation of this manual. Nevertheless, OMRON assumes no
responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the informa­tion contained in this publication.

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TABLE OF CONTENTS

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PRECAUTIONS xiii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Intended Audience xiv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 General Precautions xiv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Safety Precautions xiv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Operating Environment Precautions xv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Precautions xv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 1

Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1 Overview 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2 Relay Circuits: The Roots of PC Logic 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-3 PC Terminology 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-4 OMRON Product Terminology 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-5 Overview of PC Operation 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-6 PC Operating Modes 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-7 Peripheral Devices 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-8 CV-series Manuals 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-9 C-series–CV-series System Compatibility 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-10 Networks and Remote I/O Systems 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-11 New CPUs and Related Units 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-12 CPU Comparison 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-13 Improved Specifications 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 2

Hardware Considerations 21. . . . . . . . . . . . . . . . . . . . . . . . .

2-1 CPU Components 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2 Program Memory 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3 Memory Cards 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-4 Data Memory and Expansion Data Memory Unit 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-5 I/O Control Unit and I/O Interface Unit Displays 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-6 Peripheral Devices 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-7 PC Configuration 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 3

Memory Areas 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1 Introduction 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2 Data Area Structure 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3 CIO (Core I/O) Area 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-4 TR (Temporary Relay) Area 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-5 CPU Bus Link Area 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6 Auxiliary Area 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-7 Transition Area 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-8 Step Area 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-9 Timer Area 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-10 Counter Area 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-11 DM and EM Areas 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-12 Index and Data Registers (IR and DR) 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TABLE OF CONTENTS

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SECTION 4

Writing Programs 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1 Basic Procedure 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-2 Instruction Terminology 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3 Basic Ladder Diagrams 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-4 Mnemonic Code 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-5 Branching Instruction Lines 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-6 Jumps 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-7 Controlling Bit Status 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-8 Intermediate Instructions 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-9 Work Bits (Internal Relays) 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-10 Programming Precautions 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-11 Program Execution 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-12 Using Version-2 CVM1 CPUs 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13 Data Formats 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 5

Instruction Set 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1 Notation 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-2 Instruction Format 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-3 Data Areas, Definers, and Flags 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-4 Differentiated and Immediate Refresh Instructions 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-5 Coding Right-hand Instructions 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-6 Ladder Diagram Instructions 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-7 Bit Control Instructions 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-8 INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003) 134. . . . . . . . . . . . . . . . . .

5-9 JUMP and JUMP END: JMP(004) and JME(005) 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-10 CONDITIONAL JUMP: CJP(221)/CJPN(222) 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-11 END: END(001) 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-12 NO OPERATION: NOP(000) 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-13 Timer and Counter Instructions 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-14 Shift Instructions 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-15 Data Movement Instructions 187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-16 Comparison Instructions 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-17 Conversion Instructions 219. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-18 BCD Calculation Instructions 249. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-19 Binary Calculation Instructions 261. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-20 Symbol Math Instructions 272. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-21 Floating-point Math Instructions 293. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-22 Increment/Decrement Instructions 314. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-23 Special Math Instructions 319. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-24 PID and Related Instructions 330. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-25 Logic Instructions 341. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-26 Time Instructions 349. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-27 Special Instructions 354. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-28 Flag/Register Instructions 366. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) 368. . . . . . . . . . . . . . . . . . . . . . .

5-30 Subroutines 377. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-31 Interrupt Control 382. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-32 Stack Instructions 389. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-33 Data Tracing 393. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-34 Memory Card Instructions 396. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-35 Special I/O Instructions 404. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-36 Network Instructions 413. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-37 SFC Control Instructions 427. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-38 Block Programming Instructions 438. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TABLE OF CONTENTS

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SECTION 6

Program Execution Timing 451. . . . . . . . . . . . . . . . . . . . . . . .

6-1 PC Operation 452. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-2 Cycle Time 464. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-3 Calculating Cycle Time 470. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-4 Instruction Execution Times 472. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-5 I/O Response Time 486. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 7

PC Setup 495. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-1 PC Setup Overview 496. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-2 PC Setup Details 497. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-3 PC Setup Default Settings 501. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 8

Error Processing 503. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-1 Alarm Indicators 504. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-2 Programmed Alarms and Error Messages 504. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-3 Reading and Clearing Errors and Messages 504. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-4 Error Messages 504. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-5 Error Flags 509. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendices

A Instruction Set 511. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B Error and Arithmetic Flag Operation 569. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C PC Setup Default Settings 575. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D Data Areas 577. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E I/O Assignment Sheets 583. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F Program Coding Sheet 589. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G Data Conversion Table 593. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

H Extended ASCII 595. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Glossary 597. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Index 619. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Revision History 629. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xi

About this Manual:

This manual describes ladder diagram programming and memory allocation in the SYSMAC CV-series Program­mable Controllers (PCs) (CV500, CV1000, CV2000, and CVM1). This manual is designed to be used together with
two other CV-series PC operation manuals and an installation guide. The entire set of CV-series PC manuals is listed
below. Only the basic portions of the catalog numbers are given; be sure you have the most recent version for your
area.

Manual Cat. No.

CV-series PC Installation Guide W195
CV-series PC Operation Manual: SFC W194
CV-series PC Operation Manual: Ladder Diagrams W202
CV-series PC Operation Manual: Host Interface W205

Programming and operating CV -series PCs are performed with the CV Support Software (CVSS), the SYSMAC Sup­port Software (SSS), and the CV-series Programming Console for which the following manuals are available.

Product Manuals

CVSS The CV Series Getting Started Guidebook (W203) and the CV Support Software Opera-

tion Manuals: Basics (W196), Offline (W201), and Online (W200).

SSS SYSMAC Support Software Operation Manuals: Basics (W247), C-series PC Opera-

tions (W248), and CVM1 Operations (W249)

CV-series Programming Console CVM1-PRS21-E Programming Console Operation Manual (W222)

Note The CVSS does not support new instructions added for version-2 CVM1 PCs. The SSS does not support SFC

programming (CV500, CV1000, or CV2000).

Please read this manual completely together with the other CV-series manuals and be sure you understand the infor­mation provide before attempting to install, program, or operate a CV-series PC. The basic content of each section of
this manual is outlined below.

Section 1

gives a brief overview of the history of Programmable Controllers and explains terms commonly used in
ladder-diagram programming. It also provides an overview of the process of programming and operating a PC. A list
of the manuals available to use with this manual is also provided.

Section 2

provides information on hardware aspects of the CV-series PCs relevant to programming and software
operation. This information is covered in more detail in the

CV-series PC Installation Guide

.

Section 3

describes the way in which PC memory is broken into various areas for different purposes. The contents of
each area and addressing conventions are also described.

Section 4

explains the basic steps and concepts involved in writing a basic ladder diagram program. The entire set
of instructions used in programming is described in

Section 5 Instruction Set

.

Section 5

explains each instruction in the CV-series PC instruction sets and provides the ladder diagram symbols,
data areas, and flags used with each. The instructions provided by the CV-series PCs are described in following sub­sections by instruction group.

Section 6

explains the execution cycle of the PC and shows how to calculate the cycle time and I/O response times.
I/O response times in Link Systems are described in the individual System Manuals. These manuals are listed at the
end of

Section 1 Introduction

.

Section 7

provides tables that list the parameters in the PC Setup, provide examples of normal application, and
provides the default values. The use of each parameter in the PC Setup is described where relevant in this manual
and in other CV-series manuals.

Section 8

provides information on hardware and software errors that may occur during PC operation. Although de­scribed mainly in

Section 3 Memory Areas

, flags and other error information provided in the Auxiliary Area are listed in

8-5 Error Flags

.

Various appendices are also provided for convenience (see table of contents for a list).

WARNING Failure to read and understand the information provided in this manual may result in

personal injury or death, damage to the product, or product failure. Please read each
section in its entirety and be sure you understand the information provided in the section
and related sections before attempting any of the procedures or operations given.

!

xiii

PRECAUTIONS

This section provides general precautions for using the Programmable Controller (PC) and related devices.

The information contained in this section is important for the safe and reliable application of the Programmable Con­troller. You must read this section and understand the information contained before attempting to set up or operate a
PC system.

1 Intended Audience xiv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 General Precautions xiv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Safety Precautions xiv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Operating Environment Precautions xv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Precautions xv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

!

!

!

!

!

!

!

!

3Safety Precautions

xiv

1 Intended Audience

This manual is intended for the following personnel, who must also have knowl­edge of electrical systems (an electrical engineer or the equivalent).

• Personnel in charge of installing FA systems.

• Personnel in charge of designing FA systems.

• Personnel in charge of managing FA systems and facilities.

2 General Precautions

The user must operate the product according to the performance specifications
described in the operation manuals.

Before using the product under conditions which are not described in the manual
or applying the product to nuclear control systems, railroad systems, aviation
systems, vehicles, combustion systems, medical equipment, amusement ma­chines, safety equipment, and other systems, machines, and equipment that
may have a serious influence on lives and property if used improperly, consult
your OMRON representative.

Make sure that the ratings and performance characteristics of the product are
sufficient for the systems, machines, and equipment, and be sure to provide the
systems, machines, and equipment with double safety mechanisms.

This manual provides information for programming and operating the Unit. Be
sure to read this manual before attempting to use the Unit and keep this manual
close at hand for reference during operation.

WARNING It is extremely important that a PC and all PC Units be used for the specified

purpose and under the specified conditions, especially in applications that can
directly or indirectly affect human life. You must consult with your OMRON
representative before applying a PC System to the above-mentioned
applications.

3 Safety Precautions

WARNING Do not attempt to take any Unit apart while the power is being supplied. Doing so

may result in electric shock.

WARNING Do not touch any of the terminals while the power is being supplied. Doing so

may result in electric shock.

WARNING Do not attempt to disassemble, repair. or modify any Units. Any attempt to do so

may result in malfunction, fire, or electric shock.

WARNING There is a lithium battery built into the SRAM Memory Cards. Do not short the

positive and negative terminals of the battery, charge the battery, attempt to take
it apart, subject it to pressures that would deform it, incinerate it, or otherwise
mistreat it. Doing any of these could cause the battery to erupt, ignite, or leak.

Caution Execute online edit only after confirming that no adverse effects will be caused

by extending the cycle time. Otherwise, the input signals may not be readable.

Caution Confirm safety at the destination node before transferring a program to another

node or changing the I/O memory area. Doing either of these without confirming
safety may result in injury.

Caution Tighten the screws on the terminal block of the AC Power Supply Unit to the

torque specified in the operation manual. The loose screws may result in burning
or malfunction.

!

!

!

!

!

5Application Precautions

xv

4 Operating Environment Precautions

Caution Do not operate the control system in the following places:

• Locations subject to direct sunlight.

• Locations subject to temperatures or humidity outside the range specified in

the specifications.

• Locations subject to condensation as the result of severe changes in tempera­ture.

• Locations subject to corrosive or flammable gases.

• Locations subject to dust (especially iron dust) or salts.

• Locations subject to exposure to water, oil, or chemicals.

• Locations subject to shock or vibration.

Caution Take appropriate and sufficient countermeasures when installing systems in the

following locations:

• Locations subject to static electricity or other forms of noise.

• Locations subject to strong electromagnetic fields.

• Locations subject to possible exposure to radioactivity.

• Locations close to power supplies.

Caution The operating environment of the PC System can have a large effect on the lon-

gevity and reliability of the system. Improper operating environments can lead to
malfunction, failure, and other unforeseeable problems with the PC System. Be
sure that the operating environment is within the specified conditions at installa­tion and remains within the specified conditions during the life of the system.

5 Application Precautions

Observe the following precautions when using the PC System.

WARNING Always heed these precautions. Failure to abide by the following precautions

could lead to serious or possibly fatal injury.

• Always connect to a class-3 ground (to 100 Ω or less) when installing the Units.
Not connecting to a class-3 ground may result in electric shock.

• Always turn off the power supply to the PC before attempting any of the follow­ing. Not turning off the power supply may result in malfunction or electric
shock.

• Mounting or dismounting I/O Units, CPU Units, Memory Cassettes, or any
other Units.

• Assembling the Units.

• Setting DIP switches or rotary switches.

• Connecting or wiring the cables.

• Connecting or disconnecting the connectors.

Caution Failure to abide by the following precautions could lead to faulty operation of the

PC or the system, or could damage the PC or PC Units. Always heed these pre­cautions.

• Fail-safe measures must be taken by the customer to ensure safety in the
event of incorrect, missing, or abnormal signals caused by broken signal lines,
momentary power interruptions, or other causes.

5Application Precautions

xvi

• Interlock circuits, limit circuits, and similar safety measures in external circuits
(i.e., not in the Programmable Controller) must be provided by the customer.

• Always use the power supply voltage specified in the operation manuals. An
incorrect voltage may result in malfunction or burning.

• Take appropriate measures to ensure that the specified power with the rated
voltage and frequency is supplied. Be particularly careful in places where the
power supply is unstable. An incorrect power supply may result in malfunction.

• Install external breakers and take other safety measures against short-circuit­ing in external wiring. Insufficient safety measures against short-circuiting may
result in burning.

• Do not apply voltages to the Input Units in excess of the rated input voltage.
Excess voltages may result in burning.

• Do not apply voltages or connect loads to the Output Units in excess of the
maximum switching capacity. Excess voltage or loads may result in burning.

• Disconnect the functional ground terminal when performing withstand voltage
tests. Not disconnecting the functional ground terminal may result in burning.

• Install the Unit properly as specified in the operation manual. Improper installa­tion of the Unit may result in malfunction.

• Be sure that all the mounting screws, terminal screws, and cable connector
screws are tightened to the torque specified in the relevant manuals. Incorrect
tightening torque may result in malfunction.

• Leave the label attached to the Unit when wiring. Removing the label may re­sult in malfunction.

• Remove the label after the completion of wiring to ensure proper heat dissipa­tion. Leaving the label attached may result in malfunction.

• Use crimp terminals for wiring. Do not connect bare stranded wires directly to
terminals. Connection of bare stranded wires may result in burning.

• Double-check all the wiring before turning on the power supply. Incorrect wir­ing may result in burning.

• Mount the Unit only after checking the terminal block completely.

• Be sure that the terminal blocks, Memory Units, expansion cables, and other

items with locking devices are properly locked into place. Improper locking
may result in malfunction.

• Check the user program for proper execution before actually running it on the
Unit. Not checking the program may result in an unexpected operation.

• Confirm that no adverse effect will occur in the system before attempting any of
the following. Not doing so may result in an unexpected operation.

• Changing the operating mode of the PC.

• Force-setting/force-resetting any bit in memory.

• Changing the present value of any word or any set value in memory.

• Resume operation only after transferring to the new CPU Unit the contents of

the DM and HR Areas required for resuming operation. Not doing so may result
in an unexpected operation.

• Do not pull on the cables or bend the cables beyond their natural limit. Doing
either of these may break the cables.

• Do not place objects on top of the cables. Doing so may break the cables.

• When replacing parts, be sure to confirm that the rating of a new part is correct.

Not doing so may result in malfunction or burning.

• Before touching the Unit, be sure to first touch a grounded metallic object in
order to discharge any static built-up. Not doing so may result in malfunction or
damage.

1

SECTION 1

Introduction

This section gives a brief overview of the history of Programmable Controllers and explains terms commonly used in
ladder-diagram programming. It also provides an overview of the process of programming and operating a PC and ex­plains basic terminology used with OMRON PCs. A list of the manuals available to use with this manual for special PC
applications and products is also provided.

1-1 Overview 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2 Relay Circuits: The Roots of PC Logic 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-3 PC Terminology 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-4 OMRON Product Terminology 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-5 Overview of PC Operation 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-6 PC Operating Modes 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-7 Peripheral Devices 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-8 CV-series Manuals 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-9 C-series–CV-series System Compatibility 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-10 Networks and Remote I/O Systems 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-11 New CPUs and Related Units 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-12 CPU Comparison 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-13 Improved Specifications 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-13-1 Upgraded Specifications 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-13-2 Version-1 CPUs 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-13-3 Version-2 CVM1 CPUs 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-13-4 Upgraded Specifications 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

1-1 Overview

A PC (Programmable Controller) is basically a CPU (Central Processing Unit)
containing a program and connected to input and output (I/O) devices. The pro­gram controls the PC so that when an input signal from an input device turns ON
or OFF, the appropriate response is made. The response normally involves turn­ing ON or OFF an output signal to some sort of output device. The input devices
could be photoelectric sensors, pushbuttons on control panels, limit switches, or
any other device that can produce a signal that can be input into the PC. The
output devices could be solenoids, indicator lamps, relays turning on motors, or
any other devices that can be activated by signals output from the PC.

For example, a sensor detecting a passing product turns ON an input to the PC.
The PC responds by turning ON an output that activates a pusher that pushes
the product onto another conveyor for further processing. Another sensor, posi­tioned higher than the first, turns ON a different input to indicate that the product
is too tall. The PC responds by turning on another pusher positioned before the
pusher mentioned above to push the too-tall product into a rejection box.

Although this example involves only two inputs and two outputs, it is typical of the
type of control operation that PCs can achieve. Actually even this example is
much more complex than it may at first appear because of the timing that would
be required, i.e., “How does the PC know when to activate each pusher?” Much
more complicated operations are also possible.

To achieve proper control, CV-series PCs use a form of PC logic called ladder­diagram programming. A single ladder-diagram program can be used, as in C­series PCs, but CV-series PCs are also support sequential function chart, or
SFC, programming. SFC programming breaks the program into sections based
on processes, greatly reducing program development and maintenance times,
and allowing program sections to be easily used in other programs. The follow­ing diagram shows a simple SFC program, which consists of steps connected by
lines representing the flow of execution.

ST0000 01

TN0000

ST0001 02

000100

ST0011 02

000101

000200

ST0012 03

000201

ST0000

ST0020 00

000300

Initial step

Transition

Step

The transitions between the steps control when execution moves between the
steps and actions contained within the steps specify the actual executable ele­ments of the program. Programming the actions and transitions within SFC pro­gramming are generally achieved using ladder diagrams. There are also some
ladder diagram instructions that can be used to control the SFC program.

This manual is written to explain ladder-diagram programming and to prepare
the reader to program and operate the CV-series PCs. SFC programming is ex­plained in the

CV-series PCs Operation Manual: SFC

.

Overview Section 1-1

3

1-2 Relay Circuits: The Roots of PC Logic

PCs historically originate in relay-based control systems. And although the inte­grated circuits and internal logic of the PC have taken the place of the discrete
relays, timers, counters, and other such devices, actual PC operation proceeds
as if those discrete devices were still in place. PC control, however, also pro­vides computer capabilities and accuracy to achieve a great deal more flexibility
and reliability than is possible with relays.

The symbols and other control concepts used to describe PC operation also
come from relay-based control and form the basis of the ladder-diagram pro­gramming method. Most of the terms used to describe these symbols and con­cepts, however, have come in from computer terminology.

Relay vs. PC Terminology The terminology used throughout this manual is somewhat different from relay

terminology, but the concepts are the same.
The following table shows the relationship between relay terms and the PC

terms used for OMRON PCs.

Relay term PC equivalent

contact input or condition
coil output or work bit
NO relay normally open condition
NC relay normally closed condition

Actually there is not a total equivalence between these terms. The term condi­tion is only used to describe ladder diagram programs in general and is specifi­cally equivalent to one of a certain set of basic instructions. The terms input and
output are not used in programming per se, except in reference to I/O bits that
are assigned to input and output signals coming into and leaving the PC. Nor­mally open conditions and normally closed conditions are explained in

4-3 Basic

Ladder Diagrams

.

1-3 PC Terminology

Although also provided in the

Glossary

at the back of this manual, the following

terms are crucial to understanding PC operation and are thus introduced here.

PC Because CV-series PCs are Rack PCs, there is no single product that is a CV-

series PC. That is why we talk about the configuration of the PC, because a PC is
a configuration of smaller Units.

To have a functional PC, you would need to have a CPU Rack with at least one
Unit mounted to it that provides I/O points. When we refer to the PC, however, we
are generally talking about the CPU and all of the Units directly controlled by it
through the program. This does not include the I/O devices connected to PC in­puts and outputs. The term PC is also used to refer to the controlling element of
the PC, i.e., the CPU.

If you are not familiar with the terms used above to describe a PC, refer to

Sec-

tion 2 Hardware Considerations

for explanations.

Inputs and Outputs A device connected to the PC that sends a signal to the PC is called an input

device; the signal it sends is called an input signal. A signal enters the PC
through terminals or through pins on a connector on a Unit. The place where a
signal enters the PC is called an input point. This input point is allocated a loca­tion in memory that reflects its status, i.e., either ON or OFF. This memory loca­tion is called an input bit. The CPU, in its normal processing cycle, monitors the
status of all input points and turns ON or OFF corresponding input bits accord­ingly.

There are also output bits in memory that are allocated to output points on Units
through which output signals are sent to output devices, i.e., an output bit is

PC Terminology Section 1-3

4

turned ON t o send a signal to an output device through an output point. The CPU
periodically turns output points ON or OFF according to the status of the output
bits.

These terms are used when describing different aspects of PC operation. When
programming, one is concerned with what information is held in memory , and so
I/O bits are referred to. When talking about the Units that connect the PC to the
controlled system and the places on these Units where signals enter and leave
the PC, I/O points are referred to. When wiring these I/O points, the physical
counterparts of the I/O points, either terminals or connector pins, are referred to.
When talking about the signals that enter or leave the PC, one refers to input
signals and output signals, or sometimes just inputs and outputs. It all depends
on what aspect of PC operation is being talked about.

The Control System includes the PC and all I/O devices it uses to control an ex­ternal system. A sensor that provides information to achieve control is an input
device that is clearly part of the Control System. The controlled system is the
external system that is being controlled by the PC program through these I/O
devices. I/O devices can sometimes be considered part of the controlled sys­tem, e.g., a motor used to drive a conveyor belt.

1-4 OMRON Product Terminology

OMRON products are divided into several functional groups that have generic
names.

Appendix A Standard Models

lists products according to these groups.
The term Unit is used to refer to all of the OMRON PC products. Although a Unit
is any one of the building blocks that goes together to form a CV-series PC, its
meaning is generally, but not always, limited in context to refer to the Units that
are mounted to a Rack. Most, but not all, of these products have names that end
with the word Unit.

The largest group of OMRON products is the I/O Units. These include all of the
Rack-mounting Units that provide non-dedicated input or output points for gen­eral use. I/O Units come with a variety of point connections and specifications.

Special I/O Units are dedicated Units that are designed to meet specific needs.
These include Position Control Units, High-speed Counter Units, and Analog I/O
Units. This group also includes some programmable Units, such as the ASCII
Unit, which is programmed in BASIC.

CPU Bus Units connect to the CPU bus and must be mounted on either the
CPU Rack or a Expansion CPU Rack. These include the SYSMAC NET Link
Unit, SYSMAC LINK Unit, SYSMAC BUS/2 Remote I/O Master Unit, and BASIC
Unit.

Link Units are used to create communications links between PCs or between
PCs and other devices. Link Units include SYSMAC NET Link Unit, SYSMAC
LINK Unit, and, sometimes, SYSMAC BUS/2 Remote I/O Master Unit.

Other product groups include Programming Devices, Peripheral Devices,
and DIN Track Products.

1-5 Overview of PC Operation

The following are the basic steps involved in programming and operating a CV­series PC. Assuming you have already purchased one or more of these PCs,
you must have a reasonable idea of the required information for steps one and
two, which are discussed briefly below. The relevant sections of this manual that
provide more information are listed with relevant steps.

1, 2, 3...

1. Determine what the controlled system must do, in what order, and at what
times.

2. Determine what Racks and what Units will be required. Refer to the

CV-se-

ries PCs Installation Guide

. If a Link System is required, refer to the ap-

propriate

System Manual

.

Controlled System and
Control System

Overview of PC Operation Section 1-5

5

3. On paper , assign all input and output devices to I/O points on Units and de­termine which I/O bits will be allocated to each. If the PC includes Special I/O
Units, CPU Bus Units, or Link Systems, refer to the individual

Operation

Manuals

or

System Manuals

for details on I/O bit allocation. (

Section 3

Memory Areas

)

4. Divide the required control actions into processes that need to be treated as
individual sections and create an SFC program to control the flow of execu­tion of the processes. Refer to the

CV-series PCs Operation Manual: SFC

for details on the SFC program. If desired, you can also program the PC
without using an SFC program by setting the PC for ladder-only operation
from the CVSS/SSS.

5. Using relay ladder symbols, write a program that represents the sequence
of required operations within each process and their inter-relationships. If
you are using an SFC program, you will actually be writing transition pro­grams and action programs within the SFC program. Be sure to also pro­gram appropriate responses for all possible emergency situations. (

Section
4 Writing Programs, Section 5 Instruction Set, Section 6 Program Execution
Timing

)

6. Write the program in the CVSS/SSS offline, and then switch to online opera­tion and transfer the program to Program Memory in the CPU. The program
can also be written or altered online. Refer to the

CVSS/SSS Operation

Manual

for details.

7. Generate the I/O table with I/O Units installed. The I/O table can be gener­ated either online from the CVSS/SSS, or edited offline and then trans­ferred. Always turn the PC off and on after transferring the I/O table. The PC
will not run until the I/O table has been registered. Refer to the

CVSS/SSS

Operation Manual

for details.

8. The PC Setup controls a variety of basic options in PC operation (such as
the method of I/O refreshing and PC mode at start-up). The operating pa­rameters in the PC Setup can be left in their default settings or changed with
the CVSS/SSS as required. Refer to

Section 7 PC Setup

for details.

9. Debug the program, first to eliminate any syntax errors, and then to find
execution errors. Refer to the three CVSS/SSS operation manuals for de­tails on debugging operations. (

Section 8 Error Processing

)

10. Wire the PC to the controlled system. This step can actually be started as
soon as step 3 has been completed. Refer to the

CV-series PCs Installation

Guide

and to other

Operation Manuals

and

System Manuals

for details on

individual Units.

11. Test the program in an actual control situation and carry out fine tuning as
required. Refer to the CVSS/SSS operation manuals for details on debug­ging operations. (

Section 8 Error Processing

)

12. Record two copies of the finished program on masters and store them safely
in different locations. Refer to the CVSS/SSS operation manuals for details.

Note 1. The date and time are not set when the CPU is shipped. Set the date and

time by the procedure described in the

CVSS/SSS Operation Manuals

.

2. There is an error log in the PC. This log can be cleared by turning ON the
Error Log Reset Bit (A00014).

Control System Design Designing the Control System is the first step in automating any process. A PC

can be programmed and operated only after the overall Control System is fully
understood. Designing the Control System requires, first of all, a thorough un­derstanding of the system that is to be controlled. The first step in designing a
Control System is thus determining the requirements of the controlled system.

Overview of PC Operation Section 1-5

6

Input/Output Requirements The first thing that must be assessed is the number of input and output points

that the controlled system will require. This is done by identifying each device
that is to send an input signal to the PC or which is to receive an output signal
from the PC. Keep in mind that the number of I/O points available depends on
the configuration of the PC.

Next, determine the sequence in which control operations are to occur and the
relative timing of the operations. Identify the physical relationships between the
I/O devices as well as the kinds of responses that should occur between them.

For instance, a photoelectric switch might be functionally tied to a motor by way
of a counter within the PC. When the PC receives an input from a start switch, it
could start the motor. The PC could then stop the motor when the counter has
received a specified number of input signals from the photoelectric switch.

Each of the related tasks must be similarly determined, from the beginning of the
control operation to the end.

Unit Requirements The actual Units that will be mounted or connected to PC Racks must be deter-

mined according to the requirements of the I/O devices. Actual hardware specifi­cations, such as voltage and current levels, as well as functional considerations,
such as those that require Special I/O Units, CPU Bus Units, or Link Systems will
need to be considered. In many cases, Special I/O Units, CPU Bus Units or Link
Systems can greatly reduce the programming burden. Details on these Units
and Link Systems are available in appropriate

Operation Manuals

and

System

Manuals

.

Once the entire Control System has been designed, the task of programming,
debugging, and operation as described in the remaining sections of this manual
can begin.

1-6 PC Operating Modes

CV-series PCs have four operation modes: PROGRAM, DEBUG, MONITOR,
and RUN. The Unit will automatically enter the mode specified in the PC Setup
(default setting: PROGRAM mode). Refer to

Section 7 PC Setup

for details. The
PC mode can be changed from a Peripheral Device. The function of each mode
is described briefly below.

PROGRAM mode is used when making basic changes to the PC program or set­tings, such as transferring, writing, changing, or checking the program, generat­ing or changing the I/O table, or changing the PC Setup. The program cannot be
executed in PROGRAM mode. Output points at Output Units will remain OFF,
even when the corresponding output bit is ON.

DEBUG mode is used to check program execution and I/O operation after syn­tax errors in the program have been corrected. With SFC programs, a single
step can be checked for errors from a Peripheral Device using the DEBUG op­eration. Output points at Output Units will remain OFF, even when the corre­sponding output bit is ON.

MONITOR mode is used when monitoring program execution, such as making a
trial run of a program. The program is executed just as it is in RUN mode, but bit
status, timer and counter SV/PV, and the data content of most words can be
changed online. PC operation in MONITOR mode is significantly slower than it is
in RUN mode. Output points at Output Units will be turned ON when the corre­sponding output bit is ON.

RUN mode is used when operating the PC in normal control conditions. Bit sta­tus cannot be Force Set or Reset, and SVs, PVs, and the data cannot be
changed online. Output points at Output Units will be turned ON when the corre­sponding output bit is ON.

Sequence, Timing, and
Relationships

PROGRAM Mode

DEBUG Mode

MONITOR Mode

RUN Mode

PC Operating Modes Section 1-6

7

1-7 Peripheral Devices

The CV Support Software (CVSS) and the SYSMAC Support Software (SSS)
are the main Peripheral Device used to program and monitor CV-series PCs.
Y ou must have the CVSS/SSS to program and operate these PCs. The following
Peripheral Devices are available for basic programming/monitoring.

Note The CVSS does not support new instructions added for version-2 CVM1 PCs.

The SSS does not support SFC programming (CV500, CV1000, and CV2000).
New instructions added for version-2 CVM1 PCs are also supported by ver­sion-1 CV-series Programming Consoles.

The Graphics Programming Console (GPC) can be used for monitoring and pro­gramming of PCs, but does not support SFC programming.

Programming Console The Programming Console can be used for onsite monitoring and programming

of PC, but does not support SFC programming and other advanced program­ming/debugging operations.

Graphic Programming
Console

Peripheral Devices Section 1-7

8

1-8 CV-series Manuals

The following manuals are available for CV-series products. Manuals are also
available for compatible C-series products (see next section). Catalog number
suffixes have been omitted; be sure you have the current version for your region.

Product Manual Cat. No.

CV-series PCs CV-series PCs Installation Guide W195

CV-series PCs Operation Manual: SFC W194
CV-series PCs Operation Manual: Ladder Diagrams W202
CV-series PCs Operation Manual: Host Link System,

CV500-LK201 Host Link Unit

W205

CV Support Software (CVSS)

The CV Series Getting Started Guidebook W203

()

CV Support Software Operation Manual: Basics W196
CV Support Software Operation Manual: Offline W201
CV Support Software Operation Manual: Online W200

SYSMAC Support Software Operation
Manual: Basics

SSS installation procedures, hardware information for the SSS, and
general basic operating procedures (including data conversion
between C-series and CVM1 PCs).

W247

SYSMAC Support Software Operation
Manual: C-series PC Operations

Detailed operating procedures for the C-series PCs. W248

SYSMAC Support Software Operation
Manual: CVM1 Operations

Detailed operating procedures for CVM1 PCs. W249

Graphic Programming Console (GPC) CV500-MP311-E Graphic Programming Console Operation Manual W216
Programming Console CVM1-PRS21-E Programming Console Operation Manual W222
SYSMAC NET Link System SYSMAC NET Link System Manual W213
SYSMAC LINK System SYSMAC LINK System Manual W212
SYSMAC BUS/2 Remote I/O System SYSMAC BUS/2 Remote I/O System Manual W204
CompoBus/D Device Network CompoBus/D (DeviceNet) Operation Manual) W267
CV-series Ethernet Unit CV-series Ethernet System Manual W242
BASIC Unit BASIC Unit Reference Manual W207

BASIC Unit Operation Manual W206

Personal Computer Unit

Personal Computer Unit Operation Manual W251
Personal Computer Unit Technical Manual W252

Motion Control Unit

Motion Control Unit Operation Manual: Introduction W254
Motion Control Unit Operation Manual: Details W255

Temperature Controller Data Link Unit CV500-TDL21 Temperature Controller Data Link Unit Operation

Manual

W244

Memory Card Writer CV500-MCW01-E Memory Card Writer Operation Manual W214
Optical Fiber Cable Optical Fiber Cable Installation Guide W156

CV-series Manuals Section 1-8

9

1-9 C-series–CV-series System Compatibility

The following table shows when C-series Units can be used and when CV-series
Units must be used. Any C-series Unit or Peripheral Device not listed in this table
cannot be used with the CV-series PCs.

Unit C Series CV Series Remarks

CPU Rack CPU No Yes CV500-CPU01-EV1, CV1000-CPU01-EV1,

CV2000-CPU01-EV1, CVM1-CPU01-EV2,
CVM1-CPU11-EV2, and CVM1-CPU21-EV2

Power Supply No Yes CV500-PS221, CV500-PS211, and

CVM1-PA208

CPU Backplane No Yes CV500-BC031, CV500-BC051, CV500-BC101,

CVM1-BC103, and CVM1-BC053

I/O Control Unit No Yes

CV500-IC01
Expansion CPU Backplane No Yes CV500-BI111
Expansion I/O Backplane No Yes CV500-BI042, CV500-BI062, CV500-BI112,

CVM1-BI114, and CVM1-BI064 (C500

Expansion I/O Racks can be used with certain

limitations.)
16-/32-/64-point I/O Units Yes Yes --­Special I/O Units Yes Yes Applicable Units include Analog Input, Analog

Output, High-speed Counter, PID, Position

Control, Magnetic Card, ASCII, ID Sensor, and

Ladder Program I/O Units (The C500-ASC03

cannot be used.)
BASIC Unit No Yes

CV500-BSC1
Personal Computer Unit No Yes CV500-VP213-E/217-E/223-E/227-E
Temperature Control Data Link Unit No Yes CV500-TDL21
Link

SYSMAC NET No Yes CV500-SNT31

Systems

SYSMAC LINK No Yes CV500-SLK11 and CV500-SLK21
Host Link Unit No Yes CV500-LK201
Ethernet Unit No Yes CV500-ETN01

Remote I/O

SYSMAC BUS Units Yes Yes ---

Systems

SYSMAC BUS/2 No Yes CV500-RM211/221 and CV500-RT211/221

Peripheral
Devices

CV Support Software No Yes

(See note.)

CV500-ZS3AT1-EV2 (3 1/2” floppy disks) and

CV500-ZS5AT1-EV2 (5 1/4” floppy disks) for

IBM PC/AT compatible

SYSMAC Support
Software (SSS)

Yes Yes

(See note.)

C500-ZL3AT1-E (3.5” floppy disks) for IBM

PC/AT compatible

Graphic Programming
Console

Yes (Main
unit only)

Yes
(System
Cassette)

(See note.)

GPC: 3G2C5-GPC03-E

System Cassette: CV500-MP311-E

Programming Console No Yes

(See note.)

CVM1-PRS21-EV1 (set)

Note The CVSS does not support new instructions added for version-2 CVM1 PCs.

The SSS does not support SFC programming (CV500, CV1000, and CV2000).
New instructions added for version-2 CVM1 PCs are also supported by ver­sion-1 CV-series Programming Consoles.

C-series – CV-series System Compatibility Section 1-9

10

1-10 Networks and Remote I/O Systems

Systems that can be used to create networks and enable remote I/O are
introduced in this section. Refer to the operation manuals for the Systems for
details.

The SYSMAC NET Link System is a LAN (local area network) for use in factory
automation systems. The SYSMAC NET Link System can consist of up to 128
nodes among which communications may be accomplished via datagrams,
data transfers, or automatic data links.

Datagrams transmit and receive data using a command/response format. Com­mands can be issued from the user program by the DELIVER COMMAND
instruction (CMND(194)).

Data can also be transmitted and received using the NETWORK SEND and
NETWORK RECEIVE (SEND(192)/RECV(193)) instructions in the user pro­gram. Up to 256 words of data can be transferred for each instruction.

Automatic data links allow PCs and computers to create common data areas.

SYSMAC NET Link Unit
CV500-SNT31

Up to 4 Units can
be mounted.

CV-series
CPU Rack/Expansion CPU Rack

Line Server

Center Power
Feeder

C200H
C500
C1000H
C2000H

Personal
computer

Note Up to four SYSMAC NET Link Units (CV500-SNT31) can be mounted to the

CPU Rack and/or Expansion CPU Rack of each CV-series PC.

SYSMAC NET Link System

Networks and Remote I/O Systems Section 1-10

11

SYSMAC LINK System Networks can also be created using SYSMAC LINK Systems. A SYSMAC LINK

System can consist of up to 62 PCs, including the CV500, CV1000, CV2000,
CVM1, C200H, C1000H, and C2000H. Communications between the PCs is ac­complished via datagrams, data transfers, or automatic data links in ways simi­lar to the SYSMAC NET Link System.

The main differences between SYSMAC NET Link and SYSMAC LINK Systems
is in the structure of automatic data links and in the system configuration, e.g.,
only PCs can be linked in SYSMAC LINK Systems, whereas other devices can
form nodes in SYSMAC NET Link Systems.

Datagrams transmit and receive data using a command/response format. Com­mands can be issued from the user program by the DELIVER COMMAND
instruction (CMND(194)).

Data can also be transmitted and received using the NETWORK SEND and
NETWORK RECEIVE (SEND(192)/RECV(193)) instructions in the user pro­gram. Up to 256 words of data can be transferred for each instruction.

Automatic data links allow PCs and computers to create common data areas.

SYSMAC LINK Unit
CV500-SLK11 (optical)
CV500-SLK21 (wired)

Up to 4 Units can
be mounted.

CV-series
CPU Rack/Expansion CPU Rack

CV500/CV1000/
CV2000/CVM1
C200H/C1000H/
C2000H

Note Up to four SYSMAC LINK Units (CV500-SLK11/21) can be mounted to the CPU

Rack and/or Expansion CPU Rack of each CV-series PC.

Networks and Remote I/O Systems Section 1-10

12

Remote I/O can be enabled by adding a SYSMAC BUS/2 Remote I/O System to
the PC. The SYSMAC BUS/2 Remote I/O System is available in two types: opti­cal and wired.

Two Remote I/O Master Units, optical or wired, can be mounted to the CV500 or
CVM1-CPU01-EV2 CPU Rack or Expansion CPU Rack. Four Remote I/O Mas­ter Units can be mounted to the CV1000, CV2000, CVM1-CPU11-EV2, or
CVM1-CPU21-EV2 CPU Rack or Expansion CPU Rack.

Up to eight Remote I/O Slave Racks can be connected per PC.
Slaves can be used to provide up to 1,024 remote I/O points for the CV500 or

CVM1-CPU01-EV2, and up to 2,048 remote I/O points for the CV1000, CV2000,
CVM1-CPU11-EV2, or CVM1-CPU21-EV2.

A Programming Device (such as the CVSS/SSS) can be connected to up to two
Remote I/O Slave Units for each Remote I/O Master Unit as long as a total of no
more than four Programming Devices are connected per PC.

Remote I/O Master Unit
CV500-RM211 (optical)
CV500-RM221 (wired)

CV500, CVM1-CPU01-EV2: 2 Masters max. can be mounted
CV1000, CV2000, CVM1-CPU11-EV2, CVM1-CPU21-EV2:
4 Masters max. can be mounted

CV-series
CPU Rack/Expansion CPU Rack

Remote I/O Slave
Up to 8 Slave can be con­nected per PC for 58M
Slaves; 4 Slaves for 122M
or 54MH Slaves.

Remote I/O Slave Unit
CV500-RT211 (optical)
CV500-RT221 (wired)

SYSMAC BUS/2 Remote I/O
System

Networks and Remote I/O Systems Section 1-10

13

Remote I/O can also be enabled by using the C-series SYSMAC BUS Remote
I/O System with CV-series PC.

Remote I/O Master Units can be mounted on any slot of the CPU Rack, Expan­sion CPU Rack, or Expansion I/O Rack. Up to four Masters can be mounted for
the CV500 or CVM1-CPU01-EV2, up to eight Masters for the CV1000, CV2000,
CVM1-CPU11-EV2, or CVM1-CPU21-EV2.

For each Master, up to two Slave Racks can be connected for the CV500 or
CVM1-CPU01-EV2; up to eight Slave Racks for the CV1000, CV2000,
CVM1-CPU11-EV2, or CVM1-CPU21-EV2. No more than 16 Slave Racks can
be connected per PC.

Slaves can be used to provide up to 512 remote I/O points for the CV500 or
CVM1-CPU01-EV2; up to 1,024 remote I/O points for the CV1000, CV2000, or
CVM1-CPU11-EV2, and up to 2,048 remote I/O points for the
CVM1-CPU21-EV2.

Programming Devices cannot be connected to SYSMAC BUS Slave Racks.
When a C200H 10-slot Backplane is used is used as a SYSMAC BUS Slave

Rack, only the eight leftmost slots can be used.

Remote I/O Master Unit
3G2A5-RM001-(P)EV1 (optical)
C500-RM201 (wired)

Up to 8 Units

CV-series
CPU Rack/Expansion CPU
Rack/Expansion I/O Rack

C-series
Remote I/O Slave Rack

SYSMAC BUS Remote I/O
System

Networks and Remote I/O Systems Section 1-10

14

The CV -series PCs can be connected to a host computer with the host link con­nector via the CPU or a CV500-LK201 Host Link Unit mounted to a Rack.

RS-232C or RS-422 communications can be used depending on the switch set­ting. When RS-422 is selected, up to 32 PCs can be connected to a single host.

Data is transmitted and received by commands and responses.

Host link connector

Host
computer

BASIC Unit The BASIC Unit can be connected to a personal computer to enable commu-

nications with the PC using the BASIC programming language. Up to 512 bytes
(256 words) of data can be transferred between the BASIC Unit and the CPU by
the PC READ/WRITE command without using the PC program.

Up to 256 words of data can also be transferred between the BASIC Unit and the
PC’s CPU by using the NETWORK SEND and NETWORK RECEIVE
(SEND(192)/RECV(193)) instructions in the PC program.

Host Link System
(SYSMAC WAY)

Networks and Remote I/O Systems Section 1-10

15

Data can also be transferred to other BASIC Units mounted on the same PC, or
to BASIC Units mounted to other PCs connected by networks formed using a
SYSMAC NET Link or SYSMAC LINK System. RS-232C, RS-422, Centronics,
and GPIB interfaces are available.

BASIC Unit
CV500-BSC1

Personal com­puter

CV-series
CPU Rack/Expansion
CPU Rack

Personal Computer Unit The Personal Computer Unit is a full-fledged IBM PC/AT compatible that can be

used to run independent programming directly on a Rack to eliminate the need
for separate installation space. It can run along or connected to any of the normal
peripherals supported by IBM PC/AT compatibles (mice, keyboards, monitors,
data storage devices, etc.), and as a CPU Bus Unit, the Personal Computer Unit
interfaces directly to the PC’s CPU though the CPU bus to eliminate the need for
special interface hardware, protocols, or programming.

1-11 New CPUs and Related Units

The following new CV-series CPUs and related Units are included in this version
of the manual for the first time. Refer to relevant sections of this manual or the

CV-series PC Operation Manual: Ladder Diagrams

for further details.

Unit Model number Main specifications

CPU

CVM1-CPU01-EV2 I/O capacity: 512 pts; Ladder diagrams only
CVM1-CPU11-EV2 I/O capacity: 1,024 pts; Ladder diagrams only
CVM1-CPU21-EV2 I/O capacity: 2,048 pts; Ladder diagrams only
CV500-CPU01-EV1 I/O capacity: 512 pts; Ladder diagrams or SFC + ladder diagrams
CV1000-CPU01-EV1 I/O capacity: 1,024 pts; Ladder diagrams or SFC + ladder diagrams
CV2000-CPU01-EV1 I/O capacity: 2,048 pts; Ladder diagrams or SFC + ladder diagrams

Temperature Controller
Data Link Unit

CV500-TDL21 Connects up to 64 temperature controllers via 2 ports.

New CPUs and Related Units Section 1-11

16

1-12 CPU Comparison

The following table shows differences between the various CV-series CPUs.

CPU

CVM1-

CPU01-EV2

CVM1-

CPU11-EV2

CVM1-

CPU21-EV2

CV500-

CPU01-EV1

CV1000-

CPU01-EV1

CV2000-

CPU01-EV1

Ladder diagrams Supported Supported Supported Supported Supported Supported

Program-

SFC Not supported Not supported Not supported Supported Supported Supported

ming

Instructions 284 284 285 169 170 170

Speed

Basic
instructions (ms)

0.15 to 0.45 0.125 to 0.375 0.125 to 0.375 0.15 to 0.45 0.125 to 0.375 0.125 to 0.375

Other
instructions (ms)

0.6 to 9.9 0.5 to 8.25 0.5 to 8.25 0.6 to 9.9 0.5 to 8.25 0.5 to 8.25

Program capacity 30K words 30K words 62K words 30K words 62K words 62K words
Local I/O capacity 512 pts 1,024 pts 2,048 pts 512 pts 1,024 pts 2,048 pts
Remote

SYSMAC BUS/2 1,024 pts 2,048 pts 2,048 pts 1,024 pts 2,048 pts 2,048 pts

I/O
capacity

SYSMAC BUS 512 pts 1,024 pts 2,048 pts 512 pts 1,024 pts 1,024 pts

DM Area 8K words 24K words 24K words 8K words 24K words 24K words

Expansion DM Area Not supported Not supported

32K words
each for 8
banks

Not supported

32K words
each for 8
banks

32K words
each for 8
banks

Timers 512 1,024 1,024 512 1,024 1,024
Counters 512 1,024 1,024 512 1,024 1,024
SFC steps None None None 512 1,024 1,024
Step Flags None None None 512 1,024 1,024
Transition Flags None None None 512 1,024 1,024

1-13 Improved Specifications

1-13-1Upgraded Specifications

The following improvements were made December 1992 and are applicable to
all CV500-CPU01-E and CV1000-CPU01-E CPUs with lot numbers in which the
rightmost digit is 3 (3) or higher.

1, 2, 3...

1. The MLPX(110) (4-TO-16 DECODER) instruction has been improved to
also function as a 8-to-256 decoder and the DMPX(111) (16-TO-4 ENCOD­ER) instruction has been improved to also function as a 256-to-8 encoder.
To enable this improvement, the digit designator (Di) has been changed as
shown below. Refer to

5-17-8 DATA DECODER – MLPX(110)

and

5-17-9

DATA ENCODER – DMPX(111)

for details on these instructions.

Specifies the first digit to be converted
4-to-16/16-to-4: 0 to 3
8-to-256/256-to-8: 0 or 1

Number of digits to be converted
4-to-16/16-to-4: 0 to 3 (1 to 4 digits)
8-to-256/256-to-8: 0 or 1 (1 or 2 digits)

Process
0: 4-to-16/16-to-4
1: 8-to-256/256-to-8

Digit number: 3210

0

2. The following operating parameter has been added to the PC Setup. Refer
to

Section 7 PC Setup

for details on the PC Setup.

JMP(004) 0000 Processing
Y: Enable multiple usage (default)
N: Disable multiple usage

Improved Specifications Section 1-13

17

3. The operation of Completion Flags for timers has been changed so that the
Completion Flag for a timer turns ON only when the timer instruction is
executed with a PV of 0000 and not when the timer’s PV is refreshed to a PV
value of 0000, as was previously done.

Only the timing of the activation of the Completion Flag has been changed,
and the timer’s PV is still refreshed at the same times (i.e., when the timer
instruction is executed, at the end of user program execution, and every
80 ms if the cycle time exceeds 80 ms).

Refer to

5-3 Data Areas, Definers, and Flags

for details on timer and counter

instructions.

4. The READ(190) (I/O READ) and WRIT(191) (I/O WRITE) instructions have
been improved so that they can be used for Special I/O Units on Slave
Racks under the following conditions.

a) The lot number of the Remote I/O Master Unit and Remote I/O Slave Unit

must be the same as or latter than the following.

1992
October (Y: November; Z: December)
1st

01 X 2

b) The DIP switch on the Remote I/O Slave Unit must be set to “54MH.”
c) The Special I/O Unit must be one of the following: AD101, CT012,

CT021, CT041, ASC04, IDS01-V1, IDS02, IDS21, IDS22, or LDP01-V1.
(The NC221-E, NC222, CP131, and FZ001 cannot be mounted to Slave
Racks.)

Refer to

5-35-1 I/O READ – READ(190)

and

5-35-3 I/O WRITE – WRIT(191)

for details on these instructions.

1-13-2Version-1 CPUs

CV-series CPUs were changed to version 1 from December 1993. The new
model numbers are as follows: CVM1-CPU01-EV1, CVM1-CPU11-EV1,
CV500-CPU-EV1, CV1000-CPU-EV1, and CV2000-CPU-EV1. (Of these, all
CVM1 CPUs were changed to version 2 from December 1994; refer to the next
sections for details.)

The following additions and improvements were made to create the version-1
CPUs.

PT Link Function The host link interface on the CPU can be used to connect directly to Program-

mable Terminals (PTs) to create high-speed data links. T o use the PT links, turn
ON pin 3 of the DIP switch on the CPU. Pin 3 must be turned OFF for host link
connections.

EEPROM Writes With the new CPUs, you can write to EEPROM Memory Cards mounted to the

CPU by using the file write operation from a Peripheral Device. A Memory Card
Writer is no longer required for this write operation. Writing is possible in PRO­GRAM mode only.

New Command A new I/O REGISTER command (QQ) has been added so that words from differ-

ent data areas can be read at the same time.

Faster Host Links The communications response time for the built-in host link interface on the CPU

has been improved by a factor of approximately 1.2.

Faster Searches The search speed from Peripheral Devices for instructions and operands has

been nearly doubled.

Improved Specifications Section 1-13

18

1-13-3Version-2 CVM1 CPUs

CVM1 CPUs were changed to version 2 and a new CPU was added from De­cember 1994. The new model numbers are as follows: CVM1-CPU01-EV2,
CVM1-CPU11-EV2, and CVM1-CPU21-EV2.

The following additions and improvements were made to create the version-2
CPUs.

CMP/CMPL New versions of the CMP(020) and CMPL(021) have been added that are not

intermediate instructions. The new instructions are CMP(028) and CMPL(029)
and are programs as right-hand (final) instructions. A total of 24 other new com­parison instructions have also been added with symbol mnemonics (e.g., >, +,
and <).

XFER(040) This instruction has been upgraded so that source and destination areas can

overlap.

DMPX(111) This instruction has been upgraded so that either the MSB or the LSB can be

specified for use as the end code. Previously only the the MSB could be used.

New Flags Underflow and Overflow Flags have been added at A50009 and A50010, re-

spectively. These flags can be turned ON or OFF when executing ADB, ADBL,
SBB, and SBBL and can be saved or loaded using CCL and CCS.

New Instructions A total of 125 new instructions have been added. These instructions are sup-

ported by version-2 CPUs only.

Faster Online Editing The time that operation is stopped for online editing has been reduced and is no

longer added to the cycle time. The following are just a couple of examples.

Edit Time operation is stopped

Adding or deleting one instruction block at the
beginning of a 62K-word program

Approx. 0.5 s

Deleting an instruction block containing JME
from the beginning of a 62K-word program

Approx. 2.0 s

The above speed increase also applies to all V1 CPUs with lot numbers in which
the rightmost digit is 5 (5) or higher.

New Host Link Commands New C-mode commands have been added and the functionality of existing com-

mands has been improved as follows:

New Commands

• RL/WL: Read and write commands for the CIO Area.

• RH/WH: Read and write commands for the CIO Area.

• CR: Read command for the DM Area.

• R#/R$/R%: SV read commands.

• W#/W$/W%: SV change commands.

• *: Initialization command.

Improved Commands

• The Link Area (CIO 1000 to CIO 1063) and Holding Area (CIO 1200 to
CIO 1299) can now be specified for the KS, KR, KC, and QQ commands.

• CVM1-CPU21-EV1 can now be read for the MM command.

The above new and improved commands can also be used with all V1 CPUs
with lot numbers in which the rightmost digit is 5 (5) or higher.

Note Only the following Programming Devices support version-2 CPUs: SSS

(C500-ZL3AT-E) and the CVM1-PRS21-V1 Programming Console
(CVM1-MP201-V1). Of these, the SSS does not support SFC and thus cannot
be used for the CV500, CV1000, and CV2000. Use the CVSS for these PCs.

Improved Specifications Section 1-13

19

1-13-4Upgraded Specifications

The following improvements were made December 1995 and are applicable to
all CV500/CV1000/CV2000-CPU01-EV1 and CVM1-CPU01/CPU11/CPU21-EV2
CPUs with lot numbers in which the rightmost digit is 6 (6) or higher.

Simplified Backup Function Added

Specifications have been changed so that the user program, Extended PC Set­up, and IOM/DM data can be backed up from memory in the CPU Unit to a
Memory Card without using a Programming Device, and so that the data backed
up in the Memory Card can be transferred back to memory in the CPU Unit with­out using a Programming Device. (This method is provided as an easy way to
backup and restore data. We still recommend that a Programming Device be
used to confirm all essential backup and restore operations.)

Use the following procedure to prepare to backup data in the memory of the CPU
Unit to a Memory Card.

1, 2, 3...

1. Insert a Memory Card that is not write-protected and check to be sure the
available capacity is sufficient for the files that will be created.

2. Confirm that the Memory Card is not being accessed by file memory opera­tions or from a Programming Device.

3. Turn OFF pin 5 on the DIP switch on the CPU Unit.

Use the following procedure to prepare to transfer data on the Memory Card to
the memory of the CPU Unit.

1, 2, 3...

1. Insert the Memory Card and be sure that it contains the desired files.

2. Check the file checksums and sizes to be sure that they are correct.

3. Confirm that the CPU Unit is in PROGRAM mode.

4. Confirm that the Memory Card is not being accessed from a Programming
Device.

5. Turn ON pin 5 on the DIP switch on the CPU Unit.

Pins 1 and 2 on the DIP switch are used to specify the files to be transferred.
These pins are normally used to specify the baud rate for a Programming De­vice, so be sure to return them to their original settings when you finish backing
up or restoring data. Set pins 1 and 2 as shown in the following table.

Pin 1 Pin2 User program Extended PC Setup IOM/DM

OFF OFF Transferred. Transferred. Transferred.
OFF ON Transferred. Not transferred. Not transferred.
ON OFF Not transferred. Transferred. Not transferred.
ON ON Not transferred. Not transferred. Transferred.
File name

(See note.)

BACKUP.OBJ BACKUP.STD IOM: BACKUP.IOM

DM: BACKUPDM.IOM
EM: BACKUPE*.IOM
(* = bank number)

Note Any files of the same name will be automatically overwritten when backing up to

Memory Card.
Data transfers are started by pressing the Memory Card power switch for 3 se-

conds. If the transfer ends normally, the Memory Card indicator will flash once
and will then go out when the transfer has completed. The time required will de­pend on the about of data being transferred. If there is insufficient memory avail­able on the Memory Card to back up the specified data or if the specified files are
not present on the Memory Card when restoring data, the Memory Card indica­tor will flash 5 times and then go out.

Note Approximately 17 s will be required to backup all data except the EM files for the

CV1000 using a 1-Mbyte Memory Card. Approximately 2 s will be required to
restore the same data to the CPU Unit’s memory.

Backing Up Data to a
Memory Card

Transferring Data Back to
CPU Unit Memory

Specifying Files

Starting and Confirming
Data Transfers

Improved Specifications Section 1-13

20

Application of Commercial Memory Cards

The following commercially available memory cards can be used. The proce­dures and applications for using these memory cards is exactly the same as for
the Memory Cards provided by OMRON.

• RAM Memory Cards conforming to JEIDA4.0 and of the following sizes:
64 Kbytes, 128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbyte, and 2 Mbytes.

Note The 2-Mbyte Memory Cards cannot be used in the CV500-MCW01 Memory

Card Writer.

Improved Specifications Section 1-13

21

SECTION 2

Hardware Considerations

This section provides information on hardware aspects of CV-series PCs that are relevant to programming and software op­eration. These include indicators on the CPU and basic PC configuration. This information is covered in more detail in the
CV-series PC Installation Guide.

2-1 CPU Components 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1-1 Indicators 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1-2 Switches 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2 Program Memory 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3 Memory Cards 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3-1 Mounting and Removing Memory Cards 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3-2 File Transfer between the CPU and Memory Card 26. . . . . . . . . . . . . . . . . . . . . . .

2-4 Data Memory and Expansion Data Memory Unit 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-5 I/O Control Unit and I/O Interface Unit Displays 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-6 Peripheral Devices 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-7 PC Configuration 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22

2-1 CPU Components

The following diagram shows the basic components of the CPU that are used in
general operation of the PC.

Indicators

EM Card compartment

(CV1000, CV2000, or
CVM1-CPU21-EV2 only;
optional)

Memory Card (optional), DIP switch,
and battery compartment

Do not pull out the Memory Card while
the Memory Card indicator is lit. The
Memory Card power switch must be
ON for the Memory Card to operate.

Protect keyswitch

Used to write-protect the Pro­gram Memory (i.e., the Ex­tended PC Setup and the user
program).

Peripheral device connector

Host interface

RS-422/RS-232C selector

Memory Card indicator

Lit when power is supplied to
the Memory Card.

2-1-1 Indicators

CPU indicators provide visual information on the general operation of the PC.
Although not substitutes for proper error programming using the flags and other
error indicators provided in the data areas of memory, these indicators provide
ready confirmation of proper operation. CPU indicators are shown below and
are described in the following table. Indicators are the same for all CV-series
PCs.

Indicator Function

POWER (green) Lights when power is supplied to the CPU.
RUN (green) Lights when the CPU is operating normally.
ERROR (red) Lights when an error is discovered in diagnostic operations. When this indicator lights, the RUN

indicator will go off, CPU operation will be stopped, and all outputs from the PC will be turned OFF.

WDT (red) Lights when a CPU error (watchdog timer error) has been detected. When this indicator lights, the

RUN indicator will go off, CPU operation will be stopped, and all outputs from the PC will be turned

OFF.
ALARM (red) Lights when an error is discovered in diagnostic operations. PC operation will continue.
OUT INH (orange) Lights when the Output OFF Bit, A00015, is turned ON. All PC outputs will be turned OFF.
COMM (orange) Lights when the host link interface is transmitting or receiving data.
M/C ON (orange) Lights when power is supplied to the Memory Card. Press the Memory Card power switch once to

turn the power OFF or ON. Do not remove the Memory Card while the power is ON. It may flicker

when the simplified backup function operates. Refer to

1-13-4 Upgraded Specifications

for details.

CPU Components Section 2-1

23

2-1-2 Switches

The DIP switch and memory card power switch are shown below and the setting
of these and the other CPU switches are described in the following table.
Switches are the same for all CV-series PCs.

Switch Position Function

Protect keyswitch Vertical Program Memory (i.e., the Extended PC Setup

and the user program) is write-protected.
(See note 1)

Horizontal Program Memory is not write-protected.

RS-422/RS-232C
selector

Up Host link communications set for RS-232.

(Also see CPU DIP switch pins 4 and 6 below.)

Down Host link communications set for RS-422.

(Also see CPU DIP switch pins 4 and 6 below.)

Memory Card power
switch (See note 4.)

Not
applicable

Press and release to turn the power on or off.
(The M/C ON indicator lights when power is on.)

CPU DIP

Pins 1, 2

OFF, OFF Peripheral device communications: 50,000 bps

(See

ON, OFF Peripheral device communications: 19,200 bps

notes 3

and 4.)

OFF, ON Peripheral device communications: 9,600 bps
ON, ON Peripheral device communications: 4,800 bps

Pin 3

OFF Communicate via Host Link communications
ON Communicate with PT via NT Link communica-

tions.

Pin 4 OFF Host link communications governed by PC Set-

up. (See note 2)

ON Following settings used for host link communica-

tions, regardless of PC Setup: 9,600 bps, unit
number 00, even parity, 7-bit data, 2 stop bits.

Note: The above settings apply to CPUs
manufactured from July 1995 (lot number **75
for July 1995). For CPUs manufactured before
July 1995 (lot number **65 for June 1995), only
1 stop bit will be set and the baud rate will be
2,400 bps.

Pin 5
(See
note 4.)

OFF Files are not transferred from the Memory Card

automatically at start-up.

ON The program file (AUTOEXEC.OBJ) and PC

Setup file (AUTOEXEC.STD) will be transferred
from the Memory Card to the CPU automatically
at start-up.

Pin 6 OFF The termination resistance is off.

ON The termination resistance is on.

(This setting is used for the last Unit in a RS-422
Host Link System only; intermediate Units must
be set to OFF.)

Note 1. The user program can also be protected from a Peripheral Device.

2. Factory settings are 9,600 bps, 7-bit data, even parity, and 2 stop bits.

3. The baud rate must be set to 50,000 bps when the Graphic Programming
Console or Programming Console is connected to the PC, and to 9,600 bps
when a computer running the CV Support Software is connected.

4. The following switches and pins are also used for the simplified backup
function. Pins 1 and 2 are used to specify files, pin 5 is used to specify the
direction of the transfer, and the Memory Card power switch is used to start
data transfers. Refer to

1-13-4 Upgraded Specifications

for details.

CPU Components Section 2-1

OFF ON

123456ON

Memory Card
power switch

DIP switch

24

2-2 Program Memory

Program Memory is contained in the CPU and is divided into two areas, the PC
Setup and the Program Area. There are 32K words of Program Memory avail­able in the CV500, CVM1-CPU01-EV2, or CVM1-CPU11-EV2, and 64K words
available in the CV1000, CV2000, or CVM1-CPU21-EV2. The first 2K words in
both groups of PCs is taken up by the PC Setup, leaving 30K words in the
CV500, CVM1-CPU01-EV2, or CVM1-CPU11-EV2 Program Area, and 62K
words in the CV1000, CV2000, or CVM1-CPU21-EV2 Program Area. (One word
contains two bytes.)

Program Memory is backed up by the CPU battery, so data will not be lost during
a power interruption.

Note The program memory chip is built into CV-series PCs and does not need to be

installed by the user.
This area of Program Memory contains the settings described in

Section 7 PC

Setup

. Basic options in PC operation (such as the method of I/O refreshing and

the PC mode at start-up) are specified in these settings.
The PC Setup is stored in EEPROM, so this data will not be lost even if the back-

up battery power is interrupted.
This area of Program Memory contains the SFC and/or ladder program.

The following table shows the maximum program size (combined total of the
SFC and ladder programs) when SFC programming is used and the maximum
number of steps, transitions, and actions in the SFC program.

PC Program capacity SFC steps SFC transitions SFC actions

CV500 30K words 512 512 1,024
CV1000 62K words 1,024 1,024 2,048
CV2000 62K words 1,024 1,024 2,048
CVM1-CPU01/11-EV2 30K words

None (SFC programming is not supported.)

CVM1-CPU21-EV2 62K words

(gg )

Note When ladder programming is used, the program capacity includes 1.85K words

reserved for system use.

PC Setup

Program Area

Program Memory Section 2-2

!

25

2-3 Memory Cards

File memory (used to store programs and other data) is attached to the CPU in
the form of Memory Cards. The portable, high-capacity Cards allow large quan­tities of data to be handled by simply switching Memory Cards. Because
Memory Cards are not provided with the PC, they must be selected and installed
in the CPU. Three types of Memory Card are available: RAM, EPROM, and EE­PROM. Each of these comes in various capacities. Some of the memory is used
for file management and directories.

Memory type Total capacity File capacity Model No. Battery life

(See note 1)

RAM 64K bytes 61K bytes HMC-ES641 About 5 yrs

128K bytes 125K bytes HMC-ES151 About 3 yrs
256K bytes 251K bytes HMC-ES251 About 1 yr
512K bytes 506K bytes HMC-ES551 About 0.5 yrs

EEPROM

64K bytes 61K bytes HMC-EE641 Not applicable

(See note 2)

128K bytes 125K bytes HMC-EE151

EPROM

512K bytes 506K bytes HMC-EP551

(See note 2)

1 Mbyte 1016K bytes HMC-EP161

Note 1. Batteries should be replaced before the end of their life expectancy. Refer to

the

CV-series PC Installation Guide

for details on battery replacement.

2. Cannot be used without an CV500-MCW Memory Card Writer.

The following commercially available memory cards can be used for all

CV500/CV1000/CV2000-CPU01-EV1

and CVM1-CPU01/CPU11/CPU21-EV2
CPUs with lot numbers in which the rightmost digit is 6 (6) or higher. The
procedures and applications for using these memory cards is exactly the same
as for the Memory Cards provided by OMRON.

• RAM Memory Cards conforming to JEIDA4.0 and of the following sizes:

64 Kbytes, 128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbyte, and 2 Mbytes.

Note The 2-Mbyte Memory Cards cannot be used in the CV500-MCW01 Memory

Card Writer.
Memory Cards must be formatted before use. RAM and EEPROM Cards can be

formatted with the CVSS/SSS or the CV500-MCW Memory Card Writer;
EPROM Memory Cards can be formatted with the CV500-MCW Memory
Card Writer only.

Caution Memory Cards can be damaged by twisting, shock, or exposure to high temper-

ature, humidity, or direct sunlight. Handle them with care.

2-3-1 Mounting and Removing Memory Cards

Mount a Memory Card to the CPU using the following procedure.

1, 2, 3...

1. Open the cover of the Memory Card compartment.

2. If the Memory Card is RAM or EEPROM, set the write-protect switch to OFF
so that data can be written to the Card.

3. Insert the Memory Card into its compartment. In doing so, a slight resistance
will be felt as the connector on the Memory Card mates with the connector
on the CPU. Continue pushing until the Memory Card is inserted completely
into the CPU. If the Memory Card ON/OFF switch is ON, the Memory Card
indicator will light.

Mounting a Memory Card

Memory Cards Section 2-3

26

4. Close the cover.

Memory Card indicator

Memory Card
ON/OFF switch

Memory Card
eject button

Memory Card

Cover

Removing a Memory Card

1, 2, 3...

1. Open the cover of the Memory Card compartment.

2. Press the Memory Card ON/OFF switch once if the Memory Card indicator
is lit. The Memory Card indicator will turn OFF.

3. Press the Memory Card eject button. The Memory Card will be released al­lowing it to be removed.

4. Pull out the Memory Card.

5. Close the cover.

Note 1. Do not expose the Memory Card to high temperature, humidity, or direct

sunlight.

2. Do not bend the Card or subject it to shock.

3. Do not apply excess force to the Card when inserting or removing it.

4. Do not remove the Card while the Memory Card indicator is lit; doing so may
result in data errors in the memory.

2-3-2 File Transfer between the CPU and Memory Card

Data files can be transferred between the Memory Card and PC data areas with
the FILR(180) and FILW(181) instructions. A program file can be transferred
from the Memory Card with FILP(182) or FLSP(183) to change the program dur­ing operation. Refer to details on these instructions later in the manual.

Memory Card files are identified by both their filename and filename extension.
The following table lists the filenames and filename extensions that are used
with the PC. Filenames are eight characters long and recorded in ASCII. If fewer
than eight characters are needed, enter spaces (ASCII 20) in the remaining by­tes.

Type of file Filename

Extended PC Setup

1

filename

.STD

Data files

filename

.IOM

Ladder program files (files saved with the partial save
operation)

filename

.LDP

SFC program files (one step)

filename

.SFC

Program file (complete program)

filename

.OBJ

Extended PC Setup

1

(transferred at start-up) AUTOEXEC.STD

Program file (complete program transferred at start-up) AUTOEXEC.OBJ

Note 1. Extended PC Setup includes the PC Setup, I/O table, routing tables, data

link tables for data links in SYSMAC LINK and SYSMAC NET Link Systems,

Memory Card Files

Memory Cards Section 2-3

27

Communications Unit settings, BASIC Unit memory switches, and custom­ized settings (function codes and data areas).

2. The files that will be transferred at start-up must be named “AUTOEXEC.”

3. Files called BACKUP are created when the simplified backup function is
used. Refer to

1-13-4 Upgraded Specifications

for details.

There are two methods for automatic transfer of files at start-up:

1, 2, 3...

1. When pin 5 of the CPU DIP switch is ON, the Extended PC Setup file (AUTO­EXEC.STD) and the program file (AUT OEXEC.OBJ) are both transferred to
Program Memory at start-up. If either of the files is missing, a memory error
will occur and neither file will be transferred.

2. The PC Setup can be set (setting D, Program Transfer at Start-up) to trans­fer the program file (AUTOEXEC.OBJ) from the Memory Card to the PC au­tomatically when the PC is turned on. In this case the extended PC Setup file
(AUTOEXEC.STD) is not transferred.

With either method, the transfer will not proceed if the write-protect switch is ON,
but will proceed even if the program memory access right is restricted from the
CVSS/SSS. The transfer normally takes about 4 seconds.

To enable file transfer at start-up, the proper files must be recorded on a Memory
Card in advance from the CVSS/SSS. The Extended PC Setup file (AUTOEX­EC.STD) can be transferred directly from the PC to the Memory Card in online
operations from the CVSS/SSS. The program file (AUTOEXEC.OBJ) can be
created on the Memory Card using one of the following two operations.

• In online operations, transfer the program and other files to the PC and then
transfer the program file to the Memory Card from the PC.

• Convert the program into an object file in offline CVSS/SSS operations, and
then transfer it directly to the Memory Card in online operations.

If the PC is set to transfer the program at start-up but the transfer cannot be com­pleted for some reason, the Memory Card Startup T ransfer Error Flag (A40309)
will be turned ON, a memory error will occur, and the PC will not begin operation.
When the program is not transferred, either find and eliminate the cause of the
error or change the PC settings so that the program won’t be transferred, and
then turn the PC of f and on. The following are possible reasons that the program
cannot be transferred:

• The write-protect switch is ON.

• One or both AUTOEXEC files are missing.

• The Memory Card power is OFF. (If the M/C ON indicator is not lit when the PC

power is ON, press the Memory Card power switch.)

• The Memory Card is not installed.

It is not possible to write to an EPROM Card installed in the CPU. Use the
CV500-MCW Memory Card Writer t o write to an EPROM Card. Refer to the

File Transfer at Start-up

Reading and Writing
Memory Card Files

Memory Cards Section 2-3

28

Memory Card Writer Operation Manual

for details. Set the drive name to “0”

when accessing a Memory Card.
The RAM and EEPROM cards have a write-protect switch, as shown in the dia-

gram below. Turn this switch to OFF when writing to or erasing the Memory Card.

ON

OFF

The three methods of reading and writing Memory Card files are listed below.

1, 2, 3...

1. Reading and writing can be performed as an online operation with a Periph­eral Device, e.g., the CVSS/SSS.

2. Reading and writing can be performed by a command from a host computer.

3. Reading and writing can be performed by instructions in the ladder diagram
program. The four instructions are described in the following table. Refer to

Section 5 Instruction Set

for details.

Instruction Function Filename

FILR(180)
(READ DATA FILE)

Reads the specified data file from the Memory Card and writes it to a
specified data area.

filename

.IOM

FILW(181)
(WRITE DATA FILE)

Reads a specified amount of data file from a specified data area and
writes it to (or creates) the specified data file in the Memory Card.

filename

.IOM

FILP(182)
(READ PROGRAM FILE)

Reads the specified ladder program file (either one action program or
one transition program if SFC programming is being used) from the
Memory Card and writes it in Program Memory.

filename

.LDP

FLSP(183)
(CHANGE STEP PROGRAM)

Reads the specified SFC program file (one step) from the Memory
Card and writes it in Program Memory.

filename

.SFC

4. Reading and writing can be performed by using the simplified backup func­tion. Refer to

1-13-4 Upgraded Specifications

for details.

2-4 Data Memory and Expansion Data Memory Unit

The size of the Data Memory Area for the CV-series PCs is shown in the follow­ing table.

PC DM Area capacity Addresses

CV500 or
CVM1-CPU01-EV2

8K words D00000 to D08191

CV1000, CV2000,
CVM1-CPU11-EV2 or
CVM1-CPU21-EV2

24K words D00000 to D24575

If the above capacities are insufficient, an Expansion Data Memory Unit can be
added to create an EM (Expansion Data Memory) Area with the CV1000,
CV2000, or CVM1-CPU21-EV2. This Unit must be purchased separately as an
option and is not available for other PCs. The EM Area operates the same as the
DM Area, but the EM Area memory is contained in the EM Unit, while DM Area
memory is internal.

EM Area memory is divided into banks of 32K words each. Words E00000 to
E32765 of the current bank can be accessed. The current bank number is con­tained in the least significant digit of A511. A511 is in a read-only area, but the

Data Memory and Expansion Data Memory Unit Section 2-4

29

current bank number can be changed with the EMBC(171) instruction. Refer to

Section 5 Instruction Set

for details.

There are three models of EM Units available, as shown in the following table.

Model Memory capacity Memory banks

CV1000-DM641 64K words 2 (0 and 1)
CV1000-DM151 128K words 4 (0 to 3)
CV1000-DM251 256K words 8 (0 to 7)

The following diagram shows the structure of the EM Unit and identifies its main
components.

Memory element

Pullout
lever

Backup
capacitor

Expansion Data Memory Unit

CPU
connector

2-5 I/O Control Unit and I/O Interface Unit Displays

The I/O Control Unit and I/O Interface Unit have four-character 7-segment dis­plays on the front. There are four display modes that display various information
from the CPU, and the current display mode is indicated by the position of the
decimal point on the display, as shown in the following diagram.

Lit in mode 1
Lit in mode 2
Lit in mode 3
Lit in mode 4

Pressing the mode selector switch changes the display to the next mode. The
Unit will automatically enter the mode specified in the PC Setup (default setting:
mode 1). Refer to

Section 7 PC Setup

for details.

If the CPU Rack power supply is OFF or an initialization error has occurred, the
displays will show “––––” and the rack number will be displayed when the mode
selector switch is held down, but the mode will not be changed.

I/O Control Unit and I/O Interface Unit Displays Section 2-5

30

In mode 1, the first I/O word allocated to that Rack is displayed. If the I/O table
hasn’t been registered yet, or an error occurred during registration, the display
will show “0000.” In the following example, the first word allocated is CIO 0036.

16­pt.
I/O

Word
36

Indicates mode 1

Word37Word

38

16­pt.
I/O

In mode 2, the current CPU status and the rack number of that Rack are dis­played. The information displayed by the four digits is listed below.

1, 2, 3...

1. The leftmost digit indicates whether or not the CPU is operating.
“a” indicates it is operating.
“” indicates it is stopped.

2. The second digit indicates whether or not an error has occurred in the PC.
“e” indicates that a fatal error has occurred.
“f” indicates that a non-fatal error has occurred.
“” indicates that no errors have occurred.

3. The third digit from the left indicates whether or not a peripheral device is
connected to the CPU or Expansion CPU Rack. If a peripheral device is al­ready connected, another cannot be connected.
“b” indicates that a peripheral device is connected.
“” indicates that a peripheral device is not connected.

Note Only one Peripheral Device can be connected to the CPU and I/O In-

terface Units for each PC, but three additional Peripheral Devices
can be connected to the SYSMAC BUS/2 Slave Racks.

4. The rightmost digit indicates the rack number.

Indicates the CPU is in the RUN mode, a non-fatal error has occurred,
a Peripheral Device is connected, and the rack number is 2.

Indicates the rack number
Indicates whether or not Peripheral Devices are connected.

: A Peripheral Device is connected to the CPU or to an I/O Inter­face Unit.
: No Peripheral Device is connected to the CPU or to an I/O Inter-

face Unit.
Indicates mode 2
Indicates the error status of the CPU.

: A fatal error has occurred.

: A non-fatal error has occurred.

: No error has occurred.
Indicates the operating status of the CPU.

: The CPU is operating.

: The CPU has stopped.

In mode 3, the display shows a 4-character message when an IODP(189)
instruction is executed in the program for that Unit. The display mode of the des-

Display Mode 1

Display Mode 2

Display Mode 3

I/O Control Unit and I/O Interface Unit Displays Section 2-5

31

tination unit can be changed to mode 3 automatically by the instruction. Refer to

Section 5 Instruction Set

for details on IODP(189).

Mode 4 is not being used currently. In mode 4, the display will show only the deci­mal point indicating it is in mode 4.

2-6 Peripheral Devices

A total of four Peripheral Devices can be connected to a CV-series PC, as shown
in the following table. Only one Peripheral Device can be connected to the CPU
or an I/O Interface Unit.

If a Peripheral Device is connected to the CPU or an I/O Interface Unit, 3 more
Peripheral Devices can be connected to SYSMAC BUS/2 Remote I/O Slave
Units. If no Peripheral Devices are connected to the CPU or I/O Interface Unit, 4
Peripheral Devices can be connected to SYSMAC BUS/2 Remote I/O Slave
Units. Up to 2 Peripheral Devices can be connected to Remote I/O Slaves under
a single Remote I/O Master Unit.

Connecting Unit Max. connection combinations

CPU 1 0 0
I/O Interface Unit 0 1 0
SYSMAC BUS/2 Remote I/O Slave

Units

3 3 4

Peripheral Devices can be connected even when the PC is ON. Insert the cable
connector until it locks. Using pins 1 and 2 on the CPU DIP switch, set the baud
rate to 50,000 bps for the Graphic Programming Console or Programming Con­sole or to 9,600 bps for a computer running the CV Support Software.

If the ERROR indicator lights when the PC is turned ON, find the source of the
error by displaying error messages at the terminal. For a memory error, perform
the memory clear or program transfer operation online from the CVSS/SSS and
then clear the error. If a memory error cannot be cleared, there might be a hard­ware problem in the CPU.

Note 1. I/O tables cannot be created or edited and broadcast testing is not possible

for SYSMAC LINK Systems if the Peripheral Device is connected to a Slave
in a SYSMAC BUS/2 Remote I/O System.

2. Refer to

Appendix A Standard Models

in the

CV-series PC Installation

Guide

for a list of available Peripheral Devices.

2-7 PC Configuration

The following is an overview of the PC configuration. Refer to the

CV-series P C

Installation Guide

for details.

The basic PC configuration consists of three types of Rack: a CPU Rack, an Ex­pansion CPU Rack, and one or more Expansion I/O Racks. The Expansion CPU
Rack and Expansion I/O Racks are not a required part of the basic system.

An Expansion CPU Rack is used when the CPU Rack cannot accommodate the
required number of CPU Bus Units (SYSMAC BUS/2 Remote I/O Master Units,
BASIC Units, SYSMAC NET Link Units, and SYSMAC LINK Units). Expansion
I/O Racks are used to increase the number of I/O points, but do not support CPU
Bus Units. An illustration of these Racks is provided in

3-3-1 I/O Area

.

An Expansion CPU Rack cannot be connected to a CVM1-BC103/053 Back­plane.

A fourth type of Rack, called a Slave Rack, can be used when the PC is provided
with a SYSMAC BUS or SYSMAC BUS/2 Remote I/O System.

A CPU Rack consists of four components: (1) The CPU Backplane, to which the
CPU, the Power Supply, and other Units are mounted. (2) The CPU, which

Display Mode 4

Connecting Peripheral
Devices

CPU Racks

PC Configuration Section 2-7

32

executes the program and controls the PC. (3) Other Units, such as I/O Units,
Special I/O Units, and Link Units, which provide the physical I/O terminals corre­sponding to I/O points. (4) The I/O Control Unit which provides connections to an
Expansion CPU Rack and Expansion I/O Racks. The I/O Control Unit is not re­quired if an Expansion CPU Rack and Expansion I/O Racks are not connected
and connect be mounted to CVM1-BC103/053 Backplanes. (5) The Power Sup­ply, which provides power to the CPU Rack.

A CPU Rack can be used alone or it can be connected to other Racks to provide
additional I/O points. The CPU Backplane provides slots to which other Units
can be mounted. Depending on the model of Backplane used, either three, five,
or ten slots are available for other Units.

An Expansion CPU Rack Consists of an Expansion CPU Backplane, a Power
Supply, and an I/O Interface Unit to connect to the CPU Rack. Eleven slots are
available for other Units. Up to 16 CPU Bus Units can be connected to the CPU
Rack and Expansion CPU Rack. Expansion I/O Racks can be connected to the
Expansion CPU Rack.

An Expansion CPU Rack cannot be connected to a CVM1-BC103/053 Back­plane.

An Expansion I/O Rack can be thought of as an extension of the PC because it
provides additional slots to which other Units (except CPU Bus Units) can be
mounted. It is built onto an Expansion I/O Backplane to which a Power Supply
and other Units are mounted. Depending on the model of Backplane used, either
four, six, or 11 slots are available for other Units.

An I/O Interface Unit is also mounted to any Expansion I/O Rack to interface the
Rack to the CPU or Expansion CPU Rack. Also, an I/O Control Unit must be
mounted to any CPU Rack to which more than one Expansion I/O Rack is
mounted. If only one Expansion I/O Rack and no Expansion CPU Rack is con­nected, the I/O Interface and I/O Control Units are not required and the Expan­sion I/O Rack can be connected directly to the CPU Rack.

An Expansion I/O Rack is always connected to the CPU via the connectors on
the Backplanes, allowing communication between the two Racks. With C-series
Expansion I/O Racks, up to seven Expansion I/O Racks can be connected in
series to the CPU Rack. With CV-series Expansion I/O Racks, up to seven Ex­pansion I/O Racks can be connected to the CPU Rack in two series. If an Expan­sion CPU Rack is used, only six Expansion I/O Racks can be connected.

Only one Expansion I/O Rack cannot be connected to a CVM1-BC103/053
Backplane.

I/O words are allocated to Units mounted on the CPU, Expansion CPU, and Ex­pansion I/O Racks by rack number, regardless of the order in which the Racks
are connected. The CPU Rack number is fixed at 0, so I/O bits are always allo­cated first to Units on the CPU Rack. Never set the rack number of an Expansion
CPU or Expansion I/O Rack to 0.

Note The PC Setup can be used to control I/O word allocation to Racks and override

allocation by rack number. Refer to

Section 7 PC Setup

for details.

The rack numbers for Expansion CPU and Expansion I/O Racks are set with the
rack number switch (RACK No.) on the I/O Interface Unit mounted on the Rack.
Set the rack number with a standard screwdriver after turning off the Rack power
supply and be careful not to damage the switch groove.

Note 1. A duplication error will occur if 2 or more Racks have the same rack number.

2. If a rack number is set to 8 or 9, the Rack will not be recognized by the CPU.

3. If a single Expansion I/O Rack is connected to a CPU Rack, an I/O Interface
Unit is not required and the rack number of Expansion I/O Rack is fixed at 1.

4. When mounting an Interrupt Input Unit to an Expansion CPU Rack, always
set the rack number of the Expansion CPU Rack to 1.

Expansion CPU Racks

Expansion I/O Racks

Setting Rack Numbers

PC Configuration Section 2-7

33

SECTION 3

Memory Areas

This section describes the way in which PC memory is broken into various areas used for different purposes. The contents of
each area and addressing conventions, including the use of indirect addressing and addressing registers, are also described.

3-1 Introduction 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2 Data Area Structure 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3 CIO (Core I/O) Area 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3-1 I/O Area 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3-2 Work Areas 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3-3 SYSMAC BUS/2 Area 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3-4 Link Area 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3-5 Holding Area 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3-6 CPU Bus Unit Area 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3-7 CompoBus/D Areas 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3-8 SYSMAC BUS Area 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-4 TR (Temporary Relay) Area 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-5 CPU Bus Link Area 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6 Auxiliary Area 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-1 Restart Continuation Bit 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-2 IOM Hold Bit 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-3 Forced Status Hold Bit 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-4 Error Log Reset Bit 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-5 Output OFF Bit 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-6 CPU Bus Unit Restart Bits 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-7 SYSMAC BUS Error Check Bits 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-8 Momentary Power Interruption Time 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-9 CVSS/SSS Flags 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-10 Start-up Time 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-11 Power Interruption Time 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-12 Number of Power Interruptions 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-13 Service Disable Bits 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-14 Message Flags 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-15 Error Log Area 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-16 CPU Bus Unit Initializing Flags 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-17 Wait Flags 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-18 Peripheral Device Flags 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-19 CPU Bus Unit Service Interval 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-20 Memory Card Flags 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-21 Error Code 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-22 FALS Flag 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-23 SFC Fatal Error Flag and Error Code 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-24 Cycle Time Too Long Flag 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-25 Program Error Flag 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-26 I/O Setting Error Flag 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-27 Too Many I/O Points Flag 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-28 CPU Bus Error and Unit Flags 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-29 Duplication Error Flag and Duplicate Rack/CPU Bus Unit Numbers 61. . . . . . . . .

3-6-30 I/O Bus Error Flag and I/O Bus Error Slot/Rack Numbers 61. . . . . . . . . . . . . . . . .

3-6-31 Memory Error Flag 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-32 Power Interruption Flag 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34

3-6-33 CPU Bus Unit Setting Error Flag and Unit Number 61. . . . . . . . . . . . . . . . . . . . . .

3-6-34 Battery Low Flags 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-35 SYSMAC BUS Error Flag, Check Bits, and Master/Unit Numbers 62. . . . . . . . . .

3-6-36 SYSMAC BUS/2 Error Flag and Master/Unit Numbers 62. . . . . . . . . . . . . . . . . . .

3-6-37 CPU Bus Unit Error Flag and Unit Numbers 63. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-38 I/O Verification Error Flag 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-39 SFC Non-fatal Error Flag and Error Code 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-40 Indirect DM BCD Error Flag 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-41 Jump Error Flag 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-42 FAL Flag and FAL Number 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-43 Memory Error Area Location 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-44 Memory Card Start-up Transfer Error Flag 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-45 CPU-recognized Rack Numbers 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-46 CPU Bus Unit Number Setting Error Flag 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-47 CPU Bus Link Error Flag 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-48 Maximum Cycle Time 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-49 Present Cycle Time 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-50 Instruction Execution Error Flag, ER 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-51 Arithmetic Flags 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-52 Step Flag 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-53 First Cycle Flag 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-54 Clock Pulse Bits 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-55 Network Status Flags 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-56 EM Status Flags 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-7 Transition Area 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-8 Step Area 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-9 Timer Area 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-10 Counter Area 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-11 DM and EM Areas 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-12 Index and Data Registers (IR and DR) 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

3-1 Introduction

Various types of data are required to achieve effective and correct control. To
facilitate managing this data, the PC is provided with various memory areas
for data, each of which performs a different function. The areas generally ac­cessible by the user for use in programming are classified as data areas.
Details, including the name, range, and function of each area are summa­rized in the following table. The PC memory addresses are shown in paren­theses. These memory address are used for indirect addressing. Refer to

3-11 DM and EM Areas

and to

5-3 Data Areas, Definers, and Flags

for de-

tails on indirect addressing.

Area PC Range Function

CIO Area
(Core I/O)

All Words: CIO 0000 to CIO 2555

Bits: CIO 000000 to CIO 255515
($0000 to $09FB)

The CIO (Core I/O) Area is divided into
eight sections, five controlling I/O and three
used to store and manipulate data
internally.

Refer to

3-3 CIO (Core I/O) Area

for details.

Temporary
Relay Area

All TR0 to TR7 (bits only)

($09FF)

Used to temporarily store execution
conditions. TR bits are not input when
programming directly in ladder diagrams,
and are used only when programming in
mnemonic form.

CPU Bus
Link Area

All Words: G000 to G255

Bits: G00000 to G25515
($0A00 to $0AFF)

G000 is the PC Status Area; G001 to G004,
the Clock Area. G008 to G127 contain PC
output bits; G128 to G255, CPU Bus Unit
output bits.

Auxiliary
Area

All Words: A000 to A511

Bits: A00000 to A51115
($0B00 to $0CFF)

Contains flags and bits with special
functions.

Transition
Area

CV500 TN0000 to TN0511

($0D00 to $0D1F)

Transition Flags for the transitions in the
SFC program.

CV1000/CV2000 TN0000 to TN1023 ($0D00 to $0D3F)

Step Area CV500 ST0000 to ST0511 ($0E00 to $0E1F) Step Flags for steps in the SFC program. A

CV1000/CV2000 ST0000 to ST1023 ($0E00 to $0E3F)

gg

step is active when its flag is ON.

Timer Area CV500/

CVM1-CPU01-EV2

T0000 to T0511
(Completion Flags: $0F00 to $0F1F
Present Values: $1000 to $11FF)

Used to define timers (normal, high-speed,
and totalizing) and to access Completion
Flags, PV, and SV.

CV1000/CV2000/
CVM1-CPU11-EV2
CVM1-CPU21-EV2

T0000 to T1023
(Completion Flags: $0F00 to $0F3F
Present Values: $1000 to $13FF)

Counter
Area

CV500/
CVM1-CPU01-EV2

C0000 to C0511
(Completion Flags: $0F80 to $0F9F
Present Values: $1800 to $19FF)

Used to define counters (normal, reversible,
and transition) and to access Completion
Flags, PV, and SV.

CV1000/CV2000/
CVM1-CPU11-EV2
CVM1-CPU21-EV2

C0000 to C1023
(Completion Flags: $0F80 to $0FBF
Present Values: $1800 to $1BFF)

DM Area CV500/

CVM1-CPU01-EV2

D00000 to D08191 ($2000 to $3FFF) Used for internal data storage and

manipulation.

CV1000/CV2000/
CVM1-CPU11-EV2
CVM1-CPU21-EV2

D00000 to D24575 ($2000 to $7FFF)

EM Area CV1000/CV2000

CVM1-CPU21-EV2

E00000 to E32765 for each bank; 2,
4, or 8 banks ($8000 to $8FFD)

EM functions just like DM. An Extended
Data Memory Unit must be installed.

Index
registers

All IR0 to IR2 Used for indirect addressing.

Data
registers

All DR0 to DR2 Generally used for indirect addressing.

Introduction Section 3-1

36

Some data areas contain flags and/or control bits. Flags are bits that are au­tomatically turned ON and OFF to indicate particular operation status. Al­though some flags (e.g., the Carry Flag) can be turned ON and OFF by the
user, most flags are read only; they cannot be controlled directly.

Control bits are bits turned ON and OFF by the user to control specific as­pects of operation. Any bit given a name using the word bit rather than the
word flag is a control bit, e.g., Restart Bits are control bits.

3-2 Data Area Structure

Addresses There are two different sets of addresses that can be used to access PC

memory: data area addresses or memory addresses. Data area addresses are
used when specifying an address directly as an operand for an instruction.
Memory addresses are used when using indirect addressing.

When designating a data area address, the acronym for the area (the let­ter(s) identifying the data area) is always required for any area except the
CIO (Core I/O) Area. Although the CIO acronym is given for clarity in text ex­planations, it is not required and not entered when programming.

It is possible also to access any memory location through its hexadecimal PC
memory address with indirect addressing. Refer to

3-11 DM and EM Areas

,

and

3-12 IR and DR Areas

, for details on indirect addressing.

Word Structure Memory areas are divided up into words, each of which consists of 16 bits num-

bered 00 through 15 from right (least significant) to left (most significant). CIO
words 0000 and 0001 are shown below with bit numbers. Here, the content of
each word is shown as all zeros. Bit 00 is called the rightmost bit; bit 15, the left­most bit.

The term least significant bit is often used for rightmost bit; the term most
significant bit, for leftmost bit.

Bit number
CIO word 0000 0000000000000000
CIO word 0001 0000000000000000

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Data in the DM Area and EM Area, as well as Timer and Counter PVs can be
accessed as words only. Transition Flags, Step Flags, and Timer and Count­er Completion Flags can be accessed as bits only. You cannot designate any
of these for operands requiring bit data. Data in the CIO, CPU Bus Link, and
Auxiliary Areas is accessible either by word or by bit, depending on the
instruction in which the data is being used.

To designate one of these areas by word, all that is necessary is the acro­nym, if required, and the two-, three-, or four-digit word address. To desig­nate an area by bit, the word address is combined with the bit number as a
single four- to six-digit address. The following table shows examples of this.
The two rightmost digits of a bit address must indicate a bit between 00 and
15, e.g., the rightmost digit must be 5 or less when the next digit to the left
is 1.

Flags and Control Bits

Data Area Structure Section 3-2

37

The same timer and counter numbers can be used to designate either the
present value (PV) of the timer or counter, or the Completion Flag for the tim­er or counter. This is explained in more detail in

3-9 Timer Area

and

3-10

Counter Area

.

Area Word designation Bit designation

CIO 0000 000015 (leftmost bit in word CIO 0000)
CIO 0252 025200 (rightmost bit in word CIO 0252)
DM D01250 Not possible
T T215 (designates PV) T215 (designates Completion Flag)
A A012 A01200

To designate a word by its PC Memory address, write the hexadecimal ad­dress to an Index Register, DM, or EM word and indirectly address the oper­and through that register or word. Refer to

3-11 DM and EM Areas

and

3-12

IR and DR Areas

for details on indirect addressing.

Word data input as decimal values is stored in binary-coded decimal (BCD);
word data entered as hexadecimal is stored in binary form. Each four bits of
a word represent one digit, either a hexadecimal or decimal digit, numerically
equivalent to the value of the binary bits. One word of data thus contains four
digits, which are numbered from right to left. These digit numbers and the
corresponding bit numbers for one word are shown below.

Bit number
Contents 0000000000000000

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Digit number 3210

When referring to the entire word, the digit numbered 0 is called the right­most digit; the one numbered 3, the leftmost digit.

When inputting data, it must be input in the proper form for the intended pur­pose. This is no problem when designating bits, which are turned ON (equiv­alent to a binary value of 1) or OFF (a binary value of 0). When inputting
word data, however, it is important to input it either as decimal or as hexade­cimal, depending on what is called for by the instruction it is to be used for.

Section 5 Instruction Set

specifies when a particular form of data is required

for an instruction.

Binary and hexadecimal can be easily converted back and forth because
each four bits of a binary number is numerically equivalent to one digit of a
hexadecimal number. The binary number 0101111101011111 is converted to
hexadecimal by considering each set of four bits in order from the right.
Binary 1111 is hexadecimal F; binary 0101 is hexadecimal 5. The hexadeci­mal equivalent would thus be 5F5F, or 24,415 in decimal (163 x 5 + 162 x 15
+ 16 x 5 + 15).

Decimal and BCD are easily converted back and forth. In this case, each
BCD digit (i.e., each group of four BCD bits) is numerically equivalent to the
corresponding decimal digit. The BCD bits 0101011101010111 are converted
to decimal by considering each four bits from the right. Binary 0101 is deci­mal 5; binary 0111 is decimal 7. The decimal equivalent would thus be 5,757.
Note that this is not the same numeric value as the hexadecimal equivalent
of 0101011101010111, which would be 5,757 hexadecimal, or 22,359 in deci­mal (163 x 5 + 162 x 7 + 16 x 5 + 7).

Data Structure

Converting Different Forms
of Data

Data Area Structure Section 3-2

38

Because the numeric equivalent of each four BCD binary bits must be nu­merically equivalent to a decimal value, any four bit combination numerically
greater than 9 cannot be used, e.g., 1011 is not allowed because it is numeri­cally equivalent to 11, which cannot be expressed as a single digit in decimal
notation. The binary bits 1011 are of course allowed in hexadecimal and are
equivalent to the hexadecimal digit B.

There are instructions provided to convert data between BCD and hexadeci­mal. Refer to

5-15 Data Conversion

for details. Tables of binary equivalents

to hexadecimal and BCD digits are provided in the appendices for reference.

Decimal points are used in timers only. The least significant digit represents
tenths of a second. All arithmetic instructions operate on integers only. When
inputting data for use by Special I/O Units or other special applications, be
sure to check on the type of data required for the application.

Signed and Unsigned Data

This section explains signed and unsigned binary data formats. Three instruc­tions, MAX(165), MIN(166), and SUM(167), can use either signed or unsigned
data.

Unsigned binary is the standard format used in OMRON PCs. Data in this manu­al are unsigned unless otherwise stated. Unsigned binary values are always
positive and range from 0 ($0000) to 65,535 ($FFFF). Eight-digit values range
from 0 ($0000 0000) to 4,294,967,295 ($FFFF FFFF).

Bit number
Contents 0000000000000000

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Digit value 16

3

16

2

16

1

16

0

Signed binary data can have either a positive and negative value. The sign is
indicated by the status of bit 15. If bit 15 is OFF, the number is positive and if bit 15
is ON, the number is negative. Positive signed binary values range from 0
($0000) to 32,767 ($7FFF), and negative signed binary values range from
–32,768 ($8000) to –1 ($FFFF).

Bit number
Contents 0000000000000000

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Digit value 16

3

16

2

16

1

16

0

Sign indicator

Eight-digit positive values range from 0 ($0000 0000) to 2,147,483,647 ($7FFF
FFFF), and eight-digit negative values range from –2,147,483,648 ($8000

0000) to –1 ($FFFF FFFF).

Decimal Points

Unsigned binary

Signed Binary

Data Area Structure Section 3-2

39

Positive signed binary data is identical to unsigned binary data (up to 32,767)
and can be converted using BIN(100). The following procedure converts nega­tive decimal values between –32,768 and –1 to signed binary. In this example
–12345 is converted to CFC7.

Bit number
Contents 0011000000111001

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

1. First take the absolute value (12345) and convert to unsigned binary:

Bit number
Contents 1100111111000110

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

2. Next take the complement:

Bit number
Contents 1100111111000111

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

3. Finally add one:

Reverse the procedure to convert negative signed binary data to decimal.

Converting Decimal to
Signed Binary

Data Area Structure Section 3-2

40

3-3 CIO (Core I/O) Area

CIO Area addresses run from words CIO 0000 through CIO 2555 and bits
CIO 000000 through CIO 255515 and are divided into eight data areas. Five
of these data areas are used to control I/O points and Special Units, and
three data areas are used to manipulate and store data internally. The CIO
Area is accessible either by bit or by word. No prefix is required when input­ting data area addresses; the CIO prefix is used only for clarity in descrip­tions.

The name, range, and function of each data area within the CIO Area are sum­marized in the following table. PC memory addresses are in parentheses.

Area PC Range Function

I/O Area CV500

CVM1-CPU01-EV2

Words: CIO 0000 to CIO 0031
Bits: CIO 000000 to CIO 003115
($0000 to $001F)

Allocated to I/O in the System and used to
control I/O points. Bits not used to control
I/O points can be used as work bits. The PC

CV1000
CVM1-CPU11-EV2

Words: CIO 0000 to CIO 0063
Bits: CIO 000000 to CIO 006315
($0000 to $003F)

Setup can be used to control allocations.
Once I/O table has been registered, input

bits are displayed on CVSS/SSS with an I;

CV2000
CVM1-CPU21-EV2

Words: CIO 0000 to CIO 0127
Bits: CIO 000000 to CIO 012715
($0000 to $007F)

bits are dis layed on CVSS/SSS with an I

output bits, with a Q.

Work Area CV500

CVM1-CPU01-EV2

Words: CIO 0032 to CIO 0199
Bits: CIO 003200 to CIO 019915
($0020 to $00C7)

These bits are used in the program to
manipulate or to temporarily store data.

CV1000
CVM1-CPU11-EV2

Words: CIO 0064 to CIO 0199
Bits: CIO 006400 to CIO 019915
($0040 to $00C7)

CV2000
CVM1-CPU21-EV2

Words: CIO 0128 to CIO 0199
Bits: CIO 012800 to CIO 019915
($0080 to $00C7)

SYSMAC
BUS/2
Area

CV500/
CVM1-CPU01-EV2

Words: CIO 0200 to CIO 0599
Bits: CIO 020000 to CIO 059915
($00C8 to $0257)

These bits are used for remote I/O points in
the SYSMAC BUS/2 Remote I/O System
unless the default allocations are changed in
the PC Setup.

CV1000/CV2000/
CVM1-CPU11-EV2

Words: CIO 0200 to CIO 0999
Bits: CIO 020000 to CIO 099915
($00C8 to $03E7)

Bits not used to control I/O points can be
used as work bits.

Link Area All Words: CIO 1000 to CIO 1199

Bits: CIO 100000 to CIO 119915
($03E8 to $04AF)

These bits are used for SYSMAC NET Link
and SYSMAC LINK Systems. Bits not used
for data links can be used as work bits.
These bits can be set as holding bits via PC
Setup.

Holding
Area

All Words: CIO 1200 to CIO 1499

Bits: CIO 120000 to CIO 149915
($04B0 to $05DB)

Used to store data and to retain the data
values when the power is turned off.

CPU Bus
Unit Area

All Words: CIO 1500 to CIO 1899

Bits: CIO 150000 to CIO 189915
($05DC to $076B)

Used to store the operating status of CPU
Bus Units. Bits not used by CPU Bus Units
can be used as work bits. These bits can be
set as holding bits via the PC Setup.

CompoBus
/D Areas

All Words: CIO 1900 to CIO 1963

Bits: CIO 190000 to CIO 196315
($076C to $0AB)

Words: CIO 2000 to CIO 2063
Bits: CIO 200000 to CIO 206315
($07D0 to $080F)

These bits are used in CompoBus/D
networks. Bits not used for CompoBus/D
can be used as work bits.

CIO (Core I/O) Area Section 3-3

41

Area FunctionRangePC

Work
Areas

All Words: CIO 1964 to CIO 1999

Bits: CIO 196400 to CIO 199915
($07AC to $07CF)

Words: CIO 2064 to CIO 2299
Bits: CIO 206400 to CIO 229915
($0810 to $08FB)

These bits are used in the program to
manipulate or to temporarily store data.
These bits can be set as holding bits via the
PC Setup.

SYSMAC
BUS Area

CV500
CVM1-CPU01-EV2

Words: CIO 2300 to CIO 2427
Bits: CIO 230000 to CIO 242715
($08FC to $097B)

These bits are used for remote I/O points in
the SYSMAC BUS Remote I/O System
unless the default allocations are changed in
the PC Setup.

CV1000/CV2000
CVM1-CPU11-EV2
CVM1-CPU21-EV2

Words: CIO 2300 to CIO 2555
Bits: CIO 230000 to CIO 255515
($08FC to $09FB)

Bits not used to control I/O points can be
used as work bits. Up to word 2399 can be
set as holding bits via the PC Setup.

3-3-1 I/O Area

The I/O Area is used as data to control I/O points.Those words that are used to
control I/O points are called I/O words. Bits in I/O words are called I/O bits. I/O
Area bits that are not allocated as I/O bits are reset when power is interrupted or
PC operation is stopped. The number of I/O words varies between the PCs as
shown in the following table.

PC I/O words I/O bits

CV500/
CVM1-CPU01-EV2

CIO 0000 to CIO 0031 CIO 000000 to CIO 003115

CV1000/
CVM1-CPU11-EV2

CIO 0000 to CIO 0063 CIO 000000 to CIO 006315

CV2000
CVM1-CPU21-EV2

CIO 0000 to CIO 0127 CIO 000000 to CIO 012715

The maximum number of I/O bits is 16 (bits/word) times the number of I/O
words, i.e., 512 bits for the CV500 or CVM1-CPU01-EV2; 1,024 for the
CV1000 or CVM1-CPU11-EV2; and 2,048 for the CV2000 or
CVM1-CPU21-EV2. I/O bits are assigned to input or output points on Units
connected at various locations in the PC System, as described later in this
section (see

Word Allocations

).

If an I/O point on a Unit brings an input into the PC, the bit assigned to it is an
input bit; if the point sends an output from the PC, the bit assigned to it is an
output bit. To turn ON an output, the output bit assigned to it must be turned
ON from the program or from a Peripheral Device. When an input turns ON,
the input bit assigned to it also turns ON and the status of the input can be
accessed indirectly by reading the status of the input bit assigned to it. Input
status and control output status is thus manipulated through I/O bits.

After the I/O Table has been registered (see

Word Allocations

, below), an “I” will
appear before input bit addresses and a “Q” will appear before output bit ad­dresses on CVSS/SSS (CV Support Software/SYSMAC Support Software) dis­plays.

I/O bits that are not assigned to I/O points can be used as work bits.
Input bits record external signals input to the PC and can be used in any or-

der in programming. Each input bit can also be used in as many instructions
as required to achieve effective and proper control. They cannot be used as
operands in instructions that control bit status, e.g., the OUTPUT, DIFFER­ENTIATE UP, and KEEP instructions. In other words, input bits should be
treated as read-only bits.

Output bits are used to output program execution results and can be used in
any order in programming. Generally speaking, any one output bit should be

I/O Words

Input Bit Usage

Output Bit Usage

CIO (Core I/O) Area Section 3-3

42

used in only one instruction that controls its status, including OUT, KEEP(11),
DIFU(13), DIFD(14), and SFT(10). If an output bit is used in more than one
such instruction, only the status determined by the last instruction will actual­ly be output from the PC during the normal I/O refresh period.

If you control the status of an output bit in more than one instruction, be sure
to consider proper output timing and test the program before actual applica­tion. See

5-14-1 SHIFT REGISTER – SFT(050)

for an example that uses an

output bit in two “bit-control” instructions.

I/O words in the CIO Area are allocated to Units mounted on Racks or other­wise connected to the PC by performing the I/O Table Registration operation.
This operation creates in memory a table called an I/O table that records
what words and how many words are allocated to the Units and whether
these words are input or output words. The actual procedure for this opera­tion is described in the

CVSS/SSS Operation Manuals

.

The first word allocated to each Rack can be set with the CVSS/SSS under the
PC Setup. When the I/O Table Registration operation is performed, the system
assigns word addresses to Units in the order in which they are mounted left to
right on each Rack, beginning with the first word set in the PC Setup. The as­signed words must be between CIO 0000 and CIO 0511.

For any Racks not assigned a first word in the PC Setup menu when the I/O
Table is registered, the system automatically assigns word addresses to
Units. Word allocation begins with the leftmost Unit on the CPU Rack, and
then continues left to right on the CPU Expansion Rack or Expansion I/O
Rack with the lowest rack number set on its I/O Interface Unit. The order in
which the Expansion I/O Racks are connected is not relevant in word alloca­tion, only the rack numbers. I/O words start from CIO 0000 for the first Unit
on the CPU Rack and continue consecutively: CIO 0001, CIO 0002, etc.

If the lowest word assigned to a Rack in the PC Setup menu is not higher than the
total number of words required by Racks that aren’t assigned a first word, the
same word will be assigned to two Units and a duplication error will occur. A du­plication error will also occur if words assigned to Racks overlap those assigned
to Units controlled through Remote I/O Masters in the SYSMAC BUS/2 Area,
which begins at CIO 0200. Be careful when setting areas from the CVSS/SSS to
avoid overlapping allocations.

There are no specific words associated with any particular slot because dif­ferent Units can require a different number of words. Rather, each Unit is as­signed the next word(s) following the word(s) assigned to the previous Unit. If
there are any empty slots, no words will be assigned to those slots. Words
are only assigned when a Unit is mounted; all empty slots are skipped. The
numbers of I/O words allocated to the most common types of Unit are shown
below.

Unit Words required

16-pt I/O Units 1 word
24- or 32-pt I/O Units 2 words
64-pt I/O Units 4 words
Interrupt Input Unit 1 word
Dummy I/O Unit Set to 1, 2, or 4 words
Analog I/O Units 2 or 4 words
High-speed Counter Units CT012/CT041: 2 words

CT021: 2 or 4 words
MCR Units (See note 1) 4 words
PID Unit (See notes 1 and 2) 4 words

Word Allocations

CIO (Core I/O) Area Section 3-3

43

Unit Words required

Position Control Units (See note 2) NC111/NC103/NC112/NC121: 4 words

NC222: 2 words
I/O Interface Unit None
Cam Positioner 2 or 4 words
Ladder Program I/O Unit 2 words
ASCII Unit (ASC03 not applicable; use

ASC04.)

2 or 4 words

SYSMAC NET Link Unit None (assigned CIO Link Area words)
SYSMAC LINK Unit None (assigned CIO Link Area words)
SYSMAC BUS/2 Remote I/O Master Unit None (See note 1)
CompoBus/D Master Unit None
BASIC Unit None
Personal Computer Unit None (See note 3)
Motion Control Units None
Temperature Control Data Link Unit None
Ethernet Unit None
Remote I/O Master Unit None (See note 4)
Remote I/O Slave Unit None (See note 4)
I/O Link Unit 1 or 2 words (See note 5)
I/O Control Unit None

Note 1. PID Units, Magnetic Card Reader Units, Fuzzy Logic Units, and Cam Posi-

tion Units cannot be mounted to Slave Racks in SYSMAC BUS/2 Systems.

2. The PID Unit and some Position Control Units require two slots on a Rack.

3. The Personal Computer Unit requires four slots on a Rack.

4. Although no words are allocated to the Remote I/O Master and Slave Units
themselves, words are allocated to Units mounted to Slave Racks or other­wise connected to the Remote I/O System. Refer to

3-3-3 SYSMAC BUS/2

Area

and

3-3-8 SYSMAC BUS Area

, for details.

5. 3G2A5-LK010-E I/O Link Units and C500-ETL01 Teaching Tool cannot be
set to 16 point input/16 point output on a CV-series PC.

6. The I/O READ and I/O WRITE instructions (READ(190)/WRIT(191)) can be
used for Units mounted to Slave Racks in SYSMAC BUS/2 Systems (but not
in SYSMAC BUS Systems) under the following conditions.

a) The lot number of the Remote I/O Master Unit and Remote I/O Slave Unit

must be the same as or latter than the following.

1992
October (Y: November; Z: December)
1st

01 X 2

b) The DIP switch on the Remote I/O Slave Unit must be set to “54MH.”
c) The Special I/O Unit must be one of the following: AD101, CT012,

CT041, ASC04, IDS01-V1, IDS02, IDS21, IDS22, LDP01-V1, or NC222.

7. Refer to the

CV-series PC Installation Guide

or to the operation manuals for

individual Units for specific mounting procedures and limitations.

Once the word(s) assigned to a Unit has been determined, the use of individ­ual bits in the word(s) is determined by the type of Unit. If the Unit is a Spe­cial I/O Unit, I/O Link Unit, or CPU Bus Unit, each bit will have a dedicated
function. Refer to the

Operation Manuals

for the relevant Units for details.

With I/O Units, bits within a word are assigned to terminals starting at the top
of the I/O Unit with bit 00 and going sequentially to the bottom. If the first Unit

CIO (Core I/O) Area Section 3-3

44

on the left of the CPU Rack is an Input Unit, the top terminals (i.e., the top
input point) will be assigned CIO 000000, the next terminals, CIO 000001,
and so forth for all of the terminals on the Unit. The allocation order is illus­trated below. Arrows indicate the order in which words are allocated to Units
for the rack number settings indicated.

CPU Rack

Starting point

Empty slots or Units not
requiring word allocation
(no words allocated)

CPU

Power Supply Unit

Power Supply Unit

Expansion CPU Rack

I/O Control UnitI/O Interface Unit

Rack #1

Basic I/O Allocation I/O Word Allocation Example

CPU

Power Supply Unit

Power Supply Unit

I/O Control UnitI/O Interface Unit

CPU Rack

Expansion I/O Rack

CIO 0000

CIO 0001

CIO 0002 and 0003

CIO 0004

CIO 0005

CIO 0006

CIO 0007

CIO 0008 and 0009

CIO 0010

CIO 0011

CIO 0012 and 0013

CIO 0014

CIO 0015

CIO 0016

CIO 0017

CIO 0018

CIO 0019 and 0020

CIO 0021

Empty (no allocation)

CIO 0022

CIO 0023

Power Supply Unit

I/O Interface Unit

Expansion I/O Rack

Rack #1

Power Supply Unit

I/O Interface Unit

CIO 0031

CIO 0032

CIO 0033

CIO 0034

CIO 0035

CIO 0036

CIO 0037

CIO 0038

CIO 0039

CIO 0040

CIO 0041

Power Supply Unit

I/O Interface Unit

Rack #3

Expansion I/O Rack

Power Supply Unit

I/O Interface Unit

CIO 0024

CIO 0025

CIO 0026

CIO 0027

CIO 0028

CIO 0029

CIO 0030

Empty (no allocation)

Power Supply Unit

I/O Interface Unit

Expansion I/O Rack

Rack #2

Empty (no allocation)

Empty (no allocation)

Empty (no allocation)

Once Units have been mounted and the I/O Table Registration operation has
been performed, a change to any Unit mounted to a Rack that affects the
type of I/O word, or the number of words required by the Unit will cause an
I/O verification error to occur. This includes adding Units to previously un­used slots or removing Units that have already been allocated word(s). A
Unit can, however, be replaced with another Unit that requires the same
number of input words and the same number of output words without gener-

Rack Changes

CIO (Core I/O) Area Section 3-3

!

45

ating an I/O verification error. Dummy I/O Units are available to fill slots for
future use or to replace Units that are no longer needed (see

Word Reserva-

tions

, below).

There are two ways, however, to change the I/O table registered in memory.
One is to allocate words to a slot that is not currently being used. This meth­od is described below in

Word Reservations

.

The other way is to perform the I/O Table Registration operation again. When
this is done, all I/O words will be reallocated according to the Units mounted
to the Racks at the time. If the number of words allocated to any one slot
changes, all word allocations past that slot will also change, requiring that the
program be changed to allow for this.

Sometimes program changes can be avoided when a Unit is removed from a
Rack or you know that you are going to have to add a Unit later by reserving
words. Although designed to enable slot reservations for future use, a slot
reservation can be left permanently to prevent what could be extensive pro­gram changes.

Caution Always be sure to change word and bit addresses in the program whenever a

change to Units on a Rack affects word allocations. Failure to do so may cause
improper I/O operations.

Words can be reserved at a certain slot for future use either by mounting a
Dummy I/O Unit to the slot before performing the I/O Table Registration op­eration or by performing an I/O Table Change operation after performing the
I/O Table Registration operation.

A Dummy I/O Unit provides settings to designate word types (input or output)
and length (one, two, or four words). After I/O Table Generation has been
performed and a Dummy I/O Unit has been allocated the words designated
by these settings, it can be replaced at any time with a Unit that requires the
same type and number of words, e.g., if a Dummy I/O Unit is set for two input
words, it can be replaced with any 24- or 32-point Input Unit or any other Unit
that requires two input words.

Once an I/O table has been registered, it can be changed using the I/O Table
Change operation described in

CVSS/SSS Operation Manuals

. This opera­tion can be used to reserve up to four input words, output words, or non-de­fined words at a time. The I/O Table Change operation must be performed
after the I/O Table Registration operation. If I/O Table Registration is re­peated, all word reservations will be cancelled, and I/O Table Change will
have to be repeated.

3-3-2 Work Areas

There are two Work Areas available in PC memory. Words and bits in the Work
Areas can be used in programming as required to control other bits, but are not
used for direct external I/O. Other bits and words in the CIO Area which are not
being used for their intended purpose can also be used as work words and work
bits. Actual application of work bits and work words is described in

Section 4

Writing Programs

.

Word Reservations

CIO (Core I/O) Area Section 3-3

46

Work words and bits are reset when power is interrupted or PC operation is
stopped, but they are not reset when a FALS error instruction is executed in the
program.

PC Work words Work bits

CV500
CVM1-CPU01-EV2

CIO 0032 to CIO 0199 CIO 003200 to CIO 019915

CV1000
CVM1-CPU11-EV2

CIO 0064 to CIO 0199 CIO 006400 to CIO 019915

CV2000
CVM1-CPU21-EV2

CIO 0128 to CIO 0199 CIO 012800 to CIO 019915

All CIO 1964 to CIO 1999

CIO 2064 to CIO 2299

CIO 196400 to CIO 199915
CIO 206400 to CIO 229915

3-3-3 SYSMAC BUS/2 Area

I/O bits allocated in the SYSMAC BUS/2 Area correspond to I/O points on I/O
Terminals (group-1 and group-2 Slaves), Units mounted to Slave Racks
(group-3 Slaves), or other Units connected to SYSMAC BUS/2 Remote I/O Mas­ter Units (RM/2). Up to four Masters can be connected to the CV1000, CV2000,
CVM1-CPU11-EV2, or CVM1-CPU21-EV2 (RM/2 #0 to RM/2 #3), and up to two
Masters can be connected to the CV500 or CVM1-CPU01-EV2 (RM/2 #0 and
RM/2 #1). The total number of I/O points required for I/O Terminals, Units on
Slave Racks, and other Units in the SYSMAC BUS/2 Remote I/O System must
not exceed 2,048 (128 words) for the CV1000, CV2000, CVM1-CPU11-EV2, or
CVM1-CPU21-EV2, and 1,024 (64 words) for the CV500 or CVM1-CPU01-EV2.

SYSMAC BUS/2 Area address allocation can be customized with the PC Set­up using the CVSS/SSS. The first word allocated to the group-1, group-2,
and group-3 Slaves, as well as the size of each of these areas, can be
changed. The following table shows the default address allocations.

RM/2 # Group-1 Slaves* Group-2 Slaves* Group-3 Slaves

0 CIO 0200 to CIO 0249 CIO 0250 to CIO 0299 CIO 0300 to CIO 0399
1 CIO 0400 to CIO 0449 CIO 0450 to CIO 0499 CIO 0500 to CIO 0599
2 CIO 0600 to CIO 0649 CIO 0650 to CIO 0699 CIO 0700 to CIO 0799
3 CIO 0800 to CIO 0849 CIO 0850 to CIO 0899 CIO 0900 to CIO 0999

*Group-1 Slaves allocated up to 64 I/O points. Group-2 Slaves are medium-sized Units
allocated up to 128 I/O points. Group-3 Slaves are used to form Slave Racks.

As with I/O area allocations to CPU, Expansion CPU, and Expansion I/O
Racks, word allocation begins with the Slaves connected to the Master with
the lowest unit number, RM/2 #0, regardless of the order that the Masters are
mounted. Likewise, word allocation to Units connected to RM/2 #0 begins
with the Slaves that have the lowest unit numbers, regardless of the order
that the Slaves are mounted.

Up to 8 Slave Racks can be connected to each RM/2 Master. Word address­es are assigned to Units on Slave Racks in the order in which they are
mounted left to right. Refer to the

SYSMAC BUS/2 Remote I/O System

Manual

for details on word allocation to Slaves and Units on Slave Racks.

After the I/O Table has been registered or edited, an “I” will appear before
input bit addresses and a “Q” will appear before output bit addresses on
CVSS/SSS displays. Refer to the

CVSS/SSS Operation Manuals

for details

on the PC Setup.

3-3-4 Link Area

The Link Area is used as a common data area to automatically transfer in­formation between PCs. This data transfer is achieved through data links in

CIO (Core I/O) Area Section 3-3

47

either a SYSMAC LINK System or a SYSMAC NET Link System. Link Area
addresses run from CIO 1000 through CIO 1199. Link Area words CIO 1000
through CIO 1063 and DM Area words D00000 through D00127 are auto­matically used for data link tables unless specific link words are designated.
Allocations can be designated from the CVSS/SSS. Refer to the

CVSS/SSS

Operation Manuals

, and the

SYSMAC LINK System Manual

, or

SYSMAC

NET Link System Manual

for details.

3-3-5 Holding Area

The Holding Area is used to store/manipulate various kinds of data and can
be accessed either by word or by bit. Holding Area bits can be used in any
order required and can be programmed as often as required.

The default Holding Area word addresses range from CIO 1200 through CIO
1499; bit addresses, from CIO 120000 through CIO 149915. The range of the
Holding Area can be changed to any size between CIO 1000 through CIO
2399 with the PC Setup from the CVSS/SSS. If the Holding Area is in­creased, it will overlap other areas. An “H” will appear before Holding Area bit
addresses on the CVSS/SSS screen. Refer to the

CVSS/SSS Operation

Manuals

for details.

The Holding Area retains status when the operating mode is changed, power
is interrupted, or PC operation is stopped.

Holding Area bits and words can be used to preserve data whenever PC op­eration is stopped. Holding bits also have various special applications, such
as creating latching relays with the KEEP instruction and forming self-holding
outputs. These are discussed in

Section 4 Writing Programs

and

Section 5

Instruction Set

.

3-3-6 CPU Bus Unit Area

Two types of external bus are provided for C V-series PCs: the high-speed CPU
bus (S Bus) and the I/O bus. Units that connect to the CPU bus on the CPU or
Expansion CPU Rack are called CPU Bus Units and include the SYSMAC NET
Link Unit, SYSMAC LINK Unit, SYSMAC BUS/2 Remote I/O Master Unit, BASIC
Unit, and Personal Computer Unit.

CPU Bus Unit Area addresses range from CIO 1500 through CIO 1899. These
400 words are divided into 16 groups of 25 words each. These are allocated to
CPU Bus Units according their unit number settings as shown in the following
tables.

Unit # 0 1 2 3 4 5 6 7

CIO

words

1500

to

1524

1525

to

1549

1550

to

1574

1575

to

1599

1600

to

1624

1625

to

1649

1650

to

1674

1675

to

1699

Unit # 8 9 10 11 12 13 14 15

CIO

words

1700

to

1724

1725

to

1749

1750

to

1774

1775

to

1799

1800

to

1824

1825

to

1849

1850

to

1874

1875

to

1899

An additional1600 words in the DM Area (D02000 to D03599) are provided for
CPU Bus Units. The particular function of words allocated to the Unit depends on
the CPU Bus Unit being used.

3-3-7 CompoBus/D Areas

I/O bits allocated to CompoBus/D correspond to external I/O points on the de­vices connected to the CompoBus/D device network. Refer to

CompoBus/D

(DeviceNet) Operation Manual

(W267) for further information.

CIO (Core I/O) Area Section 3-3

48

3-3-8 SYSMAC BUS Area

I/O bits allocated in the SYSMAC BUS Area correspond to external I/O points on
I/O Terminals, Optical I/O Units, or I/O Units mounted to Slave Racks that are
connected to SYSMAC BUS Remote I/O Master Units (RM). Up to 8 Masters
can be connected to the CV1000, CV2000, CVM1-CPU11-EV2, or
CVM1-CPU21-EV2, and up to 4 Masters can be connected to the CV500 or
CVM1-CPU01-EV2. The total number of I/O points in the SYSMAC BUS System
must not exceed 2,048 (128 words) for the CVM1-CPU21-EV2, 1024 (64 words)
for the CV1000, CV2000, or CVM1-CPU11-EV2, and 512 (32 words) for the
CV500 or CVM1-CPU01-EV2.

Unit numbers are assigned to Masters automatically when the I/O Table is
registered or edited, according to the order in which the Masters are mounted
(taking into account rack number settings). The first word allocated to each
Master can be changed with the PC Setup using the CVSS/SSS.

SYSMAC BUS Area addresses range from CIO 2300 through CIO 2555. These
256 words are divided into 8 groups of 32 words each and are allocated to Mas­ters according their number setting. The following table shows the default ad­dress allocation.

RM # 0 1 2 3 4 5 6 7

CIO

words

2300

to

2331

2332

to

2363

2364

to

2395

2396

to

2427

2428

to

2459

2460

to

2491

2492

to

2523

2524

to

2555

Words are allocated to Units on Slave Racks in order beginning with the
Slave Rack with the lowest unit number. Up to 8 Slave Racks can be con­nected to each Master. Word addresses are assigned to Units in the first
Slave Rack in the order in which they are mounted left to right. Word alloca­tion then continues left to right on the Slave Rack with the next lowest unit
number, and so on until words have been allocated to all of the Slave Racks.

Words are allocated to I/O Terminals and Optical I/O Units according to word set­tings on the Unit. The word allocated is calculated by adding the first word of the
Master and the word setting on the Unit. To minimize the chance of overlapping
with words allocated to Slave Racks, it is recommended to set I/O Terminal and
Optical I/O Unit settings beginning from 31, the last word allocated to the Master,
and continuing down to lower settings.

Refer to the

SYSMAC BUS Remote I/O System Manual

for details on word

allocation to I/O Terminals and Slave Racks.
After the I/O Table has been registered or edited, an “I” will appear before

input bit addresses and a “Q” will appear before output bit addresses on
CVSS/SSS displays. Refer to the

CVSS/SSS Operation Manuals

for details

on the PC Setup.

3-4 TR (Temporary Relay) Area

The TR Area provides eight bits that are used only with the LD and OUT
instructions to enable certain types of branching ladder diagram program­ming. It is only necessary to use TR bits when entering the program using
mnemonic code. The CVSS/SSS enters TR bits automatically, although the
TR bits are not shown on the CVSS/SSS screen. The use of TR bits is de­scribed in

Section 4 Writing Programs

.

TR addresses range from TR0 though TR7. Each of these bits can be used
as many times as required and in any order required as long as the same TR
bit is not used twice in the same instruction block.

TR (Temporary Relay) Area Section 3-4

!

49

3-5 CPU Bus Link Area

The CPU Bus Link Area is indicated by a G prefix. Addresses range from G000
to G255. The CPU Bus Link Area can be divided into 3 sections, the PC Status
Area, Clock/Calendar Area, and Data Link Area.

G000 is the PC Status Area and contains flags and control bits relating to PC
status. G001 to G004 are the Clock/Calendar Area, and G005 to G007 are not
used.

Most of the CPU Bus Link Area (G008 to G255) is taken up by the Data Link Area
which is used to transfer information between CPU Bus Units and the CPU. CPU
Bus Units connect to the CPU bus on the CPU Rack or Expansion CPU Rack.

Caution The CPU Bus Link Area words G000 through G007 cannot be written to from the

user program and can only be read from to access the data provided there.

PC Status Area The following table shows the specific functions of flags and control bits in

the PC Status Area, G000.

G000 bit(s) Function

00 ON when the PC is in PROGRAM mode.
01 ON when the PC is in DEBUG mode.
02 ON when the PC is in MONITOR mode.
03 ON when the PC is in RUN mode.
04 ON when the program is being executed (RUN or MONITOR mode).
05 Not used.
06 ON when a non-fatal error has occured. (PC operation continues.)
07 ON when a fatal error has occured. (PC stops.)
08 to 10 Not used.
11 UM Protect Bit. Prevents both reading out and writing to Program

Memory when turned ON. Set with the CVSS/SSS.

12 Memory Card Protect Bit. Prevents writing to Memory Cards when

turned ON. Set with the Memory Card Protect Switch.
13 and 14 Not used.
15 UM Protect Bit. Prevents writing to Program Memory when turned

ON. Set with the System Protect Key Switch.

Calendar/Clock Area The following table shows the function of bits in the Calendar/Clock Area,

G001 to G004. The clock is set with the CVSS/SSS. Refer to the

CVSS/SSS

Operation Manuals

for more details.

Word Bits Contents Possible values

G001 00 to 07 Seconds 00 to 59

08 to 15 Minutes 00 to 59

G002 00 to 07 Hours 00 to 23 (24-hour system)

08 to 15 Day of month 01 to 31 (adjusted by month and for leap year)

G003 00 to 07 Month 1 to 12

08 to 15 Year 00 to 99 (Rightmost two digits of year)

G004 00 to 07 Day of week 00 to 06 (00: Sun.; 01: Mon.; 02: Tues.;

03: Wed.; 04: Thurs.; 05: Fri.; 06: Sat.)

Note The accuracy of the internal clock depends on the ambient temperature. Refer

to the following table.

Ambient temperature Error per month

55C

–3 to 0 min

25C

±1 min

C

–2 to 0 min

CPU Bus Link Area Section 3-5

!

50

Data Link Area The CPU Bus Link Area is disabled by default in the PC Setup and must be

enabled with the CVSS/SSS in order to use the Data Link Area.
The 120 words of CPU Bus Link Area from G008 to G127 are used for outputs

from the CPU to BASIC Units. The 128 words from G128 to G255 are used for
outputs from the BASIC Units. These are divided into 16 groups of 8 words each
and allocated to CPU Bus Units according their unit number settings as shown in
the following tables. All words not output by a particular BASIC Unit are read by it
as inputs from the other BASIC Units.

Unit # 0 1 2 3 4 5 6 7

Words G128

to

G135

G136

to

G143

G144

to

G151

G152

to

G159

G160

to

G167

G168

to

G175

G176

to

G183

G184

to

G191

Unit # 8 9 10 11 12 13 14 15

Words G192

to

G199

G200

to

G207

G208

to

G215

G216

to

G223

G224

to

G231

G232

to

G239

G240

to

G247

G248

to

G255

When the PC Setup have been changed to enable the CPU Bus Link, bit 15 of
the first word allocated to each Unit (e.g., bit G12815 for Unit #0) will be OFF
during data reception.

3-6 Auxiliary Area

The Auxiliary Area contains flags and control bits used for monitoring and
controlling PC operation, accessing clock pulses, and signalling errors. Auxil­iary Area word addresses range from A000 through A511; bit addresses,
from A00000 through A51115. Addresses A000 through A255 are read/write,
but addresses A256 through A511 are read only.

The Force Set/Reset operations from the CVSS/SSS behave like the
SET(016) and RSET(017) instructions when applied to words A000 through
A255.

Unused Auxiliary Area words and bits cannot be used as work words and
bits.

Caution The Auxiliary Area contains two sections. The section between A000 and A255

can be read from or written to from the user program. The section between A256
and A511, however, can be read from to access the data provided there, but it
cannot be written to from the user program.

The following table lists the functions of Auxiliary Area flags and control bits.
Most of these bits are described in more detail following the table. Descrip­tions are in order by address, except that some bits/words with related func­tions are explained together.

Word(s) Bit(s) Function

A000 00 to 10 Not used.

11 Restart Continuation Bit
12 IOM Hold Bit
13 Forced Status Hold Bit
14 Error Log Reset Bit

15 Output OFF Bit
A001 00 to 15 CPU Bus Unit Restart Bits
A002 to A004 00 to 15 Not used.
A005 00 to 07 SYSMAC BUS Error Check Bits

08 to 15 Not used.

Auxiliary Area Section 3-6

51

Word(s) FunctionBit(s)

A006 00 to 15 Not used.
A007 00 to 15 Momentary Power Interruption Time (BCD)
A008 00 to 06 Not used.

07 Stop Monitor Flag

08 Execution Time Measured Flag

09 Differentiate Monitor Completed Flag

10 Stop Monitor Completed Flag

11 Trace Trigger Monitor Flag

12 Trace Completed Flag

13 Trace Busy Flag

14 Trace Start Bit

15 Sampling Start Bit
A009 00 to 15 Not used.
A010 to A011 00 to 15 Startup Time (BCD)
A012 to A013 00 to 15 Power Interruption Time (BCD)
A014 00 to 15 Number of Power Interruptions (BCD)
A015 00 to 15 CPU Bus Service Disable Bits
A016 00 to 15 Not used.
A017 00 to 02 Not used.

03 Host Link Service Disable Bit

04 Peripheral Service Disable Bit

05 I/O Refresh Disable Bit

06 to 15 Not used.
A018 to A089 00 to 15 Not used.
A090 to A097 00 to 15 Reserved for system use
A098 00 FPD(177) Teaching Bit

01 to 15 Not used.
A099 00 to 07 Message #0 to #7 Flags

08 to 15 Not used.
A100 to A199 00 to 15

Error Log Area (20 × 5 words)

A200 to A203 00 to 15 Macro area inputs
A204 to A207 00 to 15 Macro area outputs
A208 to A255 00 to 15 Not used.
A20 to A299 00 to 15 Not used.
A300 00 to 15 Error Log Pointer (binary)
A301 00 to 15 Not used.
A302 00 to 15 CPU Bus Unit Initializing Flags
A303 to A305 00 to 15 Not used.
A306 00 Start Input Wait Flag

01 I/O Verification Error Wait Flag

02 SYSMAC BUS Terminator Wait Flag

03 CPU Bus Unit Initializing Wait Flag

04 to 07 Not used.

08 to 11 Connected Device Code 2: GPC

3: Programming Console
12 to 14 Not used.
15 Peripheral Connected Flag

A307 00 to 07 Peripheral Connected Flags for RT #0 to RT #7 of

RM/2 #0

Auxiliary Area Section 3-6

52

Word(s) FunctionBit(s)

08 to 15 Peripheral Connected Flags for RT #0 to RT #7 of

RM/2 #1

A308 00 to 07 Peripheral Connected Flags for RT #0 to RT #7 of

RM/2 #2

08 to 15 Peripheral Connected Flags for RT #0 to RT #7 of

RM/2 #3
A309 00 to 15 Peripheral Device Cycle Time (binary)
A310 to A325 00 to 15 CPU Bus Unit Service Interval (binary)
A326 to A342 00 to 15 Not used.
A343 00 to 02 Memory Card Type

03 to 06 Not used.
07 Memory Card Format Error Flag
08 Memory Card Transfer Error Flag
09 Memory Card Write Error Flag
10 Memory Card Read Error Flag
11 FIle Missing Flag
12 Memory Card Write Flag
13 Memory Card Instruction Flag
14 Accessing Memory Card Flag

15 Memory Card Protected Flag
A344 to 345 00 to 15 Not used.
A346 00 to 15 Number of Words Remaining to transfer to memory

card for a file read/write instruction (BCD)
A347 to A399 00 to 15 Not used.
A400 00 to 15 Error Code
A401 00 to 04 Not used.

06 FALS Error Flag
07 SFC Fatal Error Flag
08 Cycle Time Too Long Flag
09 Program Error Flag
10 I/O Setting Error Flag
11 Too Many I/O Points Flag
12 CPU Bus Error Flag
13 Duplication Error Flag
14 I/O Bus Error Flag
15 Memory Error Flag

A402 00 to 01 Not used.

02 Power Interruption Flag
03 CPU Bus Unit Setting Error Flag
04 Battery Low Flag
05 SYSMAC BUS Error Flag
06 SYSMAC BUS/2 Error Flag
07 CPU Bus Unit Error Flag
08 Not used.
09 I/O Verification Error Flag
10 Not used.
11 SFC Non-fatal Error Flag
12 Indirect DM Error Flag
13 Jump Error Flag
14 Not used.
15 FAL Error Flag

Auxiliary Area Section 3-6

53

Word(s) FunctionBit(s)

A403 00 to 08 Memory Error Area Location

09 Memory Card Startup Transfer Error Flag
10 to 15 Not used.

A404 00 to 07 I/O Bus Error Slot Number (BCD)

08 to 15 I/O Bus Error Rack Number (BCD)
A405 00 to 15 CPU Bus Unit Error Unit Number
A406 00 to 15 Not used.
A407 00 to 15 Total I/O Words on CPU and Expansion Racks

(BCD)
A408 00 to 15 Total SYSMAC BUS/2 I/O Words (BCD)
A409 00 to 07 Duplicate Rack Number

08 to 14 Not used

15 Duplicate System Parameter Words Flag
A410 00 to 15 CPU Bus Unit Duplicate Number
A411 to A413 00 to 15 Not used.
A414 00 to 15 SFC Fatal Error Code
A415 to A417 00 to 15 Not used.
A418 00 to 15 SFC Non-fatal Error Code
A419 00 to 07 CPU-recognized Rack Numbers

08 to 15 Not used.
A420 to A421 00 to 15 Not used.
A422 00 to 15 CPU Bus Unit Error Unit Number
A423 00 to 13 Not used.

14 CPU Bus Unit Number Setting Error Flag

15 CPU Bus Link Error Flag
A424 00 to 03 SYSMAC BUS/2 Error Master Number

04 to 15 Not used.
A425 00 to 07 SYSMAC BUS Error Master Number

08 to 15 Not used.
A426 00 to 13 Not used

14 Memory Card Battery Low Flag

15 PC Battery Low Flag
A427 00 to 15 CPU Bus Unit Setting Error Unit Number
A428 to A429 00 to 15 Not used.
A430 to A461 00 to 15 Executed FAL Number
A462 to A463 00 to 15 Maximum Cycle Time (BCD, 8 digits)
A464 to A465 00 to 15 Present Cycle Time (BCD, 8 digits)
A466 to A469 00 to 15 Not used.
A470 to A477 00 to 15 SYSMAC BUS Error Codes:

RM # 0 (A470) RM #1 (A471)
RM # 2 (A472) RM #3 (A473)
RM # 4 (A474) RM #5 (A475)

RM # 6 (A476) RM #7 (A477)
A478 00 to 15 Total SYSMAC BUS I/O Words (BCD)
A479 00 to 15 Not used.
A480 to A499 00 to 15 SYSMAC BUS/2 Error Unit Number:

RM # 0 (A480 to A484) RM #1 (A485 to A489)

RM # 2 (A490 to A494) RM #3 (A495 to A499)

Auxiliary Area Section 3-6

54

Word(s) FunctionBit(s)

A500 00 to 02 Not used.

03 Instruction Execution Error Flag
04 Carry Flag
05 Greater Than Flag
06 Equals Flag
07 Less Than Flag
08 Negative Flag
09 Overflow Flag
10 Underflow Flag
11 Not used.
12 First Cycle Flag when one-step operation is started

with STEP instruction

13 Always ON Flag
14 Always OFF Flag
15 First Cycle Flag

A501 00 0.1-s Clock Pulse

01 0.2-s Clock Pulse
02 1.0-s Clock Pulse
03 0.02-s Clock Pulse
04 to 15 Not used.

A502 00 to 07 Port #0 to #7 Enabled Flags

08 to 15 Port #0 to #7 Execute Error Flags
A503 to A510 00 to 15 Port #0 to #7 Completion Codes
A511 00 to 04 Current EM Bank (0 to 7)

05 to 14 Not used.

15 EM Installed Flag

Note Do not use A50013 (Always ON Flag), A50014 (Always OFF Flag), or A50015

(First Cycle Flag) to control execution of differentiated instructions. The instruc­tions will never be executed.

3-6-1 Restart Continuation Bit

Bit A00011 can be turned ON to make the PC automatically resume opera­tion from the point that operation stopped due to a power interruption. If bit
A00011 is OFF, the PC will enter the start-up mode set in the PC Setup and
will begin operation from the first step if the start-up mode is RUN or MON­ITOR mode.

When the Restart Continuation Bit is turned ON, several parameters in the PC
Setup must also be made for the PC to restart properly. Refer to

Section 7 PC

Setup

for more details.

3-6-2 IOM Hold Bit

Bit A00012 can be turned ON to preserve the status of the CIO Area, Transi­tion Flags, Timer Flags, Timer PVs, index registers, data registers, and the
Current EM Bank Number when shifting from PROGRAM or DEBUG to
MONITOR or RUN mode or when shifting from MONITOR or RUN mode to
PROGRAM or DEBUG mode. (I/O Memory includes the CIO Area, TR Area,
CPU Bus Link Area, Auxiliary Area, Transition Flags, Step Flags, Timer
Completion Flags, and Counter Completion Flags.)

When the IOM Hold Bit is OFF, the CIO Area, Transition Flags, Timer Flags, Tim­er PVs, index registers, data registers, and the Current EM Bank Number are
cleared when switching between these modes.

Auxiliary Area Section 3-6

55

If the IOM Hold Bit is ON, and the status of the IOM Hold Bit itself is pre­served in the PC Setup (Setting B, IOM Hold Bit status), then I/O Memory is
also preserved when the PC is turned ON or power is interrupted.

3-6-3 Forced Status Hold Bit

Bit A00013 can be turned ON to preserve the status of bits that have been
force-set or force-reset when switching modes (except RUN mode). When
the Forced Status Hold Bit is OFF, bits that have been force-set or force-re­set will return to default status when switching between modes.

If the Forced Status Hold Bit is ON, and the status of the Forced Status Hold
Bit itself is preserved in the PC Setup (Setting B, Forced Status Hold Bit sta­tus), then the status of bits that have been force-set or force-reset is also pre­served when the PC is turned ON or power is interrupted.

In any case, bits that have been force-set or force-reset will return to default sta­tus when switching to RUN mode.

3-6-4 Error Log Reset Bit

Bit A00014 can be turned ON to clear the contents of the Error Log Area
(words A100 to A199), and reset the Error Record Pointer to 0. The Error Log
Reset Bit is automatically turned OFF after the Error Log Area is cleared.

3-6-5 Output OFF Bit

Bit A00015 can be turned ON to turn OFF all outputs from the PC. The OUT
INH. indicator on the front panel of the CPU will light. The Output OFF Bit is
turned ON automatically when Restart Continuation (bit A00011) has taken
place. It is therefore necessary to include a step in the program to turn this bit
OFF to continue operation after a power interruption. Refer to

6-1 PC Opera-

tion

for details.

3-6-6 CPU Bus Unit Restart Bits

Bits A00100 through A00115 can be turned ON to reset CPU Bus Units number
#0 through #15, respectively. The Restart Bits are turned OFF automatically
when restarting is completed.

Do not turn these bits ON and OFF in the program; manipulate them from the
CVSS/SSS.

3-6-7 SYSMAC BUS Error Check Bits

Bits A00500 through A00507 can be turned ON to read out the error codes
(stored in words A470 through A477) for Masters numbered #0 through #7, re­spectively. The Error Check Bits are turned OFF automatically after the informa­tion has been read out. Refer to

3-6-35 SYSMAC BUS Error Flag

for more de-

tails.

3-6-8 Momentary Power Interruption Time

Word A007 contains the duration of the most recent power interruption. The
time is recorded in 4-digit BCD in milliseconds (0000 ms to 9999 ms), as
shown in the following table.

Bits

15 to 12 11 to 08 07 to 04 03 to 00

10

3

10

2

10

1

10

0

Auxiliary Area Section 3-6

56

The power interruption time is output to words A012 and A013, and the number
of power interruptions is output to word A014.

3-6-9 CVSS/SSS Flags

Word A008 contains flags that indicate the status of commands and instructions
performed with the CVSS/SSS.

Bit A00807 is turned ON when the Stop Monitor is used from the CVSS/SSS,
and is turned OFF when it is completed.

Bit A00808 is turned ON when the execution time has been measured with
MARK(174) instructions with the CVSS/SSS.

Bit A00809 is turned ON when the differentiate monitor condition has been
established with the CVSS/SSS.

Bit A00810 is turned ON when the Stop Monitor operation has been com­pleted with the CVSS/SSS.

Bit A00811 is turned ON when one of the trigger conditions has been estab­lished during execution of a Data or Program Trace with the CVSS/SSS.

Bit A00812 is turned ON upon when the sampling of a region of trace
memory has been completed during execution of a Data or Program Trace
with the CVSS/SSS.

Bit A00813 is turned ON when a Data or Program Trace is executed with the
CVSS/SSS, and is turned OFF when it is completed.

The Trigger conditions are established when bit A00814 is turned ON by one
of trigger conditions of a Data or Program Trace of the CVSS/SSS.

Bit A00815 is turned ON to start a Data Trace.

3-6-10Start-up Time

Words A010 and A011 contain the start-up time, in BCD format, as shown in the
following table. The start-up time is updated every time the power is turned ON.

Word Bits Contents Possible values

A010 00 to 07 Seconds 00 to 99

08 to 15 Minutes 00 to 59

A011 00 to 07 Hours 00 to 23 (24-hour system)

08 to 15 Day of month 01 to 31 (adjusted by month and for leap year)

3-6-11Power Interruption Time

Words A012 and A013 contain, in BCD format, the time at which power was in­terrupted, as shown in the following table. The power interruption time is up­dated every time the power is interrupted.

Word Bits Contents Possible values

A012 00 to 07 Seconds 00 to 99

08 to 15 Minutes 00 to 59

A013 00 to 07 Hours 00 to 23 (24-hour system)

08 to 15 Day of month 01 to 31 (adjusted by month and for leap year)

Stop Monitor Flag (A00807)

Execution Time Measured
Flag (A00808)

Differentiate Monitor
Completed Flag (A00809)

Stop Monitor Completed
Flag (A00810)

Trace Trigger Monitor Flag
(A00811)

Trace Completed Flag
(A00812)

Trace Busy Flag (A00813)

Trace Start Bit (A00814)

Sampling Start Bit (A00815)

Auxiliary Area Section 3-6

57

3-6-12Number of Power Interruptions

Word A014 contains the number of times that power has been interrupted since
the PC was first turned on. The number is in BCD, and can be reset by writing
#0000 to word A014.

3-6-13Service Disable Bits

Words A015 and A017 contain control bits that disable I/O servicing to certain
Units and periodic refreshing.Turn these bits ON and OFF in the program. The
service disable bits are automatically turned OFF when power is turned on or PC
operation is stopped.

Bits A01500 through A01515 can be turned ON to stop service to CPU Bus
Units numbered #0 through #15, respectively. Turn the appropriate bit OFF
again to resume service to the CPU Bus Unit.

Bit A01703 can be turned ON to stop Host Link System servicing. Turn OFF
again to resume service to the Host Link System.

Bit A01704 can be turned ON to stop service to Peripheral Devices. Turn
OFF again to resume service to Peripheral Devices.

Bit A01705 can be turned ON to stop periodic and SYSMAC BUS refreshing.
Turn OFF again to resume periodic and SYSMAC BUS refreshing.

3-6-14Message Flags

When the MESSAGE instruction (MSG(195)) is executed, the bit in A099 corre­sponding to the message number is turned ON. Bits 00 through 07 correspond
to message numbers 0 through 7, respectively.

3-6-15Error Log Area

Words A100 through A199 contain up to 20 records that show the nature, time,
and date of errors that have occurred in the PC. The Error Log Area will store
system-generated or FAL(006)/FALS(007)-generated error codes. Refer to

Section 8 Error Processing

for details on error codes.

The Error Log Area can be moved to the DM or EM Areas and its size can be
increased to store up to 2,047 records with the PC Setup.

With the default PC Setup, error records occupy five words each stored be­tween words A100 and A199. The last record that was stored can be ob­tained via the content of word A300 (Error Record Pointer). The record num­ber, Auxiliary Area words, and pointer value for each of the twenty records
are as follows:

Record Addresses Pointer value*

None N.A. 0000
1 A100 to A104 0001
2 A105 to A109 0002
3 A110 to A114 0003
4 A115 to A119 0004
5 A120 to A124 0005
6 A125 to A129 0006
7 A130 to A134 0007
8 A135 to A139 0008
9 A140 to A144 0009

CPU Service Disable Bits

Host Link Service Disable
Bit

Peripheral Service Disable
Bit

I/O Refresh Disable Bit

Area Structure

Auxiliary Area Section 3-6

58

Record Pointer value*Addresses

10 A145 to A149 000A
11 A150 to A154 000B
12 A155 to A159 000C
13 A160 to A164 000D
14 A165 to A169 000E
15 A170 to A174 000F
16 A175 to A179 0010
17 A180 to A184 0011
18 A185 to A189 0012
19 A190 to A194 0013
20 A195 to A199 0014

*The pointer value is in word A300, which is in the read-only area (words A256 to A511).

Although each of them contains a different record, the structure of each re­cord is the same: the first word contains the error code; the second word, the
error contents, and the third, fourth, and fifth words, the time, day, and date.
The error code will be either one generated by the system or by
FAL(006)/FALS(007); the time and date will be the time and date from the
Calendar/Clock Area, words G001 to G004. This structure is shown below.

Word Bit Content

First 00 to 15 Error code
Second 00 to 15 Error contents
Third 00 to 07 Seconds

08 to 15 Minutes

Fourth 00 to 07 Hours

08 to 15 Day of month

Fifth 00 to 07 Month

08 to 15 Year

Operation When the first error code is generated, the relevant data will be placed in the

error record after the one indicated by the Log Record Pointer (initially this
will be record 1) and the Pointer will be incremented. Any other error codes
generated thereafter will be placed in consecutive records until the last one is
used.

If there are words allocated for n errors and n errors occur, the next error will
be written into the last position, n, the contents of previous error will be
moved to record n–1, and so on until the contents of record 1 is moved off
the end and lost, i.e., the area functions like a shift register that moves data
in units of error records (5 words). The Record Pointer will remain set to n
(binary).

The Error Log Area can be reset by turning ON bit A00014 (Error Log Reset
Bit). When this is done, the Record Pointer will be reset to 0000, the Error
Log Area will be cleared, and any further error codes will be recorded from
the beginning of the Error Log Area.

3-6-16CPU Bus Unit Initializing Flags

Bits A30200 through A30215 turn ON while the corresponding CPU Bus Units
(Units #0 through #15, respectively) are initializing.

3-6-17Wait Flags

Bit A30600 is ON when the CPU Rack Power Supply Unit start input termi­nals are OFF.

Start-up Wait Flag (A30600)

Auxiliary Area Section 3-6

59

Bit A30601 is ON when the PC is not running because an I/O Verification Er­ror has occurred, and the PC Setup are set so the PC does not run when an
I/O Verification Error occurs. The PC Setup can be changed to enable opera­tion during I/O Verification Errors. Refer to “Comparison error process” in the
PC Setup.

Bit A30602 is ON when the PC is not running because there is a terminator
missing in the SYSMAC BUS System.

Bit A30603 is ON when the PC is not running because a CPU Bus Unit is
initializing, or a terminator missing in the SYSMAC BUS/2 System.

3-6-18Peripheral Device Flags

Bits A30608 through A30611 contain a binary code that identifies the type of
Peripheral Device (0: FIT10; 1: FIT20; 2: GPC; 3: Programming Console)
connected to the CPU, the Expansion CPU, or an Expansion I/O Rack.

Bit A30615 is ON when a Peripheral Device is connected to the CPU, the
Expansion CPU, or an Expansion I/O Rack.

Bits A30700 through A30815 are turned ON when a Peripheral Device is
connected to the corresponding Slave Rack, as shown in the following table.

Word Bits

00 to 07 08 to 15

A307 Racks #0 to #7 on Master #0 Racks #0 to #7 on Master #1
A308 Racks #0 to #7 on Master #2 Racks #0 to #7 on Master #3

Word A309 contains the cycle time in ms (in binary) required to service Pe­ripheral Devices, Host Link, and CPU Bus Units. Refer to

6-2 Cycle Time

for

details.

3-6-19CPU Bus Unit Service Interval

Words A310 through A325 contain the interval in ms (binary) between CPU Bus
Unit services for Units #0 through #15, respectively. Measuring the service inter­val can be enabled or disabled in the PC Setup.

3-6-20Memory Card Flags

The binary number stored in A34300 to A34303 indicates the type of Memory
Card, if any, installed in the Memory Card Drive. (0: None, 1: RAM,
2: EPROM, 3: EEPROM)

Bit A34307 is turned ON when the Memory Card is not formatted or a format­ting error has occurred.

Bit A34308 is turned ON when an error occurs while writing to the Memory
Card.

Bit A34309 is turned ON when the Memory Card cannot be written to be­cause the card is write-protected, EPROM, EEPROM, data is beyond the
capacity of the card, or there are too many files.

Bit A34310 is turned ON when the specified file is damaged and cannot be
read.

I/O Verification Error Wait
Flag (A30601)

SYSMAC BUS Terminator
Wait Flag (A30602)

CPU Bus Unit Initializing
Wait Flag (A30603)

Connected Device Code
(A30608 to A30611)

Peripheral Connected Flag
(A30615)

SYSMAC BUS/2 Peripheral
Flags (A307 and A308)

Peripheral Device Cycle
Time (A309)

Memory Card Type
(A34300 to A34303)

Memory Card Format Error
Flag (A34307)

Memory Card Transfer Error
Flag (A34308)

Memory Card Write Error
Flag (A34309)

Memory Card Read Error
Flag (A34310)

Auxiliary Area Section 3-6

60

Bit A34311 is turned ON when the specified file is not on the installed card or
no card is installed.

Bit A34312 is turned ON when the Memory Card is being written to from the
program (FILW(181)).

Bit A34313 is turned ON when an instruction affecting Memory Card files
(FILR(180), FILW(181), FILP(182), or FLSP(183)) is being executed.

Bit A34314 is turned ON when the Memory Card is being accessed.

Bit A34315 is turned ON when the Memory Card is write-protected by the
write-protect switch on the card.

Word A346 contains the number of words left to transfer to or from the
Memory Card (FILW(181) or FILR(180)). When either instruction is first
executed, the number of words in the file is placed in word A346 and as data
is transferred, the number of words transferred is subtracted from this num­ber.

The number of words to transfer is recorded in 4-digit BCD.

A346 bits

15 to 12 11 to 08 07 to 04 03 to 00

10

3

10

2

10

1

10

0

3-6-21Error Code

When an error or alarm occurs, the error code is written to A400. If two errors
occur simultaneously, the more serious error, with a higher error code, is re­corded. Refer to

Section 8 Error Processing

for details on error codes.

3-6-22FALS Flag

Bit A40106 is turned ON when the SEVERE ALARM FAILURE instruction
(FALS(007)) is executed. The FAL number is written to word A400.

3-6-23SFC Fatal Error Flag and Error Code

Bit A40107 is turned ON if an error that stops operation occurs while the SFC
program is being executed. The SFC Fatal Error Code is written in BCD to word
A414. Refer to

Section 8 Error Processing

for details on the error codes.

3-6-24Cycle Time Too Long Flag

Bit A40108 is turned ON if the cycle time exceeds the cycle time monitoring
time (i.e., the maximum cycle time) set in the PC Setup.

3-6-25Program Error Flag

Bit A40109 is turned ON if there is a program syntax error (including no
END(001) instruction).

3-6-26I/O Setting Error Flag

Bit A40110 is turned ON if the I/O designation of a slot has changed, e.g., an
Input Unit has been installed in an Output Unit’s slot, or vice versa.

3-6-27Too Many I/O Points Flag

Bit A40111 is turned ON if the total number of I/O points being used exceeds the
maximum for the PC. The total number of I/O points being used on CPU and Ex-

File Missing Flag (A34311)

Memory Card Write Flag
(A34312)

Memory Card Instruction
Flag (A34313)

Accessing Memory Card
Flag (A34314)

Memory Card Protected
Flag (A34315)

Number of Words to
Transfer (A346)

Auxiliary Area Section 3-6

61

pansion Racks is written to word A407; in the SYSMAC BUS/2 system, to word
A408; and in the SYSMAC BUS system, to word A478.

3-6-28CPU Bus Error and Unit Flags

Bit A40112 is turned ON when an error occurs during the transmission of data
between the CPU and CPU Bus Units, or a WDT (watchdog timer) error occurs
in a CPU Bus Unit. The unit number of the CPU Bus Unit involved is contained in
word A405.

Bits A40500 through A40515 correspond to CPU Bus Units #0 through #15, re­spectively. When a CPU Bus Error occurs, the bit corresponding to the unit num­ber of the CPU Bus Unit involved is turned ON.

3-6-29Duplication Error Flag and Duplicate Rack/CPU Bus Unit Numbers

Bit A401 13 is turned ON when two Racks are assigned the same rack number,
two CPU Bus Units are assigned the same unit number, or the same words are
allocated to more than one Rack or Unit in the PC Setup. The duplicate Expan­sion I/O Rack number is written to word A409, and the duplicate CPU Bus Unit
number is written to word A410.

Bits A40900 through A40907 correspond to Racks #0 through #7, respectively.
When two Racks have the same rack number, the bits corresponding to the rack
numbers involved are turned ON. Bit A40915 is also turned ON to indicate that
the same words are allocated to more than one Rack or Unit in the PC Setup.

Bits A41000 through A41015 correspond to CPU Bus Units #0 through #15, re­spectively. When two CPU Bus Units have the same unit number, the bits corre­sponding to the unit numbers of the CPU Bus Units involved are turned ON.

3-6-30I/O Bus Error Flag and I/O Bus Error Slot/Rack Numbers

Bit A40114 is turned ON when an error occurs during the transmission of data
between the CPU and I/O Units through the I/O bus, or a terminator is not
installed correctly. The rack/slot number of the Unit involved is written to word
A404.

Bits A40400 through A40407 contain the slot number, in BCD, of the I/O Unit
where the error occurred. If the error did not occur with an I/O Unit, then these
bits contain #0F. Bits A40408 through A40415 contain the rack number, in BCD,
of the Rack where the error occurred.

If the error occurred because of a terminator setting, word A404 will contain
#0E0F for line 0 (IOC right connector), or #0F0F for line 1 (IOC left connector).

3-6-31Memory Error Flag

Bit A40115 is turned ON when an error occurs in memory. The memory area in­volved is written to word A403.

3-6-32Power Interruption Flag

Bit A40202 is turned ON when power is momentarily interrupted if a momentary
power interruption is set as an error in the PC Setup (see “Error on power of f” in
the PC Setup). The time and date of the most recent power interruption is written
to words A012 and A013, and the number of power interruptions is written to
word A014.

3-6-33CPU Bus Unit Setting Error Flag and Unit Number

Bit A40203 is turned ON when the CPU Bus Units actually installed differ from
the Units registered in the I/O table. The unit number of the CPU Bus Unit in­volved is written to word A427.

Bits A42700 through A42715 correspond to CPU Bus Units #0 through #15, re­spectively. When a error occurs, the bit corresponding to the unit number of the
CPU Bus Unit involved is turned ON.

Auxiliary Area Section 3-6

62

3-6-34Battery Low Flags

Bit A40204 is turned ON if the voltage of the CPU or Memory Card battery drops.
If the problem has occurred with the Memory Card battery, bit A42614 will be
turned ON, and if the problem has occurred with the CPU battery, bit A42615 will
be turned ON.

3-6-35SYSMAC BUS Error Flag, Check Bits, and Master/Unit Numbers

Bit A40205 is turned ON when an error occurs during the transmission of data in
the SYSMAC BUS system. The number of the Master involved is written to word
A425, and information about the Unit(s) involved is written to words A470
through A477.

Bits A42500 through A42507 correspond to Masters #0 through #7, respective­ly. When a error occurs, the bit corresponding to the number of the Master in­volved is turned ON.

Words A470 through A477 are used to indicate which Unit is involved in the
error on Masters #0 through #7, respectively. The function of each bit is de­scribed below. Refer to the

Optical

and

Wired Remote I/O System Manuals

for details.

Not used.

Bit 03 turns ON when an error has occurred in remote I/O.

If the content of bits 12 through 15 is B, an error has occurred in a Remote
I/O Master or Slave Unit, and the content of bits 08 through 11 will indicate
the number of the Master of the Remote I/O Subsystem involved. These
numbers are assigned to Masters in the order that they are mounted to the
CPU and Expansion Racks. If the error is in the Master, the value of bits 4 to
7 will be 8. If the error is in a Slave, bits 4 to 7 will contain the unit number of
the Slave where the error occurred.

If the content of bits 12 through 15 is other than B, an error has occurred in
an Optical I/O Unit, I/O Link Unit, or I/O Terminal. Here, bits 08 through 15
will provide the word address (#00 to #31) that has been set on the Unit.

When this Unit is an Optical I/O Unit, bit 04 will be ON if the Unit is assigned
leftmost bits (08 through 15), and OFF if it is assigned rightmost bits (00
through 07).

If there are errors in more than one Unit for a single Master, words A470
through A477 will contain error information for only the first one. Data for the
remaining Units will be stored in memory and can be accessed by turning ON
the Error Check Bit for that Master. Bits A00500 through A00507 are the Er­ror Check Bits for Masters #0 through #7, respectively. Error Check Bits are
automatically turned OFF when data has been accessed. Write down the
data for the first error if required before using the Error Check Bit; previous
data will be cleared when data for the next error is displayed.

3-6-36SYSMAC BUS/2 Error Flag and Master/Unit Numbers

Bit A40206 is turned ON when an error occurs during the transmission of data in
the SYSMAC BUS/2 System. The number of the Master involved is written to
word A424, and information about the Slave Unit(s) involved is written to words
A480 through A499.

Bits A42400 through A42403 are turned ON when the error involves Masters #0
through #3, respectively.

Bits 00 to 02

Bit 03 – Remote I/O Error
Flag

Bits 04 to 15

Error Check Bits
(A00500 to A00507)

Auxiliary Area Section 3-6

63

Information identifying the Slave Unit(s) involved is contained in words A480
through A499, which are divided into four groups of five words, one group for
each Master , as shown below.

Words Master number

A480 to A484 0
A485 to A489 1
A490 to A494 2
A495 to A499 3

Bits are turned ON to indicate which of the Slaves connected to the Master
was involved in the error, as shown below.

Word Bits Slave

First 00 to 15 Group-1 Slaves #0 to #15
Second 00 to 15 Group-1 Slaves #16 to #31
Third 00 to 15 Group-2 Slaves #0 to #15
Fourth 00 to 07 Slave Racks #0 to #7

(Group-3 Slaves)

08 to 15 Not used.

Fifth 00 to 15 Not used

3-6-37CPU Bus Unit Error Flag and Unit Numbers

Bit A40207 is turned ON when a parity error occurs during the transmission of
data between the CPU and CPU Bus Units. The unit number of the CPU Bus Unit
involved is written to word A422.

Bits A42200 through A42215 correspond to CPU Bus Units #0 through #15, re­spectively. When a CPU Bus Unit Error occurs, the bit corresponding to the unit
number of the CPU Bus Unit involved is turned ON.

3-6-38I/O Verification Error Flag

Bit A40209 is turned ON when the Units mounted in the system disagree with
the I/O table registered in the CPU. To ensure proper operation, PC opera­tion should be stopped, Units checked, and the I/O table corrected whenever
this flag goes ON.

3-6-39SFC Non-fatal Error Flag and Error Code

Bit A40211 is turned ON if an error that does not stop operation occurs while the
SFC program is being executed. The error code is written to word A418. Refer to

Section 8 Error Processing

for details on the error codes.

3-6-40Indirect DM BCD Error Flag

Bit A40212 is turned ON if the content of an indirectly addressed DM word is not
BCD when BCD is specified in the PC Setup.

The contents of indirectly addressed DM words can be set to either binary or
BCD with the PC Setup. Binary addresses will access memory according to PC
memory addresses. BCD will access other DM words according to DM Area ad­dresses. If binary addresses are used, this flag will not operate.

3-6-41Jump Error Flag

Bit A40213 is turned ON if there is no destination for a JMP(004) instruction.

3-6-42FAL Flag and FAL Number

Bit A40215 is turned ON when the FAL(006) instruction is executed. The FAL
number is then written to words A430 to A461. Bits from A43001 to A46115 cor­respond consecutively to FAL numbers 001 to 511

Auxiliary Area Section 3-6

64

3-6-43Memory Error Area Location

Bits A40300 to A40308 are turned ON to indicate the memory area in which a
memory error has occurred. The bits correspond to memory areas as follows:

00: Program Memory 05: I/O Table
01: Memory Card 06: System Memory
02: I/O Memory 07: Routing Tables
03: EM 08: CPU Bus Unit Software Switches
04: PC Setup

3-6-44Memory Card Start-up Transfer Error Flag

Bit A40309 is turned ON when an error occurs during the transmission of the
program from the Memory Card when power is turned ON. An error can occur
because the AUTOEXEC file is missing, the Memory Card is not installed, or the
System Protect setting is ON.

3-6-45CPU-recognized Rack Numbers

Bits A41900 through A41907 are turned ON when Expansion Racks #0 through
#7, respectively, are recognized by the CPU.

3-6-46CPU Bus Unit Number Setting Error Flag

Bit A42314 is turned ON when a CPU Bus Unit is not set to an acceptable unit
number (0 to 15).

3-6-47CPU Bus Link Error Flag

Bit A42315 is turned ON when a parity error occurs with CPU bus links.

3-6-48Maximum Cycle Time

Words A462 and A463 contain the maximum cycle time that has occurred
since operation was started. If the maximum cycle time is exceeded, howev­er, the previous maximum cycle time will remain in words A462 and A463.
The time is recorded in 8-digit BCD in tenths of milliseconds (0000000.0 ms
to 9999999.9 ms), as shown in the following table.

Word Bits

15 to 12 11 to 08 07 to 04 03 to 00

A463 10

6

10

5

10

4

10

3

A462 10

2

10

1

10

0

10

–1

3-6-49Present Cycle Time

Words A464 and A465 contain the present cycle time unless the maximum
cycle time is exceeded, in which case the previous cycle time will remain.
The time is recorded in 8-digit BCD in tenths of milliseconds (0000000.0 ms
to 9999999.9 ms), as shown in the following table.

Word Bits

15 to 12 11 to 08 07 to 04 03 to 00

A465 10

6

10

5

10

4

10

3

A464 10

2

10

1

10

0

10

–1

3-6-50 Instruction Execution Error Flag, ER

Bit A50003 is turned ON if an attempt is made to execute an instruction with
incorrect operand data. Common causes of an instruction error are non-BCD
operand data when BCD data is required, or an indirectly addressed DM

Auxiliary Area Section 3-6

!

!

65

word that is non-existent. When the ER Flag is ON, the current instruction
will not be executed.

3-6-51 Arithmetic Flags

The following flags are used in data shifting, arithmetic calculation, and com­parison instructions. They are generally referred to only by their two-letter
abbreviations.

Caution These flags are all reset when the END instruction is executed, and therefore

cannot be monitored from a Peripheral Device.

Refer to

5-14 Shift Instructions, 5-16 Comparison Instructions, 5-18 BCD Cal-

culation Instructions

, and

5-19 Binary Calculation Instructions

for details.

Bit A50004 is turned ON when there is a carry in the result of an arithmetic
operation or when a rotate or shift instruction moves a “1” into CY. The con­tent of CY is also used in some arithmetic operations, e.g., it is added or sub­tracted along with other operands. This flag can be set and cleared from the
program using the SET CARRY and CLEAR CARRY instructions. This Flag
is also used by the I/O READ and I/O WRITE instructions. Refer to page 405
for details.

Bit A50005 is turned ON when the result of a comparison shows the first of
two operands to be greater than the second.

Bit A50006 is turned ON when the result of a comparison shows two oper­ands to be equal or when the result of an arithmetic operation is zero.

Bit A50007 is turned ON when the result of a comparison shows the first of
two operands to be less than the second.

Bit A50008 is turned ON when the highest bit in the result of a calculation is
ON.

Bit A50009 is turned ON when the absolute value of the result is greater than
the maximum value that can be expressed.

Bit A50010 is turned ON when absolute value of the result is less than the
minimum value that can be expressed.

Caution The previous seven flags are cleared when END(001) is is executed.

3-6-52 Step Flag

Bit A50012 is turned ON for one cycle when step execution is started with the
STEP(008) instruction.

3-6-53 First Cycle Flag

When ladder-only programming is used, bit A50015 turns ON when PC op­eration begins and then turns OFF after one cycle of the program. When
SFC programming is used, A50015 turns ON for one cycle at the beginning
of action program execution. A50015 also turns ON at the beginning of
scheduled interrupt execution. The First Cycle Flag is useful in initializing
counter values and other operations. An example of this is provided in

5-13

Timer and Counter Instructions

.

Carry Flag, CY

Greater Than Flag, GR

Equals Flag, EQ

Less Than Flag, LE

Negative Flag, N

Overflow Flag, OF

Underflow Flag, UF

Auxiliary Area Section 3-6

!

66

Note Do not use A50015 to control execution of differentiated instructions. The

instructions will never be executed.

3-6-54 Clock Pulse Bits

Four clock pulses are available to control program timing. Each clock pulse
bit is ON for the first half of the rated pulse time, then OFF for the second
half. In other words, each clock pulse has a duty factor of 50%.

These clock pulse bits are often used with counter instructions to create tim­ers. Refer to

5-13 Timer and Counter Instructions

for an example of this.

Pulse width 0.1 s 0.2 s 1.0 s 0.02 s
Bit A50100 A50101 A50102 A50103

Bit A50103

0.02-s clock pulse

Bit A50100

0.1-s clock pulse

Bit A50101

0.2-s clock pulse

Bit A50102

1.0-s clock pulse

0.1 s

.05 s .05 s

1.0 s

0.5 s 0.5 s

0.2 s

0.1 s 0.1 s

0.02 s

.01 s .01 s

Caution Because the 0.1-second and 0.02-second clock pulse bits have ON times of 50

and 10 ms, respectively, the CPU may not be able to accurately read the pulses i f
program execution time is too long.

3-6-55Network Status Flags

Bits A50200 through A50207 are turned ON to indicate that ports #0 through
#7, respectively, are enabled for the SEND(192), RECV(193), and
CMND(194) in either a SYSMAC NET Link or SYSMAC LINK System. Bits
A50208 through A50215 are turned ON to indicate that an error has occurred
in ports #0 through #7, respectively, during data communications using
SEND(192), RECV(193), or CMND(194).

A503 through A510 contain the completion codes for ports #0 through #7, re­spectively, following data communications using SEND(192), RECV(193), or
CMND(194). Refer to the

SYSMAC NET Link System Manual

or

SYSMAC LINK

System Manual

for details on completion codes.

3-6-56EM Status Flags

The rightmost digit of A511 will contain the current bank number. Bit A51115 (the
EM Installed Flag) is turned ON when a EM Unit is mounted to the CPU.

3-7 Transition Area

A transition is a condition which moves the active status from one step to the next
in the SFC program. Flags in the Transition Area are turned ON when a
TOUT(202) instruction is executed with an ON execution condition, or a
TCNT(123) counter times out.

The CV500 has 512 Transition Flags, numbered TN0000 to TN0511, and the
CV1000 or CV2000 has 1,024 Transition Flags, numbered TN0000 to TN1023.

Transition Area Section 3-7

67

Input the transition number as a bit operand when designating Transition Flags
in instructions.

The CVM1 does not support SFC programming and is not equipped with a Tran­sition Area.

3-8 Step Area

A step in the program represents a single process. All SFC programs are
executed by step. Each step must have its own unique step number. Flags in the
Step Area are turned ON to indicate that a step is active.

The CV500 has 512 Step Flags, numbered ST0000 to ST0511, and the CV1000
or CV2000 has 1,024 Step Flags, numbered ST0000 to ST1023. Input the step
number as a bit operand when designating Step Flags in instructions.

The CVM1 does not support SFC programming and is not equipped with a Step
Area.

3-9 Timer Area

Timer Completion Flags and present values (PV) are accessed through timer
numbers ranging from T0000 through T0511 for the CV500 or
CVM1-CPU01-EV2 and from T0000 through T1023 for the CV1000, CV2000,
CVM1-CPU11-EV2, or CVM1-CPU21-EV2. Each timer number and its set
value (SV) are defined using timer instructions. No prefix is required when
using a timer number to create a timer in one of these instructions.

The same timer number can be defined using more than one of these
instructions as long as the instructions are not executed in the same cycle. If
the same timer number is defined in more than one of these instructions or in
the same instruction twice, an error will be generated during the program
check, but as long as the instructions are not executed in the same cycle,
they will operate correctly. There are no restrictions on the order in which tim­er numbers can be used.

Once defined, a timer number can be designated as an operand in one or
more of certain instructions. Timer numbers can be designated for operands
that require bit data or for operands that require word data. When designated
as an operand that requires bit data, the timer number accesses the Comple­tion Flag of the timer. The Completion Flag will be ON when the timer has
timed out. When designated as an operand that requires word data, the timer
number accesses a memory location that holds the PV of the timer.

Timer PVs are reset when PC operation is begun, when the CNR(236)
instruction is executed, and when in interlocked program sections when the
execution condition for IL(002) is OFF. Refer to

5-8 Interlock and Interlock

Clear – IL(02) and ILC(03)

for details on timer operation in interlocked pro-

gram sections.
When the cycle time exceeds 10 ms, define TIMH(015) instructions with timer

numbers T0000 through T0127 for the CV500 or CVM1-CPU01-EV2, and
T0000 through T0255 for the CV1000, CV2000, CVM1-CPU11-EV2, or
CVM1-CPU21-EV2, to ensure accuracy.

TIM timers are not affected by the cycle time, but TTIM(120) timers time slowly if
the cycle time exceeds 100 ms.

Timer Area Section 3-9

68

3-10 Counter Area

Counter Completion Flags and present values (PV) are accessed through
counter numbers ranging from C0000 through C0511 for the CV500 or
CVM1-CPU01-EV2 and from C0000 through C1023 for the CV1000,
CV2000, CVM1-CPU11-EV2, or CVM1-CPU21-EV2. Each counter number
and its set value (SV) are defined using counter instructions. No prefix is re­quired when using a counter number to create a counter in a counter instruc­tion.

The same counter number can be defined using more than one of these
instructions as long as the instructions are not executed in the same cycle. If
the same counter number is defined in more than one of these instructions or
in the same instruction twice, an error will be generated during the program
check, but as long as the instructions are not executed in the same cycle,
they will operate correctly. There are no restrictions on the order in which
counter numbers can be used.

Once defined, a counter number can be designated as an operand in one or
more of certain instructions other than those listed above. Counter numbers
can be designated for operands that require bit data or for operands that re­quire word data. When designated as an operand that requires bit data, the
counter number accesses the completion flag of the counter. When desig­nated as an operand that requires word data, the counter number accesses a
memory location that holds the PV of the counter.

Counter PVs are reset when the CNR(236) instruction is executed, but unlike
timers, counters maintain their status when PC operation is begun, and when
in interlocked program sections when the execution condition for IL(002) is
OFF.

3-11 DM and EM Areas

The DM (Data Memory) Area is used for internal data storage and manipula­tion and is accessible only by word. Addresses range from D00000 through
D08191 for the CV500 or CVM1-CPU01-EV2; from D00000 through D24575
for the CV1000, CV2000, CVM1-CPU11-EV2, or CVM1-CPU21-EV2.

The EM (Extended Data Memory) Area is available with the CV1000,
CV2000, or CVM1-CPU21-EV2 only and only if purchased and installed as
an option. EM Area and DM Area functions are identical. The main difference
between EM and DM is that DM is internal, while EM is contained on an EM
Unit, a card that fits into a slot on the CV1000, CV2000, or
CVM1-CPU21-EV2 CPU. There are three models of Memory Units available,
with 64K words (E00000 to E32765 × 2 banks), 128K words (E00000 to
E32765 × 4 banks), and 256K words (E00000 to E32765 × 8 banks).

When the PC is turned on, the EM bank number is automatically set to 0, but can
be changed with the EMBC(171) instruction.

When using the SYSMAC NET Link or SYSMAC LINK systems, D00000
through D00127 are automatically allocated as part of the Data Link Table
unless data link are set manually from the CVSS/SSS. The 1,l600 words
from D02000 to D03599 are allocated for CPU Bus Units, 100 words for each
Unit. The particular function depends on the type of CPU Bus Unit being
used. Refer to the CPU Bus Unit’s

Operation Manual

for details.

Note D02000 to D03599 are not used by SYSMAC BUS/2 Remote I/O Master Units.

DM and EM Areas Section 3-11

69

Although composed of 16 bits just like any other word in memory, DM and
EM words cannot be specified by bit for use in instructions with bit-size oper­ands, such as LD, OUT, AND, and OR, nor can DM words be used with the
SHIFT instruction.

The DM and EM Areas retain status during power interruptions.

Normally, when the content of a data area word is specified for an instruction,
the instruction is performed directly on the content of that word. For example,
suppose CMP(020) (COMPARE) is used in the program with CIO 0005 as
the first operand and D00010 as the second operand. When this instruction
is executed, the content of CIO 0005 is compared with that of D00010.

It is also possible, however, to use indirect DM and EM addresses as oper­ands for instructions. If *D00100 is specified as the data for a programming
instruction, the asterisk in front of D indicates that it is an indirect address
that specifies another which contains the actual operand data. Likewise, EM
indirect addressing is indicated by an asterisk in front of the E, *E. When ad­dressed indirectly, the content of *D00100 can be read as either BCD or
binary (hexadecimal) data, depending on the PC Setup for indirect addres­sing.

If the PC Setup define the content of a *DM (or *EM) address as BCD, the
number indicates another DM (or EM) address. If the contents of the *DM
address are not BCD, a *DM BCD error will occur, and an error flag, A50003,
will be turned ON. Because only the last four digits of the final address can
be specified in one word, the range of possible BCD numbers is #0000 to
#9999, and the range of DM addresses that can be addressed indirectly is
D00000 to D09999.

If the content of D00100 is #0324, then *D00100 indicates D00324 as the
word that contains the desired data, and the content of D00324 is used as
the operand in the instruction. The following shows an example of this with
the MOVE instruction.

Word Content

D00099 4C59
D00100 0324
D00101 F35A

D00324 5555
D00325 2506
D00326 D541

5555 moved
to A0090.

Indicates
D00324.

Indirect
address

(030)
MOV *D00100 A090

If the PC Setup define the content of a *DM address as binary, the number
indicates a PC memory address. The range of possible binary numbers,
$0000 to $FFFF, allows all memory areas, including EM, to be indirectly ad­dressed.

wIf, in this case, the content of D00100 is $0324, then *D00100 indicates PC
memory address $0324, which is CIO 0804 in the SYSMAC BUS/2 Area, as the
word that contains the desired data, and the content of CIO 0804 is used as the
operand in the instruction. The following example shows this type of indirect ad­dressing with the MOVE instruction.

Indirect Addressing

DM and EM Areas Section 3-11

70

Word Content

D00099 4C59
D00100 0200
D00101 F35A

CIO 0512 5555
CIO 0513 2506
CIO 0514 D541

5555 moved
to A090.

Indicates
CIO 0512.

Indirect
address

(030)
MOV *D00100 A090

Indirect addressing can also be used in instructions that require bit operands
for bits in the Core I/O Area ($0000 to $0FFF). These bits are designated by
using the rightmost digits of the memory address as the leftmost three digits
of the hexadecimal address and adding the bit number as the rightmost digit.
For example, the CIO bit 190000 is designated by $76CA where 76C is the
rightmost three digits of the memory address (CIO word 1900 is $076C) and
A is bit 10.

3-12 Index and Data Registers (IR and DR)

The Index Registers, IR0, IR1, and IR2, which contain a single word of data, are
used for indirect addressing. A “,” prefix is included before an Index Register to
indicate indirect addressing, just as the “*” prefix is used to indicate indirect ad­dressing with DM and EM.

If an Index Register is used as an operand in an instruction without the “,”
prefix, the instruction is performed directly on the content of that Index Regis­ter, as in the following example.

08FC moved
to IR0.

Word Content

D00000 08FC

Word Content

IR0 08FC

(030)
MOV D00000 IR0

If an Index Register is used as an operand in an instruction with the “,” prefix,
the instruction is performed on the word at the PC memory address indicated
by that Index Register, as in the following example.

Word Content

IR0 076C

08FC moved
to CIO 1900.

Indicates 076C
(CIO 1900)

Indirect
address

Word Content

D00000 08FC

Word Content

CIO 1900 08FC

(030)
MOV D00000 ,IR0

Indirect addressing can also be used in instructions that require bit operands
for bits in the Core I/O Area ($0000 to $0FFF). These bits are designated by
using the rightmost digits of the memory address as the leftmost three digits

Direct Addressing

Indirect Addressing

Index and Data Registers (IR and DR) Section 3-12

71

of the hexadecimal address and adding the bit number as the rightmost digit.
For example, the CIO bit 190000 is designated by $76CA where 76C is the
rightmost three digits of the memory address (CIO word 1900 is $076C) and
A is bit 10.

The PC memory address indicated in an Index Register can be offset by a
specified constant or by the content of a Data Register (DR0, DR1, or DR2)
by inputting the constant or the Data Register before the “,” prefix. The
constant must be in BCD between –2047 and +2047. To offset the indirect
addressing by +31 words, simply input +31, before the “,” prefix, as shown.

Register Content

IR0 076C
+31 1F

078B

08FC moved
to CIO 1931.

Indicates 078B
(CIO 1931)

Word Content

D00000 08FC

Word Content

CIO 1931 08FC

(030)
MOV D00000 +31,IR0

Indirect
address

If a Data Register is input before the “,” prefix, the content of the Data Register
will be added to the content of the Index Register, and the result is the PC
memory address that is indirectly addressed. If the result exceeds $FFFF, the
carry to the fifth digit is truncated (effectively subtracting $10000 (65,536, deci­mal) from the result). In the following example, DR1 is added to IR0. The content
of DR1 is $FFE1, so adding $FFE1 is equivalent to subtracting 1F ($0FFE1 –
$10000 = –1F), for all IR0 values greater than or equal to $001F.

08FC moved
to CIO 1869.

Indicates 074D
(CIO 1869)

Word Content

D00000 08FC

Word Content

CIO 1869 08FC

Register Content

DR1 FFE1
IR0 076C

1074D

Indirect
address

(030)
MOV D00000 DR1,IR0

An auto-increment increases the contents of an Index Register by 1 or 2 after
executing the instruction. A “+” suffix indicates an auto-increment of 1, and a
“++” suffix indicates an auto-increment of 2.

An auto-decrement decreases the contents of an Index Register by 1 or 2 before
executing the instruction. A“–” prefix indicates an auto-decrement of 1, and a
“––” prefix indicates an auto-decrement of 2. The notation for auto-increments
and auto-decrements is as follows:

,IRn+: After execution, increase the contents of IRn by 1.
,IRn++: After execution, increase the contents of IRn by 2.
,–IRn: Decrease the contents of IRn by 1 before execution.
,––IRn: Decrease the contents of IRn by 2 before execution.

Both an auto-increment and an auto-decrement are used in the following exam­ple. The data movement for the first execution is shown. The second execution

Offset Indirect Addressing

Auto-increments and
Auto-decrements

Index and Data Registers (IR and DR) Section 3-12

72

would move the contents of CIO 1902 to CIO 1898; the third execution would
move the contents of CIO 1904 to CIO 1897; etc.

Word Content

CIO 1900 08FC

Word Content

CIO 1899 08FC

Register Content

IR1 076C
IR0 076C

(030)
MOV IR0++ IR1–

CIO 1900 – 1

CIO 1900

Index and Data Registers (IR and DR) Section 3-12

73

SECTION 4

Writing Programs

This section explains the basic steps and concepts involved in writing a basic ladder diagram program. It introduces the
instructions that are used to build the basic structure of the ladder diagram and control its execution, along with a few other
instructions of special interest in programming. It also introduces the new version-2 CVM1 CPUs instructions and explains
the data formats that they can utilize.

The entire set of instructions used in programming is described in Section 5 Instruction Set.

4-1 Basic Procedure 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-2 Instruction Terminology 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3 Basic Ladder Diagrams 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3-1 Basic Terms 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3-2 Basic Mnemonic Code 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3-3 Ladder Instructions 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3-4 OUTPUT and OUTPUT NOT 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3-5 The END Instruction 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-4 Mnemonic Code 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-4-1 Logic Block Instructions 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-4-2 Coding Multiple Right-hand Instructions 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-5 Branching Instruction Lines 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-5-1 TR Bits 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-5-2 Interlocks 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-6 Jumps 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-7 Controlling Bit Status 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-7-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN 94. . . . . . . . . . . . . . . . . . . .

4-7-2 SET and RESET 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-7-3 KEEP 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-7-4 Self-maintaining Bits (Seal) 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-8 Intermediate Instructions 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-9 Work Bits (Internal Relays) 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-10 Programming Precautions 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-11 Program Execution 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-12 Using Version-2 CVM1 CPUs 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-12-1 Input Comparison Instructions 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-12-2 CMP and CMPL 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-12-3 Enhanced Math Instructions 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13 Data Formats 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13-1 Unsigned Binary Data 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13-2 Signed Binary Data 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13-3 BCD Data 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13-4 Signed BCD Data 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13-5 Floating-point Data 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

74

4-1 Basic Procedure

There are several basic steps involved in writing a program. Sheets that can be
copied to aid in programming are provided in

Appendix E I/O Assignment Sheets

and

Appendix F Program Coding Sheet

.

1, 2, 3...

1. Obtain a list of all I/O devices and the I/O points that have been assigned to
them and prepare a table that shows the I/O bit allocated to each I/O device.

2. If the PC has any Units that are allocated words in data areas other than the
CIO area or are allocated CIO words in which the function of each bit is spe­cified by the Unit, prepare similar tables to show what words are used for
which Units and what function is served by each bit within the words. These
Units include CPU Bus Units, Special I/O Units, and Link Units.

3. Determine what words are available for work bits and prepare a table in
which you can allocate these as you use them.

4. Also prepare tables of timer and counter numbers and jump numbers so that
you can allocate these as you use them. Remember, timer and counter
numbers can be defined only once within the program; jump numbers can
be used only once each. (timer/counter numbers are described in

5-13 Tim-

er and Counter Instructions

; jump numbers are described in this section.)

5. Draw the ladder diagram. If SFC programming is being used, you will need
to write a ladder diagram for each action program and each transition pro­gram. You will also need to write interrupt programs if they are required.

Note The CVM1 does not support SFC programming.

6. Input the program into the CPU. Actual input is done from the CVSS and is
possible in either ladder diagram or mnemonic form.

7. Check the program for syntax errors and correct these.

8. Execute the program to check for execution errors and correct these.

9. After the entire Control System has been installed and is ready for use,
execute the program and fine tune it if required.

The basics of ladder-diagram programming and conversion to mnemonic code
are described in

4-3 Basic Ladder Diagrams

. The rest of Section 4 covers more
advanced programming, programming precautions, and program execution. All
instructions are covered in

Section 5 Instruction Set. Section 8 Error Processing

provides information required for debugging. Refer to the

CVSS Operation

Manuals

for program input, debugging, and monitoring procedures.

4-2 Instruction Terminology

There are basically two types of instructions used in ladder-diagram program­ming: instructions that correspond to the conditions on the rungs of the ladder
diagram and are used in instruction form only when converting a program to
mnemonic code, and instructions that are used on the right side of the ladder
diagram and are executed according to the conditions on the instruction lines
leading to them.

Most instructions have at least one or more operands associated with them.
Operands indicate or provide the data on which an instruction is performed.
These are sometimes input as the actual numeric values, but are usually the ad­dresses of data area words or bits that contain the data to be used. For instance,
a MOVE instruction that has CIO 0000 designated as the source operand will
move the contents of CIO 0000 to some other location. The other location is also
designated as an operand. A bit whose address is designated as an operand is
called an operand bit; a word whose address is designated as an operand is
called a n operand word. If the value is entered as a constant, it is preceded by #
to indicate it is not an address, but the actual value to be used in the instruction.

Refer to

Section 5 Instruction Set

for other terms used in describing instructions.

Instruction Terminology Section 4-2

75

4-3 Basic Ladder Diagrams

A ladder diagram consists of two vertical lines running down the sides with lines
branching in between them. The vertical lines are called bus bars; the branch­ing lines, instruction lines or rungs. Along the instruction lines are placed
conditions that lead to other instructions next to the right bus bar. The logical
combinations of the conditions on the instruction lines determine when and how
the instructions at the right are executed. A ladder diagram is shown below .

Instruction

Instruction

0000000063150252080001090025030244

00

0244

01

0000

01

0005010005

02

0005030005

04

000100000002000003000050000007T000010005150004030004

05

0000

10

0000

11

0210010210

02

0210050210

07

As shown in the diagram above, instruction lines can branch apart and they can
join back together. The short vertical pairs of lines are called conditions. Condi­tions without diagonal lines through them are called normally open conditions
and correspond to a LOAD, AND, or OR instruction. The conditions with diago­nal lines through them are called normally closed conditions and correspond
to a LOAD NOT, AND NOT, or OR NOT instruction. The number above each
condition indicates the operand bit for the instruction. It is the status of the bit
associated with each condition that determines the execution condition for fol­lowing instructions. Only these conditions and a limited number of intermediate
instructions can appear along the instruction lines. All other instructions must
appear next to the right bus bar. Instructions that appear next to the right bus bar
are called right-hand instructions.

The way the operation of each of the instructions corresponds to a condition is
described below. Before we consider these, however, there are some basic
terms that must be explained.

4-3-1 Basic Terms

Each condition in a ladder diagram is either ON or OFF depending on the status
of the operand bit that has been assigned to it. A normally open condition is ON if
the operand bit is ON; OFF if the operand bit is OFF. A normally closed condition
is ON if the operand bit is OFF; OFF if the operand bit is ON. Generally speaking,
you use a normally open condition when you want something to happen when a
bit is ON, and a normally closed condition when you want something to happen
when a bit is OFF.

0000

00

0000

00

Instruction

Instruction

Instruction is executed when
CIO bit 00000 is ON.

Instruction is executed when
CIO bit 00000 is OFF.

Normally open
condition

Normally closed
condition

Normally Open and
Normally Closed
Conditions

Basic Ladder Diagrams Section 4-3

76

In ladder diagram programming, the logical combination of ON and OFF condi­tions before an instruction determines the compound condition under which the
instruction is executed. This condition, which is either ON or OFF, is called the
execution condition for the instruction. All instructions other than LOAD instruc­tions have execution conditions. Execution conditions are maintained in buffers
in memory and are continuously changed by each instruction that is executed
until a LOAD or LOAD NOT instruction is used to start a new instruction line and
thus a new execution condition.

The operands designated for any of the ladder instructions can be any bit in the
data areas accessible by bit (e.g., not the DM or EM Areas). This means that the
conditions in a ladder diagram can be determined by I/O bits, flags, work bits,
timers/counters, etc. LOAD and OUTPUT instructions can also use TR Area
bits, but they do so only in special applications. Refer to

4-5-1 TR Bits

for details.

The relationship between the conditions on the instruction lines that lead to an
instruction determine the execution condition for the instruction. Any group of
conditions that go together to create an execution condition for an instruction is
called a logic block. Although ladder diagrams can be written without actually
analyzing individual logic blocks, understanding logic blocks is necessary for ef­ficient programming and is essential when programs are to be input in mnemon­ic code.

Version-2 CVM1 CPUs support the block programming instructions of the
C1000H and C2000H. Block programming is a form of programming that can
make it easier to program complex operations such as a series of data calcula­tions that would be difficult to program using ladder diagrams. Creating struc­tured programs can shorten cycle time, thereby improving overall system pro­cessing speed.

4-3-2 Basic Mnemonic Code

Programs can be input from a Peripheral Device in either graphic form (i.e., as a
ladder diagram) or in mnemonic form (i.e., as a list of code). The mnemonic code
provides exactly the same information as the ladder diagram. You can program
directly in mnemonic code, although it is not recommended for beginners or for
complex programs. Programming in mnemonic code is also necessary when a
logic block contains more than twenty instruction lines.

Because of the importance of mnemonic code in complete understanding of a
program, we will introduce and describe the mnemonic code along with ladder
diagrams.

The program is input into addresses in Program Memory. Addresses in Program
Memory are slightly different to those in other memory areas because each ad­dress does not necessarily hold the same amount of data. Rather, each address
holds one instruction and all of the definers and operands (described in more
detail later) required for that instruction.

With a CV-series PC, instructions can require between one and eight words in
memory. The length of an instruction depends not only on the instruction, but
also on the operands used for the instruction. If an index register is addressed
directly or a data register is used as an operand, the instruction will require one
word less than when specifying a word address for the operand. If a constant is
designated for instructions that use 2-word operands, the instruction will require
one word more than when specifying a word address for the operand. The pos­sible lengths for each instruction are provided in

Section 6 Program Execution

Timing

.

Program Memory addresses start at 00000 and run until the capacity of Program
Memory has been exhausted. The first word at each address defines the instruc­tion. Any definers used by the instruction are placed on the same line of code.

Execution Conditions

Operand Bits

Logic Blocks

Block Programming

Program Memory Structure

Basic Ladder Diagrams Section 4-3

77

Also, if an instruction requires only a single bit operand (with no definer), the bit
operand is also placed on the same line as the instruction. The rest of the words
required by an instruction contain the operands that specify what data is to be
used. All other instructions are written with the instruction on the first line fol­lowed by the operands one to a line. An example of mnemonic code is shown
below. The instructions used in it are described later in the manual. When input­ting programs in mnemonic form from the CVSS, most operands are separated
only by spaces. Refer to the

CVSS Operation Manuals

for details.

Address Instruction Operands

00000 LD 000000
00001 AND 000001
00002 OR 000002
00003 LD NOT 000100
00004 AND 000101
00005 AND LD 000102
00006 MOV(030)

0000
D00000

00007 CMP(020)

D00000

0000
00008 LD 025505
00009 OUT 000501
00010 MOV(030)

D00000

D00500
00011 DIFU(013) 000502
00012 AND 000005
00013 OUT 000503

The address and instruction columns of the mnemonic code table are filled in for
the instruction word only . For all other lines, the left two columns are left blank. If
the instruction requires no definer or bit operand, the operand column is left
blank for first line. It is a good idea to cross through any blank data column
spaces (for all instruction words that do not require data) so that the data column
can be quickly scanned to see if any addresses have been left out.

When programming, addresses are automatically displayed and do not have to
be input unless for some reason a different location is desired for the instruction.
When converting to mnemonic code, it is best to start at Program Memory ad­dress 00000 unless there is a specific reason for starting elsewhere.

4-3-3 Ladder Instructions

The ladder instructions are those instructions that correspond to the conditions
on the ladder diagram. Ladder instructions, either independently or in combina­tion with the logic block instructions described later, form the execution condi­tions upon which the execution of all other instructions are based.

Basic Ladder Diagrams Section 4-3

78

The first condition that starts any logic block within a ladder diagram corre­sponds to a LOAD or LOAD NOT instruction. Each of these instructions is written
on one line of mnemonic code. “Instruction” is used as a dummy instruction in the
following examples and could be any of the right-hand instructions described lat­er in this manual.

A LOAD instruction.

A LOAD NOT instruction.

Address Instruction

00000 LD 000000
00001 Instruction
00002 LD NOT 000000
00003 Instruction

Operands

0000

00

0000

00

When this is the only condition on the instruction line, the execution condition for
the instruction at the right is ON when the execution condition is ON. For the
LOAD instruction (i.e., a normally open condition), an ON execution condition
would be produced when CIO 000000 was ON; for the LOAD NOT instruction
(i.e., a normally closed condition), an ON execution condition would be pro­duced when CIO 000000 was OFF.

When two or more conditions lie in series on the same instruction line, the first
one corresponds to a LOAD or LOAD NOT instruction, and the rest of the condi­tions correspond to AND or AND NOT instructions. The following example
shows three conditions which correspond in order from the left to a LOAD, an
AND NOT, and an AND instruction. Again, each of these instructions is written
on one line of mnemonic code.

Address Instruction

00000 LD 000000
00001 AND NOT 000100
00002 AND 000200
00003 Instruction

0000

00

0001

00

0002

00

Instruction

Operands

The instruction would have an ON execution condition only when CIO 000000
was ON, CIO 000100 was OFF, and CIO 000200 was ON.

AND instructions in series can be considered individually, with each taking the
logical AND of the execution condition produced by the preceding instruction
and the status of the AND instruction’s operand bit. If both of these are ON, an
ON execution condition will be produced for the next instruction. If either is OFF ,
the resulting execution condition will also be OFF.

Each AND NOT instruction in a series would take the logical AND between the
execution condition produced by the preceding instruction and the inverse of its
operand bit.

When two or more conditions lie on separate instruction lines running in parallel
and then joining together, the first condition corresponds to a LOAD or LOAD
NOT instruction; the rest of the conditions correspond to OR or OR NOT instruc­tions. The following example shows three conditions which correspond in order
from the top to a LOAD NOT, an OR NOT, and an OR instruction. Again, each of
these instructions requires one line of mnemonic code.

Address Instruction

00000 LD NOT 000000
00001 OR NOT 000100
00002 OR 000200
00003 Instruction

Operands

0000

00

0001

00

0002

00

Instruction

LOAD and LOAD NOT

AND and AND NOT

OR and OR NOT

Basic Ladder Diagrams Section 4-3

79

The instruction at the right would have an ON execution condition when any one
of the three conditions was ON, i.e., when CIO 00000 was OFF, when CIO 00100
was OFF, or when CIO 000200 was ON.

OR and OR NOT instructions can be considered individually, each taking the
logical OR between the execution condition produced by the preceding instruc­tions and the status of the OR instruction’s operand bit. If either one of these
were ON, an ON execution condition would be produced for the next instruction.

When AND and OR instructions are combined in more complicated diagrams,
they can sometimes be considered individually, with each instruction performing
a logic operation on the current execution condition and the status of the oper­and bit. The following is one example. Study this example until you are con­vinced that the mnemonic code follows the same logic flow as the ladder dia­gram.

Instruction

0000

03

0000000000010000

02

0002

00

Address Instruction Operands

00000 LD 000000
00001 AND 000001
00002 OR 000200
00003 AND 000002
00004 AND NOT 000003
00005 Instruction

Here, an AND is taken between the status of CIO 000000 and that of
CIO 000001 to determine the execution condition for an OR with the status of
CIO 000200. The result of this operation determines the execution condition for
an AND with the status of CIO 000002, which in turn determines the execution
condition for an AND with the inverse (i.e., and AND NOT) of the status of
CIO 000003.

In more complicated diagrams, it is necessary to consider logic blocks before an
execution condition can be determined for the final instruction, and that’s where
AND LOAD and OR LOAD instructions are used. Before we consider more com­plicated diagrams, however, we’ll look at the instructions required to complete a
simple “input-output” program.

4-3-4 OUTPUT and OUTPUT NOT

The simplest way to output the results of combining execution conditions is to
output it directly with the OUTPUT and OUTPUT NOT. These instructions are
used to control the status of the designated operand bit according to the execu­tion condition. With the OUTPUT instruction, the operand bit will be turned ON
as long as the execution condition is ON and will be turned OFF as long as the
execution condition is OFF. With the OUTPUT NOT instruction, the operand bit
will be turned ON as long as the execution condition is OFF and turned OFF as
long as the execution condition is ON. These appear as shown below. In mne­monic code, each of these instructions requires one line.

Address Instruction Operands

00000 LD 000000
00001 OUT 000200

Address Instruction Operands

00000 LD 000001
00001 OUT NOT 000201

0002

00

0002

01

0000

00

0000

01

Combining AND and OR
Instructions

Basic Ladder Diagrams Section 4-3

80

In the above examples, CIO 000200 will be ON as long as CIO 000000 is ON and
CIO 000201 will be ON as long as CIO 000001 is OFF. Here, CIO 000000 and
CIO 000001 would be input bits and CIO 000200 and CIO 000201 output bits
assigned to the Units controlled by the PC, i.e., the signals coming in through the
input points assigned CIO 000000 and CIO 000001 are controlling the output
points to which CIO 000200 and CIO 000201 are allocated.

The length of time that a bit is ON or OFF can be controlled by combining the
OUTPUT or OUTPUT NOT instruction with Timer instructions. Refer to Exam­ples under

5-13-1 Timer – TIM

for details.

4-3-5 The END Instruction

The last instruction required to complete any program is the END instruction.
When the CPU scans a program, it executes all instructions up to the first END
instruction before returning to the beginning of the program and beginning
execution again. Although an END instruction can be placed at any point in a
program, which is sometimes done when debugging, no instructions past the
first END instruction will be executed. The number following the END instruction
in the mnemonic code is its function code, which is used when inputting most
instructions into the PC. Function codes are described in more detail later . The
END instruction requires no operands and no conditions can be placed on the
instruction line with it.

Program
execution
ends here.

Address Instruction

00500 LD 000000
00501 AND NOT 000001
00502 Instruction
00503 END(001) ---

Operands

Instruction

0000

00

0000

01

(001)
END

If there is no END instruction anywhere in a program, the program will not be
executed at all.

4-4 Mnemonic Code

4-4-1 Logic Block Instructions

Logic block instructions do not correspond to specific conditions on the ladder
diagram; rather, they describe relationships between logic blocks. Each logic
block is started with a LOAD or LOAD NOT instruction. Whenever a LOAD or
LOAD NOT instruction is executed, a new execution condition is created and the
previous execution condition is stored in a buffer. The AND LOAD instruction
logically ANDs the execution conditions produced by two logic blocks, i.e., gen­eral speaking, it ANDs the current execution condition with the last execution
condition stored in a buffer. The OR LOAD instruction logically ORs the execu­tion conditions produced by two logic blocks.

Mnemonic Code Section 4-4

81

Although simple in appearance, the diagram below requires an AND LOAD
instruction.

Address Instruction

00000 LD 000000
00001 OR 000001
00002 LD 000002
00003 OR NOT 000003
00004 AND LD ---

0000

00

Instruction

0000

02

0000

01

0000

03

Operands

The two logic blocks are indicated by dotted lines. Studying this example shows
that an ON execution condition will be produced when: either of the conditions in
the left logic block is ON (i.e., when either CIO 000000 or CIO 000001 is ON) and
either of the conditions in the right logic block is ON (i.e., when either
CIO 000002 is ON or CIO 000003 is OFF).

The above ladder diagram cannot be converted to mnemonic code using AND
and OR instructions alone. If an AND between CIO 000002 and the results of an
OR between CIO 000000 and CIO 000001 is attempted, the OR NOT between
CIO 000002 and CIO 000003 is lost and the OR NOT ends up being an OR NOT
between just CIO 000003 and the result of an AND between CIO 000002 and the
first OR. What we need is a way to do the OR (NOT)’s independently and then
combine the results.

To do this, we can use the LOAD or LOAD NOT instruction in the middle of an
instruction line. When LOAD or LOAD NOT is executed in this way, the current
execution condition is saved in special buffers and the logic process is begun
over. To combine the results of the current execution condition with that of a pre­vious “unused” execution condition, an AND LOAD or an OR LOAD instruction is
used. Here “LOAD” refers to loading the last unused execution condition. An un­used execution condition is produced by using the LOAD or LOAD NOT instruc­tion for any but the first condition on an instruction line.

Analyzing the above ladder diagram in terms of mnemonic instructions, the
condition for CIO 000000 is a LOAD instruction and the condition below it is an
OR instruction between the status of CIO 000000 and that of CIO 000001. The
condition at CIO 000002 is another LOAD instruction and the condition below is
an OR NOT instruction, i.e., an OR between the status of CIO 000002 and the
inverse of the status of CIO 000003. To arrive at the execution condition for the
instruction at the right, the logical AND of the execution conditions resulting from
these two blocks would have to be taken. AND LOAD does this. The mnemonic
code for the ladder diagram is shown to the right of the diagram. The AND LOAD
instruction requires no operands of its own, because it operates on previously
determined execution conditions. Here too, dashes are used to indicate that no
operands needs designated or input.

AND LOAD

Mnemonic Code Section 4-4

82

The following diagram requires an OR LOAD instruction between the top logic
block and the bottom logic block. An ON execution condition would be produced
for the instruction at the right either when CIO 000000 is ON and CIO 000001 is
OFF or when CIO 000002 and CIO 000003 are both ON. The operation of and
mnemonic code for the OR LOAD instruction is exactly the same as those for a
AND LOAD instruction except that the current execution condition is ORed with
the last unused execution condition.

0000

00

0000

01

0000

02

0000

03

InstructionInstruction

Address Instruction

00000 LD 000000
00001 AND 000001
00002 LD 000002
00003 AND NOT 000003
00004 OR LD ---

Operands

Naturally, some diagrams will require both AND LOAD and OR LOAD instruc­tions.

To code diagrams with logic block instructions in series, the diagram must be
divided into logic blocks. Each block is coded using a LOAD instruction to code
the first condition, and then AND LOAD or OR LOAD is used to logically combine
the blocks. With both AND LOAD and OR LOAD there are two ways to achieve
this. One is to code the logic block instruction after the first two blocks and then
after each additional block. The other is to code all of the blocks to be combined,
starting each block with LOAD or LOAD NOT, and then to code the logic block
instructions which combine them. In this case, the instructions for the last pair of
blocks should be combined first, and then each preceding block should be com­bined, working progressively back to the first block. Although either of these
methods will produce exactly the same result, the second method, that of coding
all logic block instructions together, can be used only if eight or fewer blocks are
being combined, i.e., if seven or fewer logic block instructions are required.

The following diagram requires AND LOAD to be converted to mnemonic code
because three pairs of parallel conditions lie in series. The two means of coding
the programs are also shown.

00000 LD 000000
00001 OR NOT 000001
00002 LD NOT 000002
00003 OR 000003
00004 LD 000004
00005 OR 000005
00006 AND LD --­00007 AND LD --­00008 OUT 000500

0000

00

0000

02

0000

01

0000

03

0000

05

0000

04

0005

00

Address Instruction Operands

Address Instruction Operands

00000 LD 000000
00001 OR NOT 000001
00002 LD NOT 000002
00003 OR 000003
00004 AND LD --­00005 LD 000004
00006 OR 000005
00007 AND LD --­00008 OUT 000500

OR LOAD

Logic Block Instructions in
Series

Mnemonic Code Section 4-4

83

Again, with the second method, a maximum of eight blocks can be combined.
There is n o l i m i t t o the number of blocks that can be combined with the first meth­od.

The following diagram requires OR LOAD instructions to be converted to mne­monic code because three pairs of conditions in series lie in parallel to each oth­er.

0000

01

0000

03

0000

05

0000

00

0000

02

0000

04

0005

01

00000 LD 000000
00001 AND NOT 000001
00002 LD NOT 000002
00003 AND NOT 000003
00004 LD 000004
00005 AND 000005
00006 OR LD —
00007 OR LD —
00008 OUT 000501

Address Instruction Operands

Address Instruction Operands

00000 LD 000000
00001 AND NOT 000001
00002 LD NOT 000002
00003 AND NOT 000003
00004 OR LD —
00005 LD 000004
00006 AND 000005
00007 OR LD —
00008 OUT 000501

The first of each pair of conditions is converted to LOAD with the assigned bit
operand and then ANDed with the other condition. The first two blocks can be
coded first, followed by OR LOAD, the last block, and another OR LOAD, or the
three blocks can be coded first followed by two OR LOADs. The mnemonic code
for both methods is shown to the right of the ladder diagram.

Again, with the second method, a maximum of eight blocks can be combined.
There is n o l i m i t t o the number of blocks that can be combined with the first meth­od.

Both of the coding methods described above can also be used when using AND
LOAD and OR LOAD, as long as the number of blocks being combined does not
exceed eight.

The following diagram contains only two logic blocks as shown. It is not neces­sary to further separate block b components, because it can be coded directly
using only AND and OR.

Block

a

Block

b

Address Instruction

00000 LD 000000
00001 AND NOT 000001
00002 LD 000002
00003 AND 000003
00004 OR 000201
00005 OR 000004
00006 AND LD —
00007 OUT 000501

0000

01

0000

00

0005

01

0000020000

03

0002

01

0000

04

Operands

Combining AND LOAD and
OR LOAD

Mnemonic Code Section 4-4

84

Although the following diagram is similar to the one above, block b in the diagram
below cannot be coded without separating it into two blocks combined with OR
LOAD. In this example, the three blocks have been coded first and then OR
LOAD has been used to combine the last two blocks followed by AND LOAD to
combine the execution condition produced by the OR LOAD with the execution
condition of block a.

When coding the logic block instructions together at the end of the logic blocks
they are combining, they must, as shown below , be coded in reverse order, i.e.,
the logic block instruction for the last two blocks is coded first, followed by the
one to combine the execution condition resulting from the first logic block
instruction and the execution condition of the logic block third from the end, and
on back to the first logic block that is being combined.

Block

a

Block

b

Block

b2

Block

b1

0000000000

01

0005

02

0000

02

0002

02

0000

03

0000

04

Address Instruction Operands

00000 LD NOT 000000
00001 AND 000001
00002 LD 000002
00003 AND NOT 000003
00004 LD NOT 000004
00005 AND 000202
00006 OR LD —
00007 AND LD —
00008 OUT 000502

When determining what logic block instructions will be required to code a dia­gram, it is sometimes necessary to break the diagram into large blocks and then
continue breaking the large blocks down until logic blocks that can be coded
without logic block instructions have been formed. These blocks are then coded,
combining the small blocks first, and then combining the larger blocks. Either
AND LOAD or OR LOAD is used to combine the blocks, i.e., AND LOAD or OR
LOAD always combines the last two execution conditions that existed, regard­less of whether the execution conditions resulted from a single condition, from
logic blocks, or from previous logic block instructions.

When working with complicated diagrams, blocks will ultimately be coded start­ing at the top left and moving down before moving across. This will generally
mean that, when there might be a choice, OR LOAD will be coded before AND
LOAD.

The following diagram must be broken down into two blocks and each of these
then broken into two blocks before it can be coded. As shown below, blocks a
and b require an AND LOAD. Before AND LOAD can be used, however, OR
LOAD must be used to combine the top and bottom blocks on both sides, i.e., to
combine a1 and a2; b1 and b2.

Block

a

Block

b

Block

b2

Block

b1

Block

a2

Block

a1

0000

02

0000

00

0005

03

0000

04

0002

07

0000

01

0000

03

0000

05

0000

06

Address Instruction Operands

00000 LD 000000
00001 AND NOT 000001
00002 LD NOT 000002
00003 AND 000003
00004 OR LD —
00005 LD 000004
00006 AND 000005
00007 LD 000006
00008 AND 000007
00009 OR LD —
00010 AND LD —
00011 OUT 000503

Blocks a1 and a2

Blocks b1 and b2
Blocks a and b

Complicated Diagrams

Mnemonic Code Section 4-4

85

The following type of diagram can be coded easily if each block is coded in order:
first top to bottom and then left to right. In the following diagram, blocks a and b
would be combined using AND LOAD as shown above, and then block c would
be coded and a second AND LOAD would be used to combined it with the execu­tion condition from the first AND LOAD. Then block d would be coded, a third
AND LOAD would be used to combine the execution condition from block d with
the execution condition from the second AND LOAD, and so on through to
block n.

0005

00

Block

a

Block

b

Block

n

Block

c

The following diagram requires an OR LOAD followed by an AND LOAD to code
the top of the three blocks, and then two more OR LOADs to complete the mne­monic code.

Address Instruction

00000 LD 000000
00001 LD 000001
00002 LD 000002
00003 AND NOT 000003
00004 OR LD ––
00005 AND LD ––
00006 LD NOT 000004
00007 AND 000005
00008 OR LD ––
00009 LD NOT 000006
00010 AND 000007
00011 OR LD ––
00012 OUT 000200

0000

00

0000

01

0000020000

03

0000

05

0000

04

0000

06

0000

07

0002

00

Operands

Although the program will execute as written, this diagram could be drawn as
shown below to eliminate the need for the first OR LOAD and the AND LOAD,
simplifying the program and saving memory space.

0000

03

0000

02

0000

00

0000

01

0000

05

0000

06

0000

07

0000

04

0002

00

Address Instruction Operands

00000 LD 000002
00001 AND NOT 000003
00002 OR 000001
00003 AND 000000
00004 LD NOT 000004
00005 AND 000005
00006 OR LD ––
00007 LD NOT 000006
00008 AND 000007
00009 OR LD ––
00010 OUT 000200

Mnemonic Code Section 4-4

86

The following diagram requires five blocks, which here are coded in order before
using OR LOAD and AND LOAD to combine them starting from the last two
blocks and working backward. The OR LOAD at program address 00008 com­bines blocks blocks d and e, the following AND LOAD combines the resulting
execution condition with that of block c, etc.

Address Instruction

Blocks d and e
Block c with result of above
Block b with result of above
Block a with result of above

00000 LD 000000
00001 LD 000001
00002 AND 000002
00003 LD 000003
00004 AND 000004
00005 LD 000005
00006 LD 000006
00007 AND 000007
00008 OR LD ––
00009 AND LD ––
00010 OR LD ––
00011 AND LD ––
00012 OUT 000200

0000

00

0000

01

0000

03

0002

00

0000

02

0000

04

0000

05

0000060000

07

Block

e

Block

d

Block

c

Block

b

Block a

OperandsAddress Instruction Operands

00000 LD 000000
00001 LD 000001
00002 AND 000002
00003 LD 000003
00004 AND 000004
00005 LD 000005
00006 LD 000006
00007 AND 000007
00008 OR LD ––
00009 AND LD ––
00010 OR LD ––
00011 AND LD ––
00012 OUT 000200

Again, this diagram can be redrawn as follows to simplify program structure and
coding and to save memory space.

0000

06

0002

00

0000

07

0000030000

04

0000

00

0000

05

0000

01

0000

02

Address Instruction Operands

00000 LD 000006
00001 AND 000007
00002 OR 000005
00003 AND 000003
00004 AND 000004
00005 LD 000001
00006 AND 000002
00007 OR LD ––
00008 AND 000000
00009 OUT 000200

The next and final example may at first appear very complicated but can be
coded using only two logic block instructions. The diagram appears as follows:

Block cBlock b

Block a

0000

00

0005

00

0000

01

0000

02

0000

04

0000

03

0010000010

01

0005

00

0000

06

0000

05

Mnemonic Code Section 4-4

87

The first logic block instruction is used to combine the execution conditions re­sulting from blocks a and b, and the second one is to combine the execution
condition of block c with the execution condition resulting from the normally
closed condition assigned CIO 000003. The rest of the diagram can be coded
with OR, AND, and AND NOT instructions. The logical flow for this and the re­sulting code are shown below.

000000 000001

000500

000002 000003

001000 001001

000004 000005

000500

000006

Block c

Block bBlock a

OR LD

LD 000000
AND 000001

OR 000500

AND 000002
AND NOT 000003

LD 001000
AND 001001

OR 000006

LD 000004
AND 000005

AND LD

00000 LD 000000
00001 AND 000001
00002 LD 001000
00003 AND 001001
00004 OR LD ––
00005 OR 000500
00006 AND 000002
00007 AND NOT 000003
00008 LD 000004
00009 AND 000005
00010 OR 000006
00011 AND LD ––
00012 OUT 000500

Address Instruction Operands

4-4-2 Coding Multiple Right-hand Instructions

If there is more than one right-hand instruction executed with the same execu­tion condition, they are coded consecutively following the last condition on the
instruction line. In the following example, the last instruction line contains one
more condition that corresponds to an AND with CIO 000400.

Address Instruction

00000 LD 000000
00001 OR 000001
00002 OR 000002
00003 OR 000200
00004 AND 000003
00005 OUT 000001
00006 OUT 000500
00007 AND 000400
00008 OUT 000506

Operands

0000

01

0005

00

0005

06

0000

00

0000

03

0004

00

0000

01

0000

02

0002

00

4-5 Branching Instruction Lines

When an instruction line branches into two or more lines, it is sometimes neces­sary to use either interlocks or TR bits to maintain the execution condition that
existed at a branching point. This is because instruction lines are executed
across to a right-hand instruction before returning to the branching point to
execute instructions one a branch line. If a condition exists on any of the instruc­tion lines after the branching point, the execution condition could change during
this time making proper execution impossible. The following diagrams illustrate

Branching Instruction Lines Section 4-5

88

this. In both diagrams, instruction 1 is executed before returning to the branching
point and moving on to the branch line leading to instruction 2.

Instruction 2

00000 LD 000000
00001 AND 000001
00002 Instruction 1
00003 AND 000002
00004 Instruction 2

00000 LD 000000
00001 Instruction 1
00002 AND 000002
00003 Instruction 2

Branching

point

Diagram B: Incorrect Operation

Diagram A: Correct Operation

Address Instruction

Address Instruction

Operands

Operands

0000

00

0000

02

Instruction 1

0000

00

0000

02

Instruction 2

Instruction 1

Branching

point

0000

01

If, as shown in diagram A, the execution condition that existed at the branching
point cannot be changed before returning to the branch line (instructions at the
far right do not change the execution condition), then the branch line will be
executed correctly and no special programming measure is required.

If, as shown in diagram B, a condition exists between the branching point and the
last instruction on the top instruction line, the execution condition at the branch­ing point and the execution condition after completing the top instruction line will
sometimes be different, making it impossible to ensure correct execution of the
branch line.

There are two means of programming branching programs to preserve the
execution condition. One is to use TR bits; the other, to use interlocks
(IL(002)/ILC(003)).

4-5-1 TR Bits

The TR area provides eight bits, TR0 through TR7, that can be used to tempo­rarily preserve execution conditions. If a TR bit is placed at a branching point, the
current execution condition will be stored at the designated TR bit. When return­ing to the branching point, the TR bit restores the execution status that was
saved when the branching point was first reached in program execution.

Note When programming in graphic ladder diagram form from the CVSS, it is not nec-

essary to input TR bits and none will appear on the screen. The CVSS will auto­matically process TR bits for you as required and input them into the program.
You will have to input TR bit when programming in mnemonic form.

The previous diagram B can be written as shown below to ensure correct execu­tion. In mnemonic code, the execution condition is stored at the branching point
using the TR bit as the operand of the OUTPUT instruction. This execution
condition is then restored after executing the right-hand instruction by using the
same TR bit as the operand of a LOAD instruction

Diagram B: Corrected Using a TR bit

TR0

Address Instruction

00000 LD 000000
00001 OUT TR0
00002 AND 000001
00003 Instruction 1
00004 LD TR0
00005 AND 000002
00006 Instruction 2

Operands

0000

00

0000

02

0000

01

Instruction 2

Instruction 1

Branching Instruction Lines Section 4-5