This maintenance manual describes how to maintain the Pacemark 4410/Microline 4410 printer
in the field.
This manual is for customer engineers.
For further information, refer to the Users Manual for handling or operating the equipment.
Single DensityDouble DensityQuadruple Density
8161,6323,264
b) Text
Print ModeCharacter Pitch (CP)
10 CPI12 CPI15 CPI17.1 CPI 20 CPI
ML, EPSON, IBM UTILITY1,6321,9582,4482,7983,264
ML, EPSON, IBM NLQ3,2643,9174,8965,5966,528
ML, EPSON, IBM HSD1,2241,4681,8362,0982,448
(6) Maximun Number of Character per Line
Character Pitch (CPI)567.58.510121517.120
ML EPSON IBM6881102116136163204233272
(7) Printhead
Print method:Impact dot matrix
Number of dot wires:9 wires x 2 rows
Dot wire diameter:0.36mm(0.014inch)
(8) Line feed Speed
6 LPI spacing, one LF = 60 ms
8 LPI spacing, one LF = 52 ms
Continuous paper feed rate is 15 inches per second. (at head gap 1, 2)
(9) Line Feed Pitches
6 LPI 0.167 inch (4.23mm)
8 LPI 0.125 inch (3.175mm)
A variable line feed pitch of n/216 inch (integer n: 0 ≤ n ≤ 255) can also be specified. Also,
7/72 inch and n/72 inch can be specified.
PROPRINTERn : 1 ≤ n ≤ 255
EPSONn : 1 ≤ n ≤ 255 (Cannot specify MSB : 1≤ n ≤ 127)
(10) Power Requirements
a) Input power
Single-phase AC
Voltage :120VAC +5.5%, -15%
230 VAC ±15%
Frequency : 50/60Hz ±2%
b) Power consumption
Local Test : Max. 295 W (Rolling ASCII, Utility)
Idle :Max. 15W (Energy Star compliant)
c) AC power cable
Length :Approximately 5.9 It (1.8 m)
Cable conforms to the UL, CSA, and European Standards.
40496501TH Rev.110
(11) Ambient temperature and relative humidity
OperatingNon-operatingStorageTransportationUnit
Temperature41 to 9532 to 109.414 to 122-40 to 158°F
(5 to 35)(0 to 43)(-10 to 50)(-40 to 70)(°C)
Relative20 to 8010 to 905 to 955 to 95%RH
Humidity
Avoid condensation at all times.
(12) Vibration
Operating :Max. 0.3G (5 to 150 Hz) (except at resonant frequency)
Non-operating :Max. 1G (5 to 150 Hz) (except at resonant frequency)
(13) Impact (Drop Test)
Packing : 12" Drop
(14) Noise
The 8-second average noise is Max. 55 dBA in quiet utility mode. (ISO 7779)
(15) Ribbon
Genuine OKI cartridge ribbon
Ink color :Black
Ribbon life :Approximately 15 million characters (Characters in Utility mode)
(16) Reliability
a) MTBF (mean time between failures)
12,000 hours of power-on time at 25% duty cycle and 35% page density.
b) Printhead life
400 million characters (average) in 10 CPI Utility print mode at 25% duty cycle and 35%
page density.
c) Printer life
12,000 hours of power-on time at 25% duty cycle and 35% page density, or 5 years.
d) MTTR
30 minutes, major Sub-assembly level.
Definition of terms
• Duty cycle :Actual operation rate
• Page density :The proportion in area of characters and spaces within print head
PPmovable area.
• Power on Time : 8H/day, 25days/month and 12 months/year.
40496501TH Rev.111
2.THEORY OF OPERATION
2.1Electrical Operation
The electrical operation of the printer circuit is described in this section.
2.1.1Summary
Fig. 2-1 shows the block diagram of the printer.
The control board is made up of the microprocessors, peripheral circuits, drive circuits, sensors and
interface connectors.
The power to the control board is supplied by the power board through the connector cord.
The pwer to other electrical parts is also distributed through the connectors within the control board.
2.1.2Microprocessor and the peripheral circuit
(1) Microprocessor (IC24: 80C186-16)
This processor is a CMOS single-chip computer with integrated peripheral device functions
and a 16 bit MPU core.
The processor has a 20 bit address bus and a 16 bit data bus.
It is capable of accessing up to 4M bit program memory and 4M bit of data memory.
The following characteristics are also provided:
•High-Speed DMA Channel x 2
•Programmable Interrupt Controller
•Programmable 16-bit Timer x 3
•Programmable Memory and Peripheral Chip-Select Logic
•Programmable Wait State Generator
•Local Bus Controller
And others.
The function of this microprocessor is to provide a central mechanism for the entire printer
by executing the control program through the LSI and driver circuits.
40496501TH Rev.112
to ALM circuit
PM
LF motor
driver
Sub LSI #1
72V017
AG slit sensor
to ALM circuit
PM
AG motor
driver
P/S FANP/S FAN DV.
HD FAN 1
HD FAN 2
HD FAN DV.1
HD FAN DV.2
SP FAN
CB FAN
SP FAN DV.
FAN ALM
Continuous
paper cutter
(option)
Sub LSI #2
72V017
to ALM circuit
PM
Bail motor
driver
to ALM circuit
PM
Paper path
switching
motor driver
Either of them
LAN
Sensor, SW
DIP SW
SRAM
(1M)
2/2
NHDC LSI
RS232
LSI
1/2
NHDC LSI
D/R
to ALM
circuit
PM
Ribbon motor
driver
DRAM
(4M)
TFA. TFD.720S
PRG,
EEPROM
ROM
(4M)
IEEE1284
BUF
BUF
OPpanel
OPpanel
LSI
CG,
ROM
MUPIS
LCD
(4M)
card
BUF
(x1)
HEAD
Head driver
Extended slot
<OPTION>
ML300's/ 500's
BUF
to ALM circuit
AG sensor
FL ROM
(8M)
OPTION
RS232C, TWINAX,
COAX, etc
Slit sensor
to ALM circuit
SP motor
DC
SP motor driver
ALM circuit
Head/ motor driverPOWEROFF-P
Main LSI
Each part
ALE/ RD/ WR/ CS/ CLK
AD0~AD15
A16~A19/ BHE
+44V
+12V
+ 5V
CPU
80C186
32
MHz
-12V0VEP
Unit
Power Supply
POWOFF-P
POWDOWN-P
AC DOWN-P
POW ONRST-N
POWALM-P
Figure 2.1
40496501TH Rev.113
(2) PG ROM (IC46)
This is a 256 x16 bits (4M bit) EPROM with the control program for the printer stored. The MPU
executes instructions under this program.
The program ROM is assigned to the program memory area of the MPU and is fetched by the
RD signal of the MPU.
The following shows the operation of the memory access.
MPU
ALE
RD
WR
CS
CLK
A16~BHE
AD0~AD15
Main LSIPG ROM
A17
A16
A1~A16
NHDC LSI
BANK0
BANKS
CS
A0~A15
OE
CE
MPU CLOCK
ALE
A16~BHE
AD0~AD15
RD
CS
A16-BHE
A0–A15D0–D15
Figure 2.2
40496501TH Rev.114
(3) DRAM(IC28)
The RAM is CMOS dynamic RAM with (256K x 16 bit) configuration, and used as buffers (such
as receiving buffer, printing buffer, DLL buffer and working buffer).
The following shows the examples of the memory access operation.
MPU CLOCK
ALE
A16~BHE
MPUNHDC LSI
A16~BHE
AD0~AD15
ALE
RD
WR
CS
CLK
A16~BHE
RAS
CASU
CASL
WR
DRAM
DRAMA0~A9
DRAMD0~D15
RD
AD0~AD15
RD
AD0~AD15
WR
CS
A0–A15D0–D15
A0–A15D0–D15
Figure 2.3
40496501TH Rev.115
(4) CG ROM (IC48)
This is a 256K x 16 bits (4M bits) EPROM with the font data for the characters stored.
CG ROM is assigned to the program memory area of the MPU and is fetched by the RD signal
of the MPU.
The following shows the memory access operation.
MPU
ALE
RD
WR
CS
CLK
A16~BHE
AD0~AD15
Main LSICG ROM
A17
A16
A1~A16
NHDC LSI
BANK0
BANKS
CS
A0~A15
OE
CE
MPU CLOCK
ALE
A16~BHE
AD0~AD15
RD
CS
A16-BHE
A0–A15D0–D15
Figure 2.4
40496501TH Rev.116
(5) EEPROM(IC40)
,
The EEPROM is a CMOS serial I/O type memory which is capable of electrically erasing and
writing 1,024 bits.
The EEPROM contains menu data.
The following shows the memory access operation.
NHDC LSIEEPROM
EEPROMWR-P
DI
EEPROMCS-P
CS
EEPROMRD-P
DO
EEPROMCLK-P
SK
PRE = O
PE = X
EEPROMCS-P
EEPROMCLK-P
EEPROMWR-P
EEPROMRD-P
PRE = O
PE
EEPROMCS-P
EEPROMCLK-P
EEPROMWR-P
Read cycle timing (READ)
Operation
Start
code
code
0
11
Write cycle timing (WRITE)
Operation
Start
code
code
0
11
Address
A0A5
0
D15D0 D15D0 D15
AddressData
t
CS
t
CS
D0D15A0A5
EEPROMRD-P
twp
ReadyBus
Figure 2.5
40496501TH Rev.117
(6) Main LSI (IC38: MSM91U036)
MSM91U036 is control LSI for head data, DC motor and modification of print data, which has
the following functions.
(a) Head data control
It distributes print data stored in the DRAM over wire arrangements of the print head and
outputs it as dot data in synchronism with print timing. In this time, the distribution
complies with each print mode which is specified by the MPU.
(b) Print timing control
It outputs the signals which control the print timing of ODD and EVEN pins on the print
head.
(c) Space motor speed control function
It controls the space motor with micro-programs to accelerate/decelerate it.
This LSI also controls the speed of the space motor in agreement with each print mode.
(d) I/O port
This printer has 8-bit output port which is used for controlling the SRAM.
(e) Head position count
It counts the outputs from slit sensors (SPPHASE A, B) located on the space motor to
keep monitoring the current position of the print head.
(f) Print data modifying function
It modifies the print data stored in the DRAM with command inputs from the MPU.
(h) DMA control function
It outputs a DMA request to the MPU, simultaneously controlling the DMA.
This LSI is connected in multiplex to the MPU.
40496501TH Rev.118
MPU CLOCK
ALE
MPUMain LSI
A16~BHE
AD0~AD15
ALE
RD
WR
CS
CLK
A16~BHE
AD0~AD15
RD
AD0~AD15
WR
CS
A16~BHE
A0–A15D0–D15
A0–A15D0–D15
Figure 2.6
40496501TH Rev.119
(7) NHDC LSI(IC27: TC190G08CF-7036)
This LSI controls timer, interruption, memories, printing, external interface, motor drive
interface.
(a) Timer control
It controls the watchdog timer for detecting any out-of-control program, baud rate
generator for setting the baud rate of the serial interface, and pulse generation timer for
AG plus count.
(b) Interruption control
It controls LSI inside interruptions, external interruptions and interruptions from an
external interface as outputs for the MPU.
(c) Memory control
DRAM and SRAM control, chip select output control of ROM, flash memory and MUPIS,
and bank switch control for expanding their memory spaces.
(d) Print control
It creates a print timing corresponding to the print DPI to control the possition and print
correction for pins.
This also controls the print Mask and DMAC which reads print data from the memory and
transmits it to the print output buffer.
(e) External interface
It controls various interfaces for main LSI, IEEE1284, serial, MUPIS, OpePaneLSI,
EEPROM.
(f) Motor drive interface
Each control of OVDV pulse generation for AG motor, generation of pulse for switching
ribbon motor phase, and OVDV pulse generation for LF motor.
(8) Sub LSI (IC17, IC18: MSM72V017)
This LSI is the I/O port LSI which controls the input/output of various controlling signals with
command inputs from the MPU.
(a) Sub LSI #1 (IC17: MSM72V017)
Input/output control for controlling signals to various sensors, FAN controlling signals,
sensor slice level controlling signals, AG motor controlling signals, and LF motor
controlling signals.
(b) Sub LSI #2 (IC18: MSM72V017)
Input/output control for controlling signals to various sensors, SP motor current controlling signals, external interface controlling signals, TR motor controlling signals, bail motor
controlling signals, cutter motor (for optional connection) controlling signals.
(9) Serial I/F LSI (IC35: 85L30)
This LSI is the serial I/F LSI which controls the input/output of serial I/F controlling signals with
command inputs from the MPU.
40496501TH Rev.120
2.1.3Initialization
This printer is initialized when the power is tumed on or when the I-PRIME-N signal is input from
the host side via the parallel interface.
For the initialize operation, the RESET-N signal is first output from the reset circuit to reset the MPU
and LSIs. When resetting ends, the program starts and the LSIs are reset by NHDC LSI via
LRESET-N. Reset operation by I-PRIME starts program to initialize, but does not reset the MPU.
The program here sets the mode of the LSI including the MPU, checks the memories (ROMs and
RAMs), then carries out carriage homing, and determines the LF motor phase.
Finally, the program establishes the interface signals (P-I/F: ACK-P signal sending, and S-I/F:
BUSY-N signal off) and lights the SELECT lamp to inform the ready state for receiving to the host
side and ends the initialize operation.
Start
MPU RESET
MPU
Initial Setting
Internal RAM
CHECK
Serial
I/F
I/F BUSY OFF
ROM CHECK
LSI RESET
External RAM
CHECK
LSI Initial Setting
and I/F Busy ON
RAM Clear
Carriage Homing
LF Motor Phase
Initialization
Parallel
I/F
I/F ACK Send
End
Figure 2.7
40496501TH Rev.121
2.1.4Interface control
The PM4410 is provided with the centronics parallel interface and RS-232C serial interface as
standard features.Also, it can be connected to option OKI HSP or Opt. Card. The interface cable
can be connected simultaneously with these interfaces.
These interfaces can be switched with the menu switch on the operation panel, in addition, you can
designate auto-select for them. The MPU communicates with hosts through the NHDC according
to the selected interface mode. The selected interface is stored to the EEPROM and can maintain
even after powering the printer off.
2.1.5Parallel Interface Control
The Parallel data input from the host to the NHDC LSI is latched to its internal register at the falling
or rising edge of the STROBE-N signal.
At the same time, the LSI sets the BUSY signal to the high level to inform the host that the data
is being processed, and outputs the INT-P signal to inform the MPU of data reception. The data
is read upon receiving the RD-N signal from the MPU.
When the data processing ends, the BUSY signal is set to off and the ACK-N signal in sent to
request the next data. When reception is impossible because the buffer is full, the BUSY signal is
sent to request stopping of data transmission.
Data
1 to 8
STROBE
BUSY
MPUNHDC LSI
BSYP
A/D bus
ACKN
PSBN
INT-P
INTINT
oror
500ns max.
Line
driver
receiver
Parallel I/F
BUSY
ACK-N
STB-N
ACK
2~8µs
INT
Figure 2.8
40496501TH Rev.122
2.1.6Serial Interface
The MPU sets the baud rate which is selected with the menu switch for the NHDC LSI and have
the serial I/F LSI to output the clock frequency of the baud rate.
Input signals from the serial I/F (DSR, CTS, CD and RD) are converted into TTL level ones by the
Line driver/receiver and input to the serial I/F LSI and NHDC LSI. The serial I/F LSI converts serial
data into parallel data to output it to the MPU.
Output signals (DTR, RTS, SSD and TD) to the serial I/F are output from the MPU to the NHDC
LSI and serial I/F LSI, and then converted through the Line driver/receiver into line voltage which
is output to the serial I/F.
AD0-AD7
MPUNHDC LSI
DSR
RD
STSP
TCK0
RTSN
SSDN
DTRN
CTSN
DSRN
DCDN
Serial I/F LSI
CLK
RXDA
TXDA
Line
driver
receiver
Serial I/F
TD
RD
RTS
SSD
DTR
CTS
DSR
CD
SSD
Figure 2.9
40496501TH Rev.123
2.1.7Printing operation
The time chart for the spacing and printing, line feed operations are as shown below.
The spacing, printing and line feed operations are controlled by the MPU. The MPU also controls
the entire timing of these operations.
Acceleration
Constant speed
Deceleration
SP Motor
Operation
Printing
Print
Line Feed
LF
Figure 2.10
When starting the printing operation, the MPU specifies the distance moved, print start position,
printing speed, etc. to the LSI, and activates the spacing motor. The MPU, when the carriage
arrives at the print position specified, activates the printer to start printing, and when printing
terminates, the MPU activates the line feed motor for line feed operation. During the line feed
operation, the MPU causes the carriage to decelerate. Upon termination of line feed operation, the
spacing operation is performed.
40496501TH Rev.124
2.1.8Printhead control
The printhead is controlled by the Main LSI and NHDC LSI.
Printing is synchronized with the ITOUT signal from the NHDC LSI.
Control Board
The NHDC LSI outputs the dot timing1 signals (DT1:1~18) and the dot timing2 signals (DT2:1~18),
and the driver IC drives each dot magnet. These signals are output from the NHDC LSI after the
following corrections for final driving time determination inside the LSI:
(1) Correction for the number of pins driven
MPUNHDC LSI
A/D bus
Main LSI
TFA-N
TFD-N
Print Data
HEAD1-P~
HEAD18-P
Figure 2.11
Driver Board
DRIVER
Print Data
HEAD1~
HEAD18
Print Head
The driving time is corrected according to the number of pins driven at the same time out of
18 pins.
(2) Correction according to adjacent pin drive timing
The driving time is adjusted by checking whether the pin adjacent to the pin to be driven is
driven on the previous timing.
(3) Correction for head gap
The driving time is corrected according to the head gap.
40496501TH Rev.125
DT2 Basic drive time
(3)
Dot magnet drive
coil current
signals
DT
1
(D1–D18)
signals
DT
2
(D1–D18)
Basic drive time
DT
1
Figure 2.12
(1)+(2)+(3)
40496501TH Rev.126
2.1.9Print Compensation Control
The print compensation can be made as shown below:
(a) Simultaneous Compensation of the number of impact pins
The NHDC LSI is provided with the compensation table for each pin to make necessary
compensation.
Number of impact pinsFewMany
Drive timeShortLong
(b) Duty control
1. If the number of the lines which exceeds 60% printing duty is continuous 8 lines, the printer
starts 2-path printing at the 8th line.
2. If the printer can activate 12 pins simultaneously in a line, it 2-path prints the line.
According to the thickness of the printing medium, the print mode is compensated as shown
in the table below:
Head Gap Range12345
Print speed100%97%95%90%89%
Drive timeShortLong
(Drive time lengthens at each step.)
2.1.10 Space motor control
(1) The Main LSI generates the SPDV-P signal upon receiving the spacing command from the
MPU. This is a fixed cycle pulse signal.
The Main LSI varies the pulse duty according to the speed data from the MPU to control the
motor speed.
The SPFOW-P or SPREV-P signal from the Main LSI changes the current direction in the DC
motor to run the motor in the forward or reverse direction.
SPFOW-P
SPREV-P
SPDV-P
MotorCurrent
Figure 2.13
40496501TH Rev.127
(2) Slit encoder
As the space motor rotates, it generates feedback pulse signals SPA-P and SPB-P. The Main
LSI detects the edge pulses from these signals and multiplies the frequency to output the
S720-P signals as the normalized timing to NHDC LSI to generate head drive timing.
SPA-P
SPB-P
Edge pulse
S720-P
UTILITY MODE
ITOUT 10CPI
ITOUT 12CPI
ITOUT 15CPI
ITOUT 17CPI
ITOUT 20CPI
2.1.11 Line feed
1/360"
1/120"
1/144"
1/180"
1/206"
1/240"
Figure 2.14
The LF motor is locked by the current supplied from +12V according to the pulse duty of the
LFCHOP-P signal during the stop period.
It is driven by +44V application by the LFOVDV-P signal for line feed operation.
LFø1
LFø2
LFø3
LFø4
LFOVDV-P
LFCHOP-P
Figure 2.15
40496501TH Rev.128
2.1.12 Bail, tractor switching, AG, ribbon motor control
Bail, tractor switching, AG and ribbon motor control is as shown below.
The AG motor is locked with AGHOLD-P.
MO ø1
MO ø2
MO ø3
MO ø4
MO OVDV
AGHOLD-P
Figure 2.16
40496501TH Rev.129
2.1.13 Operation Panel
The clock synchronization OPCLK of NHDC LSI is used to input the switch data and output the LED
data and LCD data through the operation panel control LSI (IC1: BU6152S).
NHDC LSI
SCKN
SCSN
SDO
SDI
OPDATAOUT-P
56
OPSCLK-N
59
OPSQCR-N
58
OPDATAIN-P
57
BU6152S
Command
and Data
latch
LED driver
+5V
Switch
controller
Figure 2.17
A 2-byte (15 bits + 1 even parity bit) command (OPDATAOUT-P) is transmitted to the LSI
(BU6152S) in synchronization with the OPSCLK-N signal. The LSI decodes this command and
when it is found to be legal, returns a 2-byte command response back to the NHDC LSI which
includes data on Switch information, LED status, LCD status receive command ACK/NAK and 1
odd parity bit.
Any transmission errors found cause the command to be reissued after the transmission of the
OPSQCR-N signal.
40496501TH Rev.130
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