OKI MSM82C51A-2RS, MSM82C51A-2GS-K, MSM82C51A-2JS Datasheet

E2O0017-27-X2

¡ Semiconductor MSM82C51A-2RS/GS/JS

¡ Semiconductor

This version: Jan. 1998

Previous version: Aug. 1996

MSM82C51A-2RS/GS/JS

UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER

GENERAL DESCRIPTION

The MSM82C51A-2 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication. As a peripheral device of a microcomputer system, the MSM82C51A-2 receives parallel data from the CPU and transmits serial data after conversion. This device also receives serial data from the outside and transmits parallel data to the CPU after conversion. The MSM82C51A-2 configures a fully static circuit using silicon gate CMOS technology. Therefore, it operates on extremely low power at 100 mA (max) of standby current by suspending all operations.

FEATURES

• Wide power supply voltage range from 3 V to 6 V

• Wide temperature range from –40°C to 85°C

• Synchronous communication upto 64 Kbaud

• Asynchronous communication upto 38.4 Kbaud

• Transmitting/receiving operations under double buffered configuration.

• Error detection (parity, overrun and framing)

• 28-pin Plastic DIP (DIP28-P-600-2.54): (Product name: MSM82C51A-2RS)

• 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C51A-2JS)

• 32-pin Plastic SSOP(SSOP32-P-430-1.00-K): (Product name: MSM82C51A-2GS-K)

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¡ Semiconductor MSM82C51A-2RS/GS/JS

FUNCTIONAL BLOCK DIAGRAM

D

7 - D0

RESET

CLK

C/D

RD

WR

DSR DTR

CTS

RTS

CS

Data Bus

Buffer

Read/Write

Control

Logic

Modem Control

Transmit

Buffer

(P - S)

Transmit

Control

Internal Bus Line

Recieve

Buffer

(S - P)

Recieve

Control

TXD

TXRDY TXE

TXC

RXD

RXRDY

RXC

SYNDET/BD

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¡ Semiconductor MSM82C51A-2RS/GS/JS

PIN CONFIGURATION (TOP VIEW)

28 pin Plastic DIP

D

TXC

WR

CS

D

1

2

D

2

3

RXD

3

GND

4

D

5

4

D

6

5

D

7

6

8

D

7

9

TXC

10

RXRDY

RXD

NC

GND

TXC

WR

C/D

RXRDY

D

CS

NC

RD

WR

CS

C/D

RD

2

3

4

5

6

7

11

12

13

14

32 pin Plastic SSOP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

28 pin Plastic QFJ

RXD 3

3D2D1

D 2

1

GND 4

5

4

6

5

7

6

8

7

9

10

11

12

13

14

15

RD

C/D

TXRDY

RXRDY

0

CC

D

V

28

27

26

16

17

18

CTS

SYNDET/BD

TXEMPTY

25

24

23

22

21

20

19

RXC

DTR

RTS

DSR

RESET

CLK

TXD

28

D

27

26

V

25

RXC

24

DTR

23

RTS

22

DSR

RESET

21

20

CLK

TXD

19

TXEMPTY

18

CTS

17

SYNDET/BD

16

TXRDY

15

1

0

CC

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

D

1

D

0

V

CC

NC

RXC

DTR

RTS

DSR

RESET

CLK

TXD

TXEMPTY

NC

CTS

SYNDET/BD

TXRDY

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¡ Semiconductor MSM82C51A-2RS/GS/JS

FUNCTION

Outline

The MSM82C51A-2's functional configuration is programed by software. Operation between the MSM82C51A-2 and a CPU is executed by program control. Table 1 shows the operation between a CPU and the device.

Table 1 Operation between MSM82C51A and CPU

CS

C/D

1

0

0 0

0

RD

¥ ¥

1 1

0

WR

¥

1

0 1

0

1

¥

1

1 0

1

0

Data Bus 3-State

Data Bus 3-State Status Æ CPU Control Word ¨ CPU Data Æ CPU Data ¨ CPU

It is necessary to execute a function-setting sequence after resetting the MSM82C51A-2. Fig. 1 shows the function-setting sequence. If the function was set, the device is ready to receive a command, thus enabling the transfer of data by setting a necessary command, reading a status and reading/writing data.

External Reset

Internal Reset

Write Mode Instruction

Asynchronous

no

Write First Sync

Charactor

Single

Sync Mode

no

Write Second Sync

Charactor

End of Mode Setting

yes

Fig. 1 Function-setting Sequence (Mode Instruction Sequence)

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¡ Semiconductor MSM82C51A-2RS/GS/JS

)

Control Words

There are two types of control word.

1. Mode instruction (setting of function)

2. Command (setting of operation)

1) Mode Instruction

Mode instruction is used for setting the function of the MSM82C51A-2. Mode instruction will be in “wait for write” at either internal reset or external reset. That is, the writing of a control word after resetting will be recognized as a “mode instruction.” Items set by mode instruction are as follows:

• Synchronous/asynchronous mode

• Stop bit length (asynchronous mode)

• Character length

• Parity bit

• Baud rate factor (asynchronous mode)

• Internal/external synchronization (synchronous mode)

• Number of synchronous characters (Synchronous mode)

The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous mode, it is necessary to write one-or two byte sync characters. If sync characters were written, a function will be set because the writing of sync characters constitutes part of mode instruction.

D

S

D

7

1

6

S

1

D

EP PEN L

D

5

D

4

D

3

2

D

2

L

B

1

D

1

0

B

2

1

Baud Rate Factor

0 1 0 1

0 0 1 1

Refer to

Fig. 3 SYNC

0 1 0

0 0 1

5 bits 6 bits 7 bits

0 1 0 1

0 0 1 1

Disable

1 ¥ 16 ¥ 64 ¥

Charactor Length

Odd

Parity

Parity Check

Disable

1

8 bits

Even

Parity

Stop bit Length

0 1 0

0 0 1

Inhabit 1 bit 1.5

bits

Fig. 2 Bit Configuration of Mode Instruction (Asynchronous

1

2 bits

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¡ Semiconductor MSM82C51A-2RS/GS/JS

)

D

7

SCS ESD EP PEN L

D

6

D

5

D

4

D

3

2

D

2

L

1

0 0

D

0

Charactor Length

0 1 0

0 0 1

5 bits 6 bits 7 bits

1

8 bits

Parity

0 1 0 1

0 0 1 1

Disable

Odd

Parity

Disable

Even

Parity

Synchronous Mode

0 1

Internal

Synchronization

External

Synchronization

Number of Synchronous Charactors

0 1

2 Charactors 1 Charactor

Fig. 3 Bit Configuration of Mode Instruction (Synchronous

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¡ Semiconductor MSM82C51A-2RS/GS/JS

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2) Command

Command is used for setting the operation of the MSM82C51A-2. It is possible to write a command whenever necessary after writing a mode instruction and sync characters. Items to be set by command are as follows:

• Transmit Enable/Disable

• Receive Enable/Disable

• DTR, RTS Output of data.

• Resetting of error flag.

• Sending to break characters

• Internal resetting

• Hunt mode (synchronous mode)

The bit configuration of a command is shown in Fig. 4.

D

EH

D

7

IR

D

6

RTS

D

5

ER

D

4

SBRK

D

3

RXE

D

2

DTR

D

1

0

TXEN

1ºTransmit Enable 0ºDisable

DTR

1 Æ DTR = 0 0 Æ DTR = 1

1ºRecieve Enable 0ºDisable

1ºSent Break Charactor 0ºNormal Operation

1ºReset Error Flag 0ºNormal Operation

RTS

1 Æ RTS = 0 0 Æ RTS = 1

1ºInternal Reset 0ºNormal Operation

1ºHunt Mode (Note) 0ºNormal Operation

Note: Seach mode for synchronous

charactors in synchronous mode.

. 4 Bit Configuration of Command

Fi

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¡ Semiconductor MSM82C51A-2RS/GS/JS

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Status Word

It is possible to see the internal status of MSM82C51A-2 by reading a status word. The bit configuration of status word is shown in Fig. 5.

D

DSR

D

7

SYNDET

/BD

D

6

FE

D

5

OE

D

4

PE

3

D

2

TXEMPTY

D

1

RXRDY

D

0

TXRDY

Parity Different from TXRDY Terminal. Refer to "Explanation" of TXRDY Terminals.

Same as terminal. Refer to "Explanation" of Terminals.

1ºParity Error

1ºOverrun Error

1ºFraming Error

Note:

Only asynchronous mode. Stop bit cannot be detected.

Shows Terminal DSR 1ºDSR = 0 0ºDSR = 1

Fi

. 5 Bit Configuration of Status Word

Standby Status

It is possible to put the MSM82C51A-2 in “standby status” When the following conditions have been satisfied the MSM82C51A-2 is in “standby status.”

(1) CS terminal is fixed at Vcc level. (2) Input pins other CS , D0 to D7, RD, WR and C/D are fixed at Vcc or GND level (including

SYNDET in external synchronous mode).

Note: When all output currents are 0, ICCS specification is applied.

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