OKI MSM63238-xxx, MSM63238-xxxGS-BK, MSM63238-xxxTS-K Datasheet
E2E0027-38-95
¡ Semiconductor MSM63238
¡ Semiconductor
This version: Sep. 1998
Previous version: Mar. 1996
MSM63238
4-Bit Microcontroller with Built-in POCSAG Decoder and Melody Circuit, Operating at
0.9 V (Min.)
GENERAL DESCRIPTION
The MSM63238 is a CMOS 4-bit microcontroller with a built-in POCSAG (Post Office Code
Standardization Advisory Group) decoder.
The MSM63238 employs Oki's original nX-4/250 CPU core and is suitable for pager applications.
The MSM63P238 is a one-time-programmable ROM-version product having one-time PROM
(OTP) as internal program memory.
The specifications of the MSM63P238 are equal to those of the MSM63238 except for electrical
characteristics, packaging (only 80-pin flat package is available for the MSM63P238), and some
functions.
FEATURES
• Rich instruction set
439 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock : 32.768 kHz/38.4 kHz/76.8 kHz crystal oscillator
High-speed clock : 2 MHz (Max.) RC or ceramic oscillator select
• Program memory space
16K words
Basic instruction length is 16 bits/1 word
• Data memory space
1K nibbles
• External data memory space
64 Kbytes (expandable by using an I/O port)
1/32
¡ Semiconductor MSM63238
• Stack level
Call stack level : 16 levels
Register stack level : 16 levels
• POCSAG decoder
Data rate : 512 bps/1200 bps/2400 bps
User frame : 3 types
User address : 6 types
Battery saving mode (for controlling intermittent operations of RF receiver)
• I/O ports
Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/
high-impedance input
Output ports: Selectable as P-channel open drain output/N-channel open drain output/
CMOS output/high-impedance output
Input-output ports: Selectable as input with pull-up resistance/input with pull-down
resistance/high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output/high-impedance output
Can be interfaced with external peripherals that use a different power supply than this device
uses.
Number of ports:
Input port : 1 port ¥ 4 bits
Output port : 6 ports ¥ 4 bits
Input-output port : 5 ports ¥ 4 bits
1 port ¥ 2 bits
• Melody output function
Melody sound frequency : 529 to 2979 Hz
Tone length : 63 types
Tempo : 15 types
Note data : Resides in the program memory
Buzzer drive signal output : 4 kHz
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
Criterion voltage : Can be selected as 1.05 ±0.10 V, 1.30 ±0.15 V,
2.20 ±0.20 V or 2.80 ±0.30 V
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
2/32
¡ Semiconductor MSM63238
• Timers and counter
8-bit timer ¥ 4
Selectable as auto-reload mode/capture mode/clock frequency measurement mode
Watchdog timer ¥ 1
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Serial port
Mode : UART mode, synchronous mode
UART communication speed : 1200 bps, 2400 bps, 4800 bps, 9600 bps
Clock frequency in synchronous mode : 32.768 kHz (internal clock mode), external
clock frequency
Data length : 5 to 8 bits
• Interrupt sources
External interrupt : 3
Internal interrupt : 15 (watchdog timer interrupt is a nonmask-
able interrupt)
• Operating voltage
When backup used : 0.9 to 2.7 V
(Low-speed clock operating)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
When backup not used : 1.8 to 5.5 V
(Operating frequency: 300 to 500 kHz)
2.2 to 5.5 V
(Operating frequency: 300 kHz to 1 MHz)
2.7 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
• Package options:
80-pin plastic QFP (QFP80-P-1420-0.80-BK) : (Product name: MSM63238-xxxGS-BK)
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) : (Product name: MSM63238-xxxTS-K)
Chip : MSM63238-xxx
xxx indicates a code number.
3/32
¡ Semiconductor MSM63238
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function. and indicate that the power is
supplied from V
V
to the circuits corresponding to signal names inside . (V
DDR
for interface)
TIMING
CONTROL
CBR
EBR
to the circuits corresponding to the signal names inside , and from
DDI
H
nX-4/250
L
YX
RA
and V
DDI
PC
A
ROM
16KW
: power supply
DDR
SP
RSP
STACK
CAL.S: 16-level
REG.S: 16-level
RESET
TST1
TST2
TST3
XTM0
XTM1
XT0
XT1
OSC0
OSC1
TBCCLK*
HSCLK*
XTSEL0
XTSEL1
V
DDH
V
DD
V
DDL
V
DD2
CB1
CB2
ALU
INSTRUCTION
DECODER
RST
TST
OSC
BACKUP
Internal
PORT
P0.0-P0.3
P8.2, P8.3
PE.0-PE.3
PF.0-PF.3
INT
C G
RAM
1024N
INT
INT
4
INT
1
3
MIE
IR
TBC
BLD
WDT
Z
BUS
CONTROL
DATA BUS
4
2
1
3
1
INT
INT
INT
INT
INT
EXTMEM
TIMER
8bit ¥ 4
SIO
MELODY
I/O
PORT
INPUT
PORT
OUTPUT
PORT
D0-7*
A0-15*
RD*
WR*
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
RXC*
TXC*
RXD*
TXD*
MD
P8.0, P8.1
P9.0-P9.3
PA.0-PA.3
PB.0-PB.3
PC.0-PC.3
PD.0-PD.3
P1.0-P1.3
P7.0-P7.3
P6.0-P6.3
P5.0-P5.3
P4.0-P4.3
P3.0-P3.3
P2.0-P2.3
SIGIN
BS1
BS2
POCSAG
Dec
V
DDI
V
DDR
4/32
¡ Semiconductor MSM63238
PIN CONFIGURATION (TOP VIEW)
P9.0
P9.1
P9.2
P9.3
PA.0
PA.1
PA.2
PA.3
P4.0
P4.1
P4.2
P4.3
P5.0
P5.2
79
P5.1
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P5.3
80
(NC)
P6.0
P6.1
P6.2
P6.3
P7.0
P7.1
P7.2
P7.3
BS1
BS2
SIGIN
V
DDR
XT0
XT1
TST1
TST2
TST3
OSC0
OSC1
XTSEL0
XTSEL1
XTM0
XTM1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P8.1
(NC)
P8.0
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
P1.3
P1.2
P1.1
P1.0
PB.3
PB.2
PB.1
PB.0
PC.3
PC.2
PC.1
PC.0
(NC)
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SS
(NC)
DD2
V
DDL
V
DDH
V
CB1
CB2
V
DD
MD
V
RESET
(NC)
DDI
V
PD.0
PD.1
PD.2
80-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
40
PD.3
5/32
¡ Semiconductor MSM63238
PIN CONFIGURATION (TOP VIEW) (continued)
(NC)
P6.0
(NC)
P5.3
(NC)
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
999897969594939291
100
90
89 P4.0
88 (NC)
87 PA.3
86 PA.2
85 PA.1
84 PA.0
83 (NC)
82 P9.3
81 P9.2
80 P9.1
79 P9.0
78 (NC)
77 P8.1
76 (NC)
1
P6.1
2
P6.2
3
P6.3
4
P7.0
5
P7.1
6
(NC)
7
P7.2
8
P7.3
9
(NC)
10
BS1
11
BS2
12SIGIN
13(NC)
14V
DDR
15XT0
16XT1
17(NC)
18TST1
19TST2
20TST3
21OSC0 55 (NC)
22OSC1
23XTSEL0
24XTSEL1
25(NC)
75
P8.0
74
P3.3
73
P3.2
72
P3.1
71
(NC)
70
P3.0
69
P2.3
68
P2.2
67
P2.1
66
(NC)
65
P2.0
64 P1.3
63 (NC)
62 P1.2
61 P1.1
60 (NC)
59 P1.0
58 PB.3
57 PB.2
56 PB.1
54 PB.0
53 PC.3
52 PC.2
51 PC.1
2627282930313233343536
DD2VDDL
DDH
(NC)
XTM0
XTM1
(NC)
(NC)
V
CB1
V
CB2
DD
V
37VSS38MD
39RESET
40(NC)
41(NC)
42V
DDI
43PD.0
44PD.1
45PD.2
46PD.3
100-Pin Plastic TQFP
Note: Pins marked as (NC) are no-connection pins which are left open.
47(NC)
48PC.0
49(NC)
50(NC)
6/32
¡ Semiconductor MSM63238
PAD CONFIGURATION
Pad Layout
PC.2 39
PC.3 40
PB.0 41
PB.1 42
PB.2 43
PB.3 44
P1.0 45
P1.1 46
P1.2 47
P1.3 48
P2.0 49
P2.1 50
P2.2 51
P2.3 52
P3.0 53
P3.1 54
P3.2 55
P3.3 56
P8.0 57
PC.138
PC.037
PD.336
PD.235
PD.134
PD.033
DDI
V
32
RESET31
MD30
SS
V
29
DD
V
28
CB227
CB126
DDH
V
25
DDL
V
24
DD2
V
23
XTM122
XTM021
XTSEL120
11
XTSEL019
OSC118
OSC017
TST316
TST215
TST114
XT113
XT012
V
SIGIN10
BS29
BS18
P7.37
P7.26
P7.15
P7.04
P6.33
P6.22
P6.11
DDR
P8.1 58
P9.0 59
P9.1 60
P9.2 61
P9.3 62
PA.0 63
PA.1 64
PA.2 65
PA.3 66
P4.0 67
P4.1 68
P4.2 69
P4.3 70
P5.0 71
P5.1 72
P5.2 73
P5.3 74
Chip Size : 4.55 mm ¥ 4.55 mm
Chip Thickness : 350 mm (typ.)
Coordinate Origin : Chip center
Pad Hole Size : 110 mm ¥ 110 mm
Pad Size : 120 mm ¥ 120 mm
Minimum Pad Pitch : 150 mm
Note: The chip substrate voltage is VSS.
Y
P6.0 75
X
7/32
¡ Semiconductor MSM63238
Pad Coordinates
Pad No. Y (µm)X (µm)Pad Name
1 –1897.72123.6P6.1
2 –1701.4P6.2
3 –1505.4P6.3
4 –1231.1P7.0
5 –1034.8P7.1
6 –838.8P7.2
7 –642.5P7.3
8 –446.2BS1
9 –250.2BS2
10 –54.0SIGIN
11 142.0V
DDR
12 338.3XT0
13 495.0XT1
14 691.3TST1
15 887.2TST2
16 1083.6TST3
17 1279.8OSC0
18 1436.5OSC1
19 1819.3XTSEL0
20 2031.2XTSEL1
21 1609.4XTM0
22 1452.8XTM1
23 938.6V
24 782.0V
25 625.3V
DD2
DDL
DDH
26 468.6CB1
27 312.0CB2
28 155.4V
29 –1.3V
DD
SS
30 –219.4MD
31 –405.6RESET
32 –592.2V
DDI
33 –778.4PD.0
34 –964.9PD.1
35 –1151.2PD.2
36 –1337.7PD.3
37 –1523.9PC.0
38 –2031.2PC.1
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2123.6
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
2107.3
Pad No.
39 1810.6–2123.6PC.2
40 1618.5PC.3
41 1264.2PB.0
42 1072.2PB.1
43 880.1PB.2
44 688.0PB.3
45 496.0P1.0
46 303.9P1.1
47 111.8P1.2
48 –80.6P1.3
49 –272.7P2.0
50 –464.8P2.1
51 –656.8P2.2
52 –848.9P2.3
53 –1041.0P3.0
54 –1233.1P3.1
55 –1529.1P3.2
56 –1721.2P3.3
57 –1913.3P8.0
58 –1552.5P8.1
59 –1370.2P9.0
60 –1187.6P9.1
61 –1005.2P9.2
62 –822.9P9.3
63 –640.6PA.0
64 –458.2PA.1
65 –275.9PA.2
66 –93.6PA.3
67 88.7P4.0
68 271.0P4.1
69 453.4P4.2
70 635.7P4.3
71 818.0P5.0
72 1000.3P5.1
73 1182.7P5.2
74 1365.0P5.3
75 2042.0P6.0
Y (µm)X (µm)Pad Name
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2123.6
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
–2107.3
8/32
¡ Semiconductor MSM63238
PIN DESCRIPTIONS
The basic functions of each pin of the MSM63238 are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
For pin, "GS-BK" denotes an 80-pin flat package (80QFP) and "TS-K" a 100-pin flat package
(100TQFP).
Table 1 Pin Descriptions (Basic Functions)
Function Symbol Type Description
Pin
31
32
13
TS-K
36
37
14
—
—
—
Positive power supply
Negative power supply
Interface power supply for SIGIN, BS1, BS2
V
V
V
GS-BK
DD
SS
DDR
Positive power supply pin for external interface
V
DDI
36
42
—
(power supply for input, output, and I/O ports)
Positive power supply pin for internal logic (internally generated).
Power
Supply
V
V
DDL
DD2
27
26
32
31
—
—
A capacitor (0.1 mF) should be connected between this pin and V
Positive power supply pin for low-speed clock (internally generated)
Voltage multiplier pin for power supply backup
(internally generated).
V
DDH
CB1 Pins to connect a capacitor for voltage multiplier.
CB2
XT0 I
28
29
30
14
33
34
35
15
—
—
—
A capacitor (1.0 mF) should be connected between this pin
SS
.
and V
A capacitor (1.0 mF) should be connected between CB1 and CB2.
Clock oscillation pins for POCSAG decoder.
A 32.768 kHz, 38.4 kHz, or 76.8 kHz crystal and capacitor (C
XT1 O
XTM0 I
15
23
16
27
should be connected to these pins.
Low-speed clock oscillation pins for CPU.
A 32.768 kHz crystal and capacitor (C
Oscillation
XTM1 O
OSC0 I
24
19
28
21
to these pins.
High-speed clock oscillation pins.
A ceramic resonator and capacitors (C
OSC1 O
20
22
oscillation resistor (R
) should be connected to these pins.
OS
Low-speed CPU clock select pins.
Test
XTSEL0
XTSEL1
TST1 Input pins for testing.
TST2 I
TST3
21
22
16
17
18
23
24
18
19
20
These pins are used to select a low-speed CPU clock.
I
Because these are high impedance inputs, be sure to tie these
pins to V
or VSS.
DD
Pull-down resistors are internally connected to these pins.
The user cannot use these pins.
) should be connected
GM
, CL1) or external
L0
SS
.
)
G
9/32
¡ Semiconductor MSM63238
Table 1 Pin Descriptions (Basic Functions) (continued)
33
10
11
12
50
51
52
Pin
TS-KGS-BK
Reset input pin.
Setting this pin to "H" level puts this device into a reset state.
hen, setting this pin to "L" level starts executing an instruction
39
38
10
11
12
59
61
62
64
T
from address 0000H.
A pull-down resistor is internally connected to this pin.
Battery saving outputs.
O
Signals to control intermittent operations of RF receiver.
Receive data input pin.
Input pin for receive data from RF receiver.
4-bit input port.
Pull-up resistor input, pull-down resistor input, or
high-impedance input is selectable for each bit.
I
Function Symbol Type Description
Reset 34
Melody
POCSAG
Decoder
RESET I
MD O Melody output pin (normal phase)
BS1
BS2
SIGIN I
P1.0/INT5
P1.1/INT5
P1.2/INT5
P1.3/INT5 53
Port
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
P4.0/A0
P4.1/A1
P4.2/A2
P4.3/A3
P5.0/A4
P5.1/A5
P5.2/A6
P5.3/A7
P6.0/A8
P6.1/A9
P6.2/A10
P6.3/A11
P7.0/A12
P7.1/A13
P7.2/A14
P7.3/A15 9
54
55
56
57
58
59
60
61
73
74
75
76
77
78
79
80
65
67
68
69
70
72
73
74
89
90
91
92
93
94
95
97
2
3
4
5
6
7
8
99
1
2
3
4
5
7
8
4-bit output ports.
P-channel open drain output, N-channel open drain output,
O
CMOS output, or high-impedance output is selectable for each
bit.
O
O
O
O
O
10/32
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