OKI MSM63182A-xxx, MSM63182A-xxxGS-K Datasheet
E2E0055-19-41
¡ Semiconductor MSM63182A
This version: Apr. 1999
¡ Semiconductor
MSM63182A
4-Bit Microcontroller with Built-in 512-Dot Matrix LCD Drivers, Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The MSM63182A is an enhanced version of the MSM63182 in which supply currents have been
improved.
The MSM63182A is a CMOS 4-bit microcontroller with built-in 512-dot matrix LCD drivers and
operates at 0.9 V (min.). The MSM63182A is suitable for applications such as games, toys,
watches, etc. which are provided with an LCD display.
The MSM63182A is an M6318x series mask ROM-version product of OLMS-63K family, which
employs Oki's original CPU core nX-4/250.
The MSM63P180 is the one-time-programmable ROM version of MSM63188/A, having one-time
PROM (OTP) as internal program memory.
The MSM63P180 is used to evaluate the software development.
FEATURES
• Rich instruction set
439 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock : 32.768 kHz crystal oscillator
High-speed clock : 2 MHz (Max.) RC or ceramic oscillator select
• Program memory space
4K words
Basic instruction length is 16 bits/1 word
• Data memory space
384 nibbles
• External data memory space
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¡ Semiconductor MSM63182A
64 Kbytes (expandable by using an I/O port)
• Stack level
Call stack level : 8 levels
Register stack level : 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/
high-impedance input
Output ports: Selectable as P-channel open drain output/N-channel open drain output/
CMOS output/high-impedance output
Input-output ports: Selectable as input with pull-up resistance/input with pull-down
resistance/high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output/high-impedance output
Can be interfaced with external peripherals that use a different power supply than this device
uses.
Number of ports:
Input port : 2 ports ¥ 4 bits
Output port : 4 ports ¥ 4 bits
Input-output port : 3 ports ¥ 4 bits
• Buzzer function
Buzzer output : 0.946 to 5.461 kHz (adjustable in 15 steps)
Buzzer output modes : Intermittent sound 1, 2; simple sound; continu-
ous sound
• LCD driver
Number of segments : 512 Max. (32 SEG ¥ 16 COM)
1/1 to 1/16 duty
1/4 or 1/5 bias (regulator built-in)
Selectable as all-on mode/all-off mode/power down mode/normal display mode
Adjustable contrast
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
Criterion voltage : Can be selected as 1.05 ±0.10 V, 1.30 ±0.15 V,
2.20 ±0.20 V or 2.80 ±0.30 V
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
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¡ Semiconductor MSM63182A
• Timers and counter
Watchdog timer ¥ 1
Overflows in 2 sec.
100 Hz timer ¥ 1
Measurable in steps of 1/100 sec.
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Interrupt sources
External interrupt : 2
Internal interrupt : 6 (watchdog timer interrupt is a nonmask-
able interrupt)
• Operating voltage
When backup used : 0.9 to 2.7 V
(Low-speed clock operating)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
When backup not used : 1.8 to 5.5 V
(Operating frequency: 300 to 500 kHz)
2.2 to 5.5 V
(Operating frequency: 300 kHz to 1 MHz)
2.7 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
• Package:
128-pin plastic QFP (QFP128-P-1420-0.50-K) : (Product name: MSM63182A-xxxGS-K)
Chip : (Product name: MSM63182A-xxx)
xxx indicates a code number.
Differences Between the MSM63182 and the MSM63182A
The MSM63182A has the following improved characteristics.
• Supply currents (I
• The V
voltage during a halt of high-speed clock oscillation
DDL
DD1
, I
DD2
, I
) in DC characteristics
DD3
3/27
¡ Semiconductor MSM63182A
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function. indicates that the power is supplied
to the circuits corresponding to the signal names inside from V
interface).
nX-4/250
L
TIMING
CONTROL
CBR
EBR
H
YX
RA
PC
A
ROM
4KW
(power supply for
DDI
SP
RSP
STACK
CAL: 8-level
REG: 16-level
RESET
TST1
TST2
XT0
XT1
OSC0
OSC1
V
DDH
V
DD
CB1
CB2
V
DD1
V
DD2
V
DD3
V
DD4
V
DD5
C1
C2
V
DDL
RST
TST
OSC
BACK
UP
BIAS
ALU
INSTRUCTION
DECODER
INT
4
INT
1
INT
1
CG
MIE
IR
RAM
384N
INT182
TBC
BLD
100HzTC
WDT
Z
BUS
CONTROL
DATA BUS
EXTMEM
BUZZER
INT
1
INPUT
PORT
OUTPUT
PORT
I/O
PORT
INT
1
LCD
&
DSPR
D0-7*
A0-15*
RD*
WR*
BD
BDB
P0.0-P0.3
P1.0-P1.3
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3
P7.0-P7.3
P8.0-P8.3
P9.0-P9.3
PA.0-PA.3
COM1-16
SEG0-31
V
DDI
V
SS
4/27
¡ Semiconductor MSM63182A
PIN CONFIGURATION (TOP VIEW)
DDI
BDBBDP7.0
P7.1
P7.2
(NC)
(NC)
(NC)
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
V
(NC)
(NC)
(NC)
(NC)
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
(NC)
(NC)
(NC)
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
1
1
110
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39404142434445464748495051525354555657585960616263
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
(NC)
(NC)
(NC)
P7.3
P6.0
P6.1
P6.2
P6.3
P1.0
P1.1
P1.2
P1.3
PA.0
PA.1
PA.2
PA.3
P9.0
P9.1
P9.2
P9.3
P8.0
P8.1
P8.2
P8.3
P0.0
P0.1
P0.2
P0.3
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
(NC)
(NC)
(NC)
(NC)
(NC)
SS
DD1VDD2VDD3VDD4VDD5
V
V
C1
C2
DDH
V
CB1
V
CB2
DD
DDL
V
OSC1
OSC0
XT1
XT0
RESET
TST2
TST1
P5.3
(NC)
128-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
(NC)
(NC)
5/27
¡ Semiconductor MSM63182A
PAD CONFIGURATION
Pad Layout
DD
75 P5.3
73 TST2
74 TST1
70 RESET
71 XT1
72 XT0
DDL
67 V
68 OSC1
69 OSC0
66 V
65 CB2
63 V
64 CB1
DDH
61 C1
62 C2
DD5
60 V
59 V
DD4
DD2
DD3
57 V
58 V
DD1
SS
56 V
55 V
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P0.3
P0.2
P0.1
P0.0
P8.3
P8.2
P8.1
P8.0
P9.3
P9.2
P9.1
P9.0
PA.3
PA.2
PA.1
PA.0
P1.3
P1.2
P1.1
P1.0
P6.3
P6.2
P6.1
P6.0
P7.3
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
54 SEG0
53 SEG1
52 SEG2
51 SEG3
50 SEG4
49 SEG5
48 SEG6
47 SEG7
46 SEG8
45 SEG9
44 SEG10
43 SEG11
42 SEG12
41 SEG13
40 SEG14
39 SEG15
38 SEG16
37 SEG17
36 SEG18
35 SEG19
34 SEG20
33 SEG21
32 SEG22
31 SEG23
30 SEG24
29 SEG25
28 SEG26
27 SEG27
26 SEG28
25 SEG29
24 SEG30
23 SEG31
Y
123456789
DDI
BD
V
P7.0
P7.1
BDB
COM1
P7.2
COM3
COM2
11
10
COM5
COM4
13
12
COM7
COM6
15
14
COM9
COM8
17
16
18
COM10
COM12
COM11
192120
COM15
COM14
COM13
22
COM16
Chip Size : 4.44 mm ¥ 4.92 mm
Chip Thickness : 350 mm (typ.)
Coordinate Origin : Chip center
Pad Hole Size : 100 mm ¥ 100 mm
Pad Size : 110 mm ¥ 110 mm
Minimum Pad Pitch : 140 mm
Note: The chip substrate voltage is VSS.
X
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¡ Semiconductor MSM63182A
Pad Coordinates
Pad No.
Pad
Name
X (µm) Y (µm)
1 P7.2 –1547 –2265
2 P7.1 –1407 –2265
3 P7.0 –1267 –2265
4 BD –1090 –2265
5 BDB –950 –2265
6V
DDI
–810 –2265
7 COM1 –630 –2265
8 COM2 –490 –2265
9 COM3 –350 –2265
10 COM4 –210 –2265
11 COM5 –70 –2265
12 COM6 70 –2265
13 COM7 210 –2265
14 COM8 350 –2265
15 COM9 490 –2265
16 COM10 630 –2265
17 COM11 770 –2265
18 COM12 910 –2265
19 COM13 1050 –2265
20 COM14 1190 –2265
21 COM15 1330 –2265
22 COM16 1470 –2265
23 SEG31 2075 –2170
24 SEG30 2075 –2030
25 SEG29 2075 –1890
26 SEG28 2075 –1750
27 SEG27 2075 –1610
28 SEG26 2075 –1470
29 SEG25 2075 –1330
30 SEG24 2075 –1190
31 SEG23 2075 –1050
32 SEG22 2075 –910
33 SEG21 2075 –770
34 SEG20 2075 –630
35 SEG19 2075 –490
36 SEG18 2075 –350
Pad No.
Pad
Name
X (µm) Y (µm) Pad No.
37 SEG17 2075 –210
38 SEG16 –70
39 SEG15 70
40 SEG14 210
41 SEG13 350
42 SEG12 490
43 SEG11 630
44 SEG10 770
45 SEG9 910
46 SEG8 1050
47 SEG7 1190
48 SEG6 1330
49 SEG5 1470
50 SEG4 1610
51 SEG3 1750
52 SEG2 1890
53 SEG1 2030
54 SEG0 2170
55 V
56 V
57 V
58 V
59 V
60 V
SS
DD1
DD2
DD3
DD4
DD5
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
1575 2265
1425 2265
1275 2265
1125 2265
975 2265
825 2265
61 C1 675 2265
62 C2 525 2265
63 V
DDH
375 2265
64 CB1 225 2265
65 CB2 75 2265
66 V
67 V
DD
DDL
–75 2265
–225 2265
68 OSC1 –375 2265
69 OSC0 –525 2265
70 RESET –675 2265
71 XT1 –825 2265
72 XT0 –975 2265
Pad
Name
X (µm) Y (µm)
73 TST2 –1247 2265
74 TST1 –1387 2265
75 P5.3 –1548 2265
76 P5.2 2170
77 P5.1 2030
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105 –1890
P5.0
P4.3
P4.2
P4.1
P4.0
P0.3
P0.2
P0.1
P0.0
P8.3
P8.2
P8.1
P8.0
P9.3
P9.2
P9.1
P9.0
PA.3
PA.2
PA.1
PA.0
P1.3
P1.2
P1.1
P1.0
P6.3
P6.2
P6.1
106 P6.0 –2030
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
1890
1750
1610
1470
1330
1190
1050
910
770
630
490
350
210
70
–70
–210
–350
–490
–630
–770
–910
–1050
–1190
–1330
–1470
–1610
–1750
107 P7.3 –2075 –2170
7/27
¡ Semiconductor MSM63182A
PIN DESCRIPTIONS
The basic functions of each pin of the MSM63182A are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
Table 1 Pin Descriptions (Basic Functions)
Function Symbol Pin Type
V
V
V
V
V
V
V
DD
SS
DD1
DD2
DD3
DD4
DD5
52 —
41 —
42
43
44 —
45
46
C1 47 —
Power
Supply
C2 48 —
V
V
V
DDI
DDL
DDH
110 —
53 —
49 —
CB1 50 —
CB2 51 —
XT0 58 I
XT1 57 O
Oscillation
OSC0 55 I
OSC1 54 O
TST1 60 I
Test
TST2 59 I
Reset RESET 56 I
Description
Positive power supply
Negative power supply
Power supply pins for LCD bias (internally generated).
Capacitors (0.1 mF) should be connected between these pins and
.
V
SS
Capacitor connection pins for LCD bias generation.
A capacitor (0.1 mF) should be connected between C1 and C2.
Positive power supply pin for external interface
(power supply for input, output, and input-output ports)
Positive power supply pin for internal logic (internally generated).
A capacitor (0.1 mF) should be connected between this pin and V
SS
.
Voltage multiplier pin for power supply backup (internally generated).
A capacitor (1.0 mF) should be connected between this pin and VSS.
Pins to connect a capacitor for voltage multiplier.
A capacitor (1.0 mF) should be connected between CB1 and CB2.
Low-speed clock oscillation pins.
A 32.768 kHz crystal should be connected between XT0 and XT1,
and C
(5 to 25 pF) should be connected between XT0 and VSS.
G
High-speed clock oscillation pins.
A ceramic resonator and capacitors (C
oscillation resistor (R
) should be connected to these pins.
OS
, CL1) or external
L0
Input pins for testing.
A pull-down resistor is internally connected to these pins.
The user cannot use these pins.
Reset input pin.
Setting this pin to "H" level puts this device into a reset state.
Then, setting this pin to "L" level starts executing an instruction
from address 0000H.
A pull-down resistor is internally connected to this pin.
Buzzer
BD 108 O
BDB 109 O
Buzzer output pin (non-inverted output)
Buzzer output pin (inverted output)
8/27
¡ Semiconductor MSM63182A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol
P0.0/INT5
P0.1/INT5
P0.2/INT5
P0.3/INT5
P1.0/INT5
P1.1/INT5
P1.2/INT5
P1.3/INT5
P4.0/A0
P4.1/A1
P4.2/A2
P4.3/A3
P5.0/A4
P5.1/A5
P5.2/A6
P5.3/A7
P6.0/A8
P6.1/A9
Port
P6.2/A10
P6.3/A11
P7.0/A12
P7.1/A13
P7.2/A14
P7.3/A15
P8.0/RD
P8.1/WR
P8.2
P8.3/INT4
P9.0/D0
P9.1/D1
P9.2/D2
P9.3/D3
PA.0/D4
PA.1/D5
PA.2/D6
Pin
78
77
76
75
94
93
92
91
74
73
72
71
70
69
68
61
98
97
96
95
107
106
105
99
82
81
80
79
86
85
84
83
90
89
88
Type Description
4-bit input ports.
Pull-up resistor input, pull-down resistor input, or
I
high-impedance input is selectable for each bit.
I
4-bit output ports.
P-channel open drain output, N-channel open drain output,
O
CMOS output, or high-impedance output is selectable for each
bit.
O
O
O
4-bit input-output ports.
In input mode, pull-up resistor input, pull-down resistor input,
I/O
or high-impedance input is selectable for each bit.
In output mode, P-channel open drain output, N-channel open
drain output, CMOS output, or high-impedance output is
selectable for each bit.
I/O
I/O
PA.3/D7
87
9/27
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