OKI MSM5265GS-BK, MSM5265GS-K Datasheet

E2B0008-27-Y2

¡ Semiconductor

This version: Nov. 1997

Previous version: Mar. 1996

MSM5265¡ Semiconductor

MSM5265

80-DOT LCD DRIVER

GENERAL DESCRIPTION

The MSM5265 is an LCD driver which can directly drive up to 80 segments in the static display
mode and up to 160 segments in the 1/2 duty dynamic display mode.

The MSM5265 is fabricated with low power CMOS metal gate technology. The MSM5265
consists of a 160-stage shift register, 160-bit data latch, 80 pairs of LCD drivers and a common
signal generator.

The display data is serially input from the DATA-IN pin to the 160-stage shift register synchronized
with the CLOCK pulse. The data is shifted into the 160-bit data latch by the LOAD signal. Then
the latched data is directly output to the LCD from the 80 pairs of LCD drivers as a serial output.

The common signal can be generated by the built-in generator, or externally input. The common
synchronization circuit which is used in the dynamic display mode is integrated on the chip.

FEATURES

• Supply voltage : 3.0 to 6.0 V

• Drives LCD of up to 80 segments (in the static display mode)

• Drives LCD of up to 160 segments (in the 1/2 duty dynamic display mode)

• Simple interface with microcomputer

• Bit-to-bit correspondence between input data and output data
H: Display ON L: Display OFF

• Can be cascade-connected

• Built-in common signal generator

• Can be synchronized with the external common signal

• Testing pins for all-on (SEG-TEST) and all-off (BLANK)

• Applicable as an output expander

• LCD driving voltage can be adjusted by the combination of V

• Package options:

100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name : MSM5265GS-K)
100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name : MSM5265GS-BK)

LC1

and V

LC2

1/18

BLOCK DIAGRAM

MSM5265¡ Semiconductor

To LCD panel

SEG-TEST

BLANK

V

GND

LOAD

DATA-IN

CLOCK

D/S

OSC-OUT

OSC-OUT

OSC-IN

SEG

1

SEG

80

80-Dot Segment Driver

80

80-Ch Data Selector

DD

80-Stage Shift Register

80 80

(A)

80-Bit Data Latch

(A)

(B)

80-Bit Data Latch

(B)

80-Stage Shift Register

DATA-OUT 2

DATA-OUT 1

V

LC1

OSC 1/4 or 1/8 1/2

Common
Driver

V

LC2

COM-A

EXT/INT

SYNC

SYNC
Circuit

COM-B

COM-OUT

2/18

PIN CONFIGURATION (TOP VIEW)

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

95

96

97

98

99

100

SEG43

SEG44

93

94

SEG41

SEG42

91

92

SEG39

SEG40

89

90

SEG37

SEG38

87

88

SEG35

SEG36

85

86

SEG33

SEG34

83

84

SEG31

SEG32

81

82

MSM5265¡ Semiconductor

SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1
2
3
4
5
6
7
8
9

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1

32

31

LOAD

CLOCK

34

33

DATA-IN

DATA-OUT1

42

41

40

39

38

37

36

35

DD

D/S

V

GND

OSC-IN

EXT/INT

OSC-OUT

OSC-OUT

DATA-OUT2

100-Pin Plastic QFP

45

44

43

SYNC

BLANK

SEG-TEST

48

47

46

LC1

V

COM-A

COM-OUT

50

49

LC2

V

COM-B

3/18

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit

Supply Voltage

Input Voltage

Storage Temperature

T

V

DD

V

STG

I

= 25°C

T

a

= 25°C

T

a

—

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Range Unit

Supply Voltage

Operating Temperature

LCD Driving Voltage

• Oscillation circuit

V

V

T

DD

op

LCD

—

—

VDD–V

LC2

–0.3 to +6.5 V

GND–0.3 to VDD +0.3

–55 to +150

3 to 6 V

–40 to +85

3 to V

DD

MSM5265¡ Semiconductor

V

°C

°C

V

Parameter Min.

Symbol Condition Typ. Max. UnitCorresponding pin

Oscillator Resistance

Oscillator Capacitance 0.001C

Current Limiting Resistance 0.56R

Common Signal Frequency 25f

R

0

COM

OSC-OUT

C

0

0

0

1

— 100 220 kWOSC-OUT

Film capacitor — 0.047 mFOSC-OUT

R1≥10 R

56R

0

1 2.2 MWOSC-IN

COM-A

COM-B

— — 150 Hz

(MSM5265)

OSC-OUT

R

1

OSC-IN

4/18

ELECTRICAL CHARACTERISTICS
DC Characteristics

Parameter Symbol Condition Applicable pinMin. Typ. Max. Unit

MSM5265¡ Semiconductor

= 5.0 V Ta =–40 to +85°C)

(V

DD

"H" Input
Voltage

"L" Input
Voltage

Input
Leakage
Current

"H" Output
Voltage

"M" Output
Voltage

V

IH

—

36 — V

DD

V

SEG-TEST, BLANK,

V

IL

—

GND — 1.0 V

LOAD, DATA-IN, CLOCK,
D/S, EXT/INT, OSC-IN

I

IL

V

= 5.0 V/0 V

I

——±1mA

DATA-OUT1

V

OH

I

= –100 mA 4.5 — — V

O

DATA-OUT2
COM-OUT

= –200 mA 4.5 — — V

I

O

V

= 2.5 V, V

LC1

I

= –30 mA

O

V

= 2.5 V, V

LC1

I

= –150 mA

O

V

= 2.5 V, V

V

OM

LC1

I

= ±150 mA

O

LC2

LC2

LC2

= 0 V

= 0 V

= 0 V

4.8 — — V

4.8 — — V

2.3 — 2.7 V

OSC-OUT

OSC-OUT

SEG1-SEG

COM-A
COM-B

COM-A
COM-B

80

"L" Output
Voltage

Output
Leakage
Current

Segment
Output
Impedance

DATA-OUT1

V

OL

I

= 100 mA — — 0.5 V

O

DATA-OUT2
COM-OUT

I

= 200 mA — — 0.5 V

O

V

= 2.5 V, V

LC1

I

= 30 mA

O

V

= 2.5 V, V

LC1

I

= 150 mA

O

I

= 250 mA — — 0.8 V

O

LC2

LC2

= 0 V

= 0 V

— — 0.2 V SEG

— — 0.2 V

OSC-OUT

OSC-OUT

- SEG

1

COM-A
COM-B

SYNC

80

VO= 5 V

I

LO

R

SEG

when internal Tr is off

V

LC1

V

LC2

= (5+V

= 0 to 2 V

LC2

)/2

—— 5 mA

— — 10 kW

SYNC

SEG

- SEG

1

80

5/18

MSM5265¡ Semiconductor

Parameter

Common Output
Impedance

Static Supply
Current

Symbol

R

COM

I

DD1

Dynamic Supply
Current

I

DD2

Switching Characteristics

Parameter Symbol Condition Min. Max. Unit Applicable Pin

Clock Frequency f

Clock Pulse "H" Time f

Clock Pulse "L" Time f

Data Setup Time f

Data Hold Time f

"H"‚ "L" Propagation

Delay Time

LOAD Pulse "H" Time t

Clock Æ LOAD Time t

OSC-IN Input Frequency f

Condition Min. Typ. Max. Unit

= (5+V

V

LC1

V

= 0 to 2 V

LC2

Fix all input levels at
either V

or GND

DD

LC2

)/2

— — 1.5 kW

——

No load.
R

= 100 kW,

0

C

= 0.01 mF, R1 = 1 MW

0

—

(VDD = 3.0 to 6.0 V Ta = –40 to +85°C)

f

fH

fL

D–f

f–D

— — 1 MHz

— 0.3 — ms CLOCK

— 0.5 — ms

— 0.1 — ms DATA-IN

— 0.1 — ms

Load capacitance of

t

t

OSC

PHL

PLH

f–L

DATA-OUT1, DATA-OUT2:

L

— 0.8 ms

15 pF

— 0.2 — ms LOAD

— 0.1 — ms CLOCK

— — 5 kHz OSC-IN

100 mA

0.5 mA0.12

Applicable Pin

COM-A
COM-B

V

DD

CLOCK

DATA-OUT1

DATA-OUT2

CLOCK

LOAD

SYNC Pulse "L" Time t

DATA-IN

CLOCK

LOAD

DATA-OUT

DATA-OUT

SYNC

1

2

s

V

L

— 0.2 — ms SYNC

V

H

V

L

t

V

H

V

D-f

L

t

f-D

t

fH

= 0.8 V

H

V

H

V

L

t

t

f-L

V

H

V

L

t

s

V

= 0.2 VDD)

,

DD

L

L

V

H

V

L

V

H

V

L

V

H

V

L

t

PHL

t

PLH

V

L

(V

t

fL

6/18