OKI MSM51V18165F-70TS-K, MSM51V18165F-70TS-L, MSM51V18165F-70JS, MSM51V18165F-50TS-K, MSM51V18165F-50TS-L Datasheet
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No.
1/14
Semiconductor
M SM51V18165F
1,048,576-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM51V18165F is a 1,048,576-word ´ 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS
technology. The MSM51V18165F achieves high integration, high-speed operation, and low-power consumption
because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The
MSM51V18165F is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP.
FEATURES
· 1,048,576-word ´ 16-bit configuration
· Single 3.3V power supply, ±0.3V tolerance
· Input : LVTTL compatible, low input capacitance
· Output : LVTTL compatible, 3-state
· Refresh : 1024 cycles/16ms
· Fast page mode with EDO, read modify write capability
· CAS before RAS refresh, hidden refresh, RAS-only refresh capability
· CAS before RAS self-refresh capability
· Package options:
42-pin 400mil plastic SOJ (SOJ42-P-400-1.27) (Product : MSM51V18165F-xxJS)
50/44-pin 400mil plastic TSOP (TSOPII50/44-P-400-0.80-K) (Product : MSM51V18165F-xxTS-K)
(TSOPII50/44-P-400-0.80-L) (Product : MSM51V18165F-xxTS-L)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.) Power Dissipation
Family
t
RAC
t
AA
t
CAC
t
OEA
Cycle Time
(Min.)
Operating (Max.) Standby (Max.)
50ns 25ns 13ns 13ns 84ns 324mW
60ns 30ns 15ns 15ns 104ns 288mWMSM51V18165F
70ns 35ns 20ns 20ns 124ns 252mW
1.8mW
This version:Oct.1999
No.
2/14
PIN CONFIGRATION (TOP VIEW)
Pin Name Function
A0–A9 Address Input
RAS Row Address Strobe
LCAS Lower Byte Column Address Strobe
UCAS Upper Byte Column Address Strobe
DQ1–DQ16 Data Input/Data Output
OE Output Enable
WE Write Enable
V
CC
Power Supply (3.3V)
V
SS
Ground (0V)
NC No Connection
Note : The same power supply voltag e m ust be prov ided to ev ery VCC pin, and the same
GND voltage level must be provided to every V
SS
pin.
42-Pin Plastic SOJ
55/44-Pin Plastic TSOP
(K Type)
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
DQ1
DQ2
DQ3
DQ4
V
CC
V
CC
A3
V
SS
V
SS
V
SS
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
A9
A8
A7
A6
NC
A0
A1
A2
DQ5
DQ6
DQ7
DQ8
NC
NC
NC
WE
RAS
NC
NC
A5
A4
LCAS
UCAS
OE
22
23
24
25
29
28
27
26V
CC
NC
55/44-Pin Plastic TSOP
(L Type)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
DQ1
DQ2
DQ3
DQ4
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
A9
A8
A7
A6
A0
A1
A2
A3
DQ5
DQ6
DQ7
DQ8
NC
NC
WE
RAS
NC
NC
NC
A5
A4
LCAS
UCAS
OE
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
DQ1
DQ2
DQ3
DQ4
V
CC
V
CC
A4
V
SS
V
SS
V
CC
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
A9
A8
A0
A1
NC
A7
A6
A5
DQ5
DQ6
DQ7
DQ8
NC
NC
NC
WE
RAS
NC
NC
A2
A3
LCAS
UCAS
OE
22
23
24
25
29
28
27
26V
SS
NC
No.
3/14
BLOCK DIAGRAM
FUNCTION TABLE
Input Pin DQ Pin
RAS LCAS UCAS WE OE DQ1-DQ8 DQ9-DQ16
Function Mode
H * * * * High-Z High-Z Standby
L H H * * High-Z High-Z Refresh
LLHHL D
OUT
High-Z Lower Byte Read
LHLHLHigh-Z D
OUT
Upper Byte Read
LLLHL D
OUT
D
OUT
Word Read
LLHLH DINDon’t Care Lower Byte Write
L H L L H Don’t Care D
IN
Upper Byte Write
LLLLH D
IN
D
IN
Word Write
L L L H H High-Z High-Z
¾
* : “H” or “L”
A0-A
9
8
8
8
8
8
8
8
16
8
16
10
1010
10
Timing
Generator
Column
Address
Buffers
I/O
Controller
Internal
Address
Counter
Row
Address
Buffers
Refresh
Control Clock
I/O
Controller
Column Decoders
Sense Amplifiers
Memory
Cells
Word
Drivers
Row
Deco-
ders
I/O
Selector
Input
Buffers
Input
Buffers
Output
Buffers
Output
Buffers
DQ1-DQ
8
DQ9-DQ
16
OE
WE
RAS
LCAS
UCAS
VCCV
SS
On Chip
V
BB
Generator
On Chip
IV
CC
Generator
No.
4/14
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to V
SS
VIN, V
OUT
- 0.5 to VCC + 0.3
V
Voltage VCC Supply relative to V
SS
V
CC
- 0.5 to 4.6
V
Short Circuit Output Current
I
OS
50 mA
Power Dissipation
P
D*
1W
Operating Temperature
T
opr
0 to 70 °C
Storage Temperature
T
stg
- 55 to 150
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0 °C to 70 °C)
Parameter Symbol Min. Typ. Max. Unit
V
CC
3.0 3.3 3.6 V
Power Supply Voltage
V
SS
000V
Input High Voltage
V
IH
2.0
¾
V
CC
+ 0.3
*1
V
Input Low Voltage
V
IL
- 0.3
*2
¾
0.8 V
Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which V
CC
is applied).
*2. The input voltage is V
SS
- 1.0V when the pulse width is less than 20ns (the pulse width respect to
the point at which V
SS
is applied).
Capacitance
(VCC = 3.3V ± 0.3V, Ta = 25°C, f=1MHz)
Parameter Symbol Typ. Max. Unit
Input Capacitance (A0 - A9)
C
IN1
¾
5pF
Input Capacitance
(RAS, LCAS, UCAS, WE, OE)
C
IN2
¾
7pF
Output Capacitance (DQ1 - DQ16)
C
I/O
¾
7pF
No.
5/14
DC Characteristics
(VCC = 3.3V ± 0.3V, Ta = 0°C to 70°C)
MSM51V18165
F-50
MSM51V18165
F-60
MSM51V18165
F-70
Parameter
Symbol
Condition
Min. Max. Min. Max. Min. Max.
Unit Note
Output High Voltage
V
OH
IOH = -2.0mA
2.4
V
CC
2.4
V
CC
2.4
V
CC
V
Output Low Voltage
V
OLIOL
= 2mA
00.400.400.4V
Input Leakage
Current
I
LI
0V £ VI £ VCC+0.3V;
All other pins not
under test = 0V
- 10
10
- 10
10
- 10
10
mA
Output Leakage
Current
I
LO
DQ disable
0V £ V
O
£ V
CC
- 10
10
- 10
10
- 10
10
mA
Average Power
Supply Current
(Operating)
I
CC1
RAS, CAS cycling,
t
RC
= Min.
¾
90
¾
80
¾
70 mA 1,2
RAS, CAS = V
IH
¾
2
¾
2
¾
2
Power Supply
Current
(Standby)
I
CC2
RAS, CAS
³ V
CC
- 0.2V
¾
0.5
¾
0.5
¾
0.5
mA 1
Average Power
Supply Current
(RAS-only Refresh)
I
CC3
RAS cycling,
CAS = V
IH
,
t
RC
= Min.
¾
90
¾
80
¾
70 mA 1,2
Power Supply
Current
(Standby)
I
CC5
RAS = VIH,
CAS = V
IL
,
DQ = enable
¾
5
¾
5
¾
5mA1
Average Power
Supply Current
(CAS before RAS
Refresh)
I
CC6
RAS = cycling,
CAS before RAS
¾
90
¾
80
¾
70 mA 1,2
Average Power
Supply Current
(Fast Page Mode)
I
CC7
RAS = VIL,
CAS cycling,
t
HPC
= Min.
¾
90
¾
80
¾
70 mA 1,3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = V
IL
.
3. The address can be changed once or less while CAS = V
IH
.
No.
6/14
AC Characteristic (1/2)
(VCC = 3.3V ±
0.3
V, Ta = 0°C to 70°C) Note1,2,3
MSM51V18165
F-50
MSM51V18165
F-60
MSM51V18165
F-70
Parameter Symbol
Min. Max. Min. Max. Min. Max.
Unit Note
Random Read or Write Cy cle Time
t
RC
84
¾
104
¾
124
¾
ns
Read Modify Write Cycle Time
t
RWC
110
¾
135
¾
160
¾
ns
Fast Page Mode Cycle Time
t
HPC
20
¾
25
¾
30
¾
ns
Fast Page Mode Read Modify
Write Cycle Time
t
HPRWC
58
¾
68
¾
78
¾
ns
Access Time from RAS
t
RAC
¾
50
¾
60
¾
70 ns 4, 5, 6
Access Time from CAS
t
CAC
¾
13
¾
15
¾
20 ns 4,5
Access Time from Column Address
t
AA
¾
25
¾
30
¾
35 ns 4,6
Access Time from CAS Precharge
t
CPA
¾
30
¾
35
¾
40 ns 4,13
Access Time from OE
t
OEA
¾
13
¾
15
¾
20 ns 4
Output Low Impedance Time from
CAS
t
CLZ
0
¾
0
¾
0
¾
ns 4
Data Output Hold After CAS Low
t
DOH
5
¾
5
¾
5
¾
ns
CAS to Data Output Buffer Turnoff Delay Time
t
CEZ
013015020ns7,8
RAS to Data Output Buffer Turnoff Delay Time
t
REZ
013015020ns7,8
OE to Data Output Buffer Turn-off
Delay Time
t
OEZ
013015020ns7
WE to Data Output Buffer Turnoff Delay Time
t
WEZ
013015020ns7
Transition Time
t
T
150150150ns3
Refresh Period
t
REF
¾
16
¾
16
¾
16 ms
RAS Precharge Time
t
RP
30
¾
40
¾
50
¾
ns
RAS Pulse Width
t
RAS
50 10,000 60 10,000 70 10,000 ns
RAS Pulse Width
(Fast Page Mode with EDO)
t
RASP
50 100,000 60 100,000 70 100,000 ns
RAS Hold Time
t
RSH
7
¾
10
¾
13
¾
ns
RAS Hold Time referenced to OE
t
ROH
7
¾
10
¾
13
¾
ns
CAS Precharge Time
(Fast Page Mode with EDO)
t
CP
7
¾
10
¾
10
¾
ns 15
CAS Pulse Width
t
CAS
7 10,000 10 10,000 13 10,000 ns
CAS Hold Time
t
CSH
35
¾
40
¾
45
¾
ns
CAS to RAS Precharge Time
t
CRP
5
¾
5
¾
5
¾
ns 13
RAS Hold Time from CAS Precharge
t
RHCP
30
¾
35
¾
40
¾
ns 13
No.
7/14
AC Characteristic (2/2)
(VCC = 3.3V ± 0.3V, Ta = 0°C to 70°C) Note1,2,3
MSM51V18165
F-50
MSM51V18165
F-60
MSM51V18165
F-70
Parameter Symbol
Min. Max. Min. Max. Min. Max.
Unit Note
OE Hold Time from CAS
(DQ Disable)
t
CHO
5
¾
5
¾
5
¾
ns
RAS to CAS Delay Time
t
RCD
11 37 14 45 14 50 ns 5
RAS to Column Address Delay Time
t
RAD
9 2512301235ns6
Row Address Set-up Time
t
ASR
0
¾
0
¾
0
¾
ns
Row Address Hold Time
t
RAH
7
¾
10
¾
10
¾
ns
Column Address Set-up Time
t
ASC
0
¾
0
¾
0
¾
ns 12
Column Address Hold Time
t
CAH
7
¾
10
¾
13
¾
ns 12
Column Address to RAS Lead Time
t
RAL
25
¾
30
¾
35
¾
ns
Read Command Set-up Time
t
RCS
0
¾
0
¾
0
¾
ns 12
Read Command Hold Time
t
RCH
0
¾
0
¾
0
¾
ns 9,12
Read Command Hold Time
referenced to RAS
t
RRH
0
¾
0
¾
0
¾
ns 9
Write Command Set-up Time
t
WCS
0
¾
0
¾
0
¾
ns 10,12
Write Command Hold Time
t
WCH
7
¾
10
¾
13
¾
ns 12
Write Command Pulse Width
t
WP
7
¾
10
¾
10
¾
ns
WE Pulse Width (DQ Disable)
t
WPE
7
¾
10
¾
10
¾
ns
OE Command Hold Time
t
OEH
7
¾
10
¾
13
¾
ns
OE Precharge Time
t
OEP
7
¾
10
¾
10
¾
ns
OE Command Hold Time
t
OCH
7
¾
10
¾
10
¾
ns
Write Command to RAS Lead Time
t
RWL
7
¾
10
¾
13
¾
ns
Write Command to CAS Lead Time
t
CWL
7
¾
10
¾
13
¾
ns 14
Data-in Set-up Time
t
DS
0
¾
0
¾
0
¾
ns 11,12
Data-in Hold Time
t
DH
7
¾
10
¾
13
¾
ns 11,12
OE to Data-in Delay Time
t
OED
13
¾
15
¾
20
¾
ns
CAS to WE Delay Time
t
CWD
30
¾
34
¾
44
¾
ns 10
Column Address to WE Delay Time
t
AWD
42
¾
49
¾
59
¾
ns 10
RAS to WE Delay Time
t
RWD
67
¾
79
¾
94
¾
ns 10
CAS Precharge WE Delay Time
t
CPWD
47
¾
54
¾
64
¾
ns 10
CAS Active Delay Time from RAS
Precharge
t
RPC
5
¾
5
¾
5
¾
ns 12
RAS to CAS Set-up Time
(CAS before RAS)
t
CSR
5
¾
5
¾
5
¾
ns 12
RAS to CAS Hold Time
(CAS before RAS)
t
CHR
10
¾
10
¾
10
¾
ns 13
No.
8/14
Notes: 1. A start-up delay of 200ms is required after power-up, followed by a minimum of eight initializ ation
cycles(RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume t
T
= 2ns.
3. V
IH
(Min.) and VIL (Max.) are reference levels for measuring input tim ing signals. Transition tim es
(t
T
) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100pF.
The output timing reference levels are V
OH
= 2.0V and VOL = 0.8V.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.)
limit, then the access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.)
limit, then the access time is controlled by t
AA
.
7. t
CEZ
(Max.), t
REZ
(Max.), t
WEZ
(Max.), and t
OEZ
(Max.) define the time at which the output achieved
the open circuit condition and are not referenced to output voltage levels.
8. t
CEZ
, and t
REZ
must be satisfied for open circuit condition.
9. t
RCH
or t
RRH
must be satisfied for a read cycle.
10. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If t
WCS
³ t
WCS
(Min.), then the cycle is an early write
cycle and the data out will rem ain open circuit (high im pedance) throughout the entire cycle. If t
CWD
³ t
CWD
(Min.), t
RWD
³ t
RWD
(Min.), t
AWD
³ t
AWD
(Min.) and t
CPWD
³ t
CPWD
(Min.), then the cycle is a
read modify write cycle and data out will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the UC AS and LCAS, leading edges in an early write cy cle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
12. These parameters are determined by the falling edge of either UCAS or LCA S, whichever is earlier.
13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.
14. t
CWL
should be satisfied by both UCAS and LCAS.
15. t
CP
is determined by the time both UCAS and LCAS are high.
1R1
<247
Timing Chart
x Read Cycle
x Write Cycle (Early Write)
t
CEZ
t
CLZ
t
CAC
t
OEA
t
ASC
t
RRH
t
RAH
t
ASR
t
RAD
t
RAL
t
CRP
t
CAH
t
CRP
t
RCD
t
RC
Row
t
RAS
t
RP
t
CSH
t
RSH
t
CAS
Column
t
RAC
t
AA
t
RCS
t
ROH
Valid Data-out
t
RCH
t
REZ
t
OEZ
Open
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
OH
V
OL
“H” or “L”
t
WCS
t
WCH
t
CWL
t
ASR
t
RAH
t
ASC
t
CRP
t
RP
t
RC
t
RAS
t
DH
t
RWL
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
CAH
t
RAD
t
RAL
t
DS
t
WP
Valid Data-in
Row Column
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
IH
V
IL
“H” or “L”
Open
1R1
43247
x Read Modify Write Cycle
t
DH
t
DS
t
OEZ
t
CLZ
t
OED
t
AA
t
OEH
t
RWD
t
CWD
t
CWL
t
RWL
t
CAH
t
ASC
t
ASR
t
RAH
t
RAD
t
CRP
t
RCD
t
RSH
t
CAS
t
CRP
t
CAC
t
CSH
t
RAC
t
OEA
t
RCS
t
AWD
t
WP
t
RWC
t
RAS
t
RP
Valid
Data-out
Row Column
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
I/OH
V
I/OL
“H” or “L”
Valid
Data-in
1R1
44247
x Fast Page Mode Read Cycle (Part-1)
x Fast Page Mode Read Cycle (Part-2)
t
HPC
t
CEZ
t
CAC
t
DOH
t
CAC
t
CPA
t
AA
t
RCH
t
RCS
t
OEA
t
RAC
t
AA
t
RCS
t
CRP
t
ASR
t
CAH
t
ASC
t
RAH
t
RAD
t
ASC
t
CP
t
ASC
t
CAH
t
CAS
t
CP
t
CAS
t
RHCP
t
CSH
t
RCD
t
CLZ
t
CAH
t
AA
t
WEZ
t
CAC
t
CAS
t
RP
t
RASP
t
WPE
Valid
Data-out
Valid
Data-out
Valid *
Data-out
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
OH
V
OL
Row Column Column Column
“H” or “L”
t
AA
t
OEP
t
CHO
t
CAC
t
OEP
t
CAC
t
CPA
t
AA
t
OEA
t
AA
t
RAC
t
RRH
t
OCH
t
CAH
t
ASC
t
RAH
t
RAD
t
RCS
t
ASR
t
ASC
t
CAH
t
CP
t
CAS
t
HPC
t
RASP
t
CAS
t
CP
t
CSH
t
CRP
t
CLZ
t
CAH
t
OEA
t
OEA
t
OEZ
t
CAC
t
ASC
t
RP
t
RHCP
t
CAS
t
DOH
t
OEZ
t
REZ
t
RCD
Valid
Data-out
Valid *
Data-out
Valid *
Data-out
Valid
Data-out
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
OH
V
OL
Row Column Column Column
“H” or “L”* : Same Data,
1R1
45247
x Fast Page Mode Write Cycle (Early Write)
x Fast Page Mode Read Modify Write Cycle
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
WCH
t
WCS
t
WCStWCH
t
WCH
t
WCS
t
ASC
t
CAH
t
ASC
t
CAH
t
RAD
t
ASR
t
ASC
t
RAH
t
RCD
t
CRP
t
CAS
t
CAS
t
RSH
t
CP
t
CAS
t
RP
t
HPC
t
CSH
t
CAH
t
CP
t
HPC
t
RASP
Valid *
Data-in
Valid *
Data-in
Valid *
Data-in
“H” or “L”
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
IH
V
IL
Row Column Column Column
t
OED
t
DH
t
OEZ
t
OEH
t
CAC
t
OED
t
DH
t
OEZ
t
OEH
t
AWD
t
AWD
t
WP
t
DS
t
AA
t
DS
t
CWD
t
RCS
t
RAH
t
CAH
t
ASR
t
RAD
t
HPRWC
t
CPA
t
CWL
t
CAH
t
ASC
t
CP
t
RWL
t
RWD
t
CWD
t
RCD
t
CRP
t
RASP
t
OEA
t
RCS
t
ASC
t
WP
t
CPWD
t
RAC
t
CAC
Valid
Data-in
Valid
Data-out
t
CLZ
Valid
Data-in
Valid
Data-out
t
CLZ
Column
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
I/OH
V
I/OL
Row Column
“H” or “L”
1R1
46247
x RAS-Only Refresh Cycle
x CAS before RAS Refresh Cycle
t
ASRtRAH
t
CRP
t
RPC
t
RP
t
RAS
t
RC
t
CEZ
RAS
V
IH
V
IL
CAS
V
IH
V
IL
V
IH
V
IL
Address
V
OH
V
OL
DQ
“H” or “L”
Note: WE, OE = “H” or “L”
Row
Open
t
CEZ
t
RPC
t
RP
t
RC
t
RAS
t
CHR
t
RP
t
CSR
t
CP
t
RPC
RAS
V
IH
V
IL
CAS
V
IH
V
IL
V
OH
V
OL
DQ
Open
Note: WE, OE, Address = “H ” or “L ”
1R1
47247
x Hidden Refresh Read Cycle
x Hidden Refresh Write Cycle
t
DH
t
DS
t
WCH
t
WCS
t
RWL
t
RAL
t
RAD
t
CAH
t
RAH
t
ASR
t
ASC
t
RCD
t
CRP
t
RSH
t
RP
t
CHR
t
RP
t
RAS
t
RC
t
RC
t
RAS
t
WP
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
IH
V
IL
Row Column
Valid Data-in
“H” or “L”
t
RAC
t
CLZ
t
OEZ
t
ROH
t
OEA
t
CAC
t
RRH
t
AA
t
RAL
t
RCS
t
CAH
t
RAH
t
ASR
t
ASC
t
RAD
t
RP
t
RAS
t
RC
t
RP
t
CHR
t
RAS
t
RSH
t
RCD
t
CRP
t
RC
t
WRH
t
WRP
Column
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
OH
V
OL
Open
Row
Valid Data-out
“H” or “L”
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit and assembly designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
OKI assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to:traffic control, automotive, safety, aerospace,
nuclear power control, and medical, including lift support and maintenance.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 1997 OKI ELECTRIC INDUSTRY CO.,LTD.
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