OKI MR27T1602F Technical data

OKI Semiconductor

A

FEDR27T1602F-02-02

Issue Date: Mar. 12, 2002

MR27T1602F

1M–Word × 16–Bit or 2M–Word × 8–Bit P2ROM

FEATURES

· 1,048,576-word × 16-bit/2,097,152-word × 8-bit electrically switchable configuration

· 2.7 V to 3.6 V power supply

· Access time 90 ns MAX

· Operating current 30 mA MAX

· Standby current 10 µA MAX

· Input/Output TTL compatible

· Three-state output

PACKAGES

· MR27T1602F-xxxMA 44-pin plastic SOP (SOP44-P-600-1.27-K)

· MR27T1602F-xxxTP 44-pin plastic TSOP (TSOP(2)44-P-400-0.80-K)

· MR27T1602F-xxxTN 48-pin plastic TSOP (TSOP(1)48-P-1220-0.50-K)

P2ROM ADVANCED TECHNOLOGY

P2ROM stands for Production Programmed ROM. This exclusive Oki technology utilizes factory test equipment for programming the customers c ode into the P2 ROM prior to fi nal production testing. Advancements in this technology allows production costs to be eq uivalent to M ASKROM and has many advantages and added benefits over the other non-volatile technologies, which include the following;

· Short lead time, since the P2ROM is programmed at the

final stage of the production process, a large P2ROM inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive lead-time and minimizes liability as a custom product.

· No mask charge, since P2ROMs do not utilize a custom

mask for storing customer code, no mask charges apply.

· No additional programming charge, unlike Flash and

OTP that require additional programming and handling costs, the P2ROM already has the code loaded at the factory with minimal effect on the production throughput. The cost is included in the unit price.

· Custom Marking is available at no additional charge.

· Pin Compatible with Mask ROM and some FLASH

products.

PIN CONFIGURATION (TOP VIEW)

1

NC

2

A18

3

A17

4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

CE#

13

V

SS

14

OE#

15

D0

16

D8

17

D1

18

D9

19

D2

20

D10

21

D3

22

D11

44SOP,

44TSOP(Type-II)

1

A15

2

A14

3

A13

4

A12

5

A11

6

A10

7

A9

8

A8

9

A19

10

NC

11

NC

12

NC

13

NC

14

NC

15

NC

16

A18

17

A17

18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

48TSOP(Type-I)

44

NC

43

19

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

BYTE#

32

VSS

31

D15/A–1

30

D7

29

D14

28

D6

27

D13

26

D5

25

D12

24

D4

23

VCC

16

48

BYTE#

47

VSS

46

D15/A–1

45

D7

44

D14

43

D6

42

D13

41

D5

40

D12

39

D4

38

VCC

37

D11

36

D3

35

D10

34

D2

33

D9

32

D1

31

D8

30

D0

29

OE#

28

VSS

27

CE#

26

0

25

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OKI Semiconductor

BLOCK DIAGRAM

A0 A1 A2 A3 A4 A5 A6 A7 A8

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

PIN DESCRIPTIONS

Pin name Functions D15 / A–1 Data output / Address input A0 to A19 Address inputs D0 to D14 Data outputs

CE# Chip enable input OE# Output enable input

BYTE# Word / Byte select input

VCC Power supply voltage VSS Ground

NC No connect

A–1

CE# BYTE# OE#

CE OE

Row Decoder

Address Buffer

Column Decoder

FEDR27T1602F-02-02

MR27T1602F/P2ROM

× 8/× 16 Switch

Memory Cell Matrix

1M × 16-Bit or 2M × 8-Bit

Multiplexer

Output Buffer

D0 D2 D4 D6 D8 D10 D12 D14

D1 D3 D5 D7 D9 D11 D13 D15

In 8-bit output mode, these pins are placed in a high-Z state and pin D15 functions as the A-1 address pin.

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FEDR27T1602F-02-02

OKI Semiconductor

MR27T1602F/P2ROM

FUNCTION TABLE

Mode CE# OE# BYTE# VCC D0 to D7 D8 to D14 D15/A–1 Read (16-Bit) L L H D Read (8-Bit) L L L D

Output disable L H

Standby H ∗

H

L

H

L

3.0 V

Hi–Z L/H

OUT

Hi–Z

∗

∗: Don’t Care (H or L)

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Value Unit Operating temperature under bias Ta 0 to 70 °C Storage temperature Tstg Input voltage VI –0.5 to VCC+0.5 V Output voltage VO –0.5 to VCC+0.5 V Power supply voltage VCC Power dissipation per package PD — 1.0 W

—

relative to V

SS

–55 to 125 °C

–0.5 to 5 V

RECOMMENDED OPERATING CONDITIONS

(Ta = 0 to 70°C)

Parameter Symbol Condition Min. Typ. Max. Unit

VCC power supply voltage VCC 2.7 — 3.6 V

= 2.7 to 3.6 V

Input “H” level VIH 2.2 — VCC+0.5∗ V Input “L” level VIL

V

CC

–0.5∗∗ — 0.6 V

Voltage is relative to V

SS

.

∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns. ∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.

PIN CAPACITANCE

(VCC = 3.0 V, Ta = 25°C, f = 1 MHz)

Parameter Symbol Condition Min. Typ. Max. Unit

Input C

BYTE# C

Output C

— — 8

IN1 IN2

V

OUT

= 0 V

V

I

= 0 V — — 10

O

— — 120

pF

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