OKI ML60852 Datasheet

PEDL60852-01

Semiconductor

ML60852

USB Device Controller

Preliminary

This version: Jan. 2000

GENERAL DESCRIPTION

The ML60852 is a general purpose Universal Serial Bus (USB) device controller. The ML60852 provde a USB serial interface engine, USB transceiver, FIFOs, control/status registers, application interface circuit, and oscillation circuit thereby easily realizing a USB system. The ML60852 supports four types of data transfer such as control transfer, bulk transfer, interrupt transfer and isochronous transfer, and also supports five or six endpoints.

FEATURES

•

USB1.1 compliant

•

Supports full-speed (12 Mbps).

•

Supports four types of transfer; control transfer, bulk transfer, interrupt transfer, and isochronous transfer.

•

Endpoints: 5 to 6 endpoints Control EP 1 Bulk/interrupt EP 3 Isochronous/bulk/interrupt EP 1 or 2

•

Built-in FIFO for data storage

•

A two-layer configuration of FIFO for each of EP1, EP2, EP4, and EP5

•

DMA transfer is possible (EP1, EP2, EP4, and EP5).

•

Supports bus-powered device. The suspend condition is automatically detected and the low-power mode is activated. Normal operation is automatically restarted when the resume condition is detected.

•

Built-in USB transceiver circuit

•

=3.0 to 3.6 V

•

Interface with 5 V circuit is possible. (Input: 5 V tolerant, output: TTL)

•

Built-in 12 MHz oscillation circuit

•

Package options: 44-pin plastic QFP or TQFP 56-pin plastic LGA

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ML60852

Endpoints and FIFOs

In the ML60852, it is possible to select by making appropriate register setting either the 5EP mode in which there are five end points or the 6EP mode in which there are six end points. Although the transfer mode that can be used by EP0 is fixed, it is possible to select either the bulk transfer mode or the interrupt transfer mode for the end points EP1, EP2, and EP3, and one of the modes of isochronous, bulk, or interrupt transfer can be selected for EP4 and EP5. In addition, it is possible to selectively set the direction of data transfer for EP1 to EP5.

5EP Mode 6EP ModeEnd

point

EP0 Reception 32

EP1 64x2 Bulk/interrupt transfer

EP2 64x2 Bulk/interrupt transfer

EP3 32

EP4 512x2

EP5 — — 256x2 (64x2) Isochronous/bulk/

FIFO

Capacity

Transmission 32

(64x2)

Transfer

mode

Control transfer Reception 32

(IN/OUT)

Bulk/interrupt transfer

(IN/OUT)

Isochronous/bulk/

interrupt transfer

(IN/OUT)

Remarks FIFO

Capacity

Transmission 32

DMA

Possible

DMA

Possible

DMA

Possible

64x2 Bulk/interrupt transfer

256x2 (64x2) Isochronous/bulk/

Transfer

mode

Control transfer

(IN/OUT)

Bulk/interrupt transfer

(IN/OUT)

interrupt transfer

(IN/OUT)

interrupt transfer

(IN/OUT)

Remarks

DMA

Possible

DMA

Possible

DMA

Possible

DMA

Possible

FIFO Capacity: The unit is bytes.

Note 1: The selection between the 5EP mode and the 6EP mode is made by bit D2 of the register

SYSCON. Note 2: EP3 permits rate feedback data sequence toggling. Note 3: EP1, EP2, and EP3 are all mutually independent, and can be assigned for bulk transfer or

interrupt transfer individually. It is possible to set the maximum packet size up to 64 bytes (32

bytes for EP3) during both bulk transfer and interrupt transfer. Note 4: It is possible to set EP4 and EP5 to one of the modes of isochronous transfer, bulk transfer, and

interrupt transfer. The maximum packet size can be up to 64 bytes when these end points are set

to bulk transfer. Note 5: When using EP4 and EP5 in the isochronous transfer mode:

In the 5EP mode, the maximum packet size of EP4 is 512 bytes. EP5 cannot be used.

In the 6EP mode, the maximum packet size of both EP4 and EP5 is 256 bytes.

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PIN CONFIGURATION (TOP VIEW)

44-pin QFP/TQFP (Top View)

PEDL60852-01

ML60852

YL YB

DREQ0

AD7

AD6

AD5

AD4

GND

AD3

AD2

AD1

AD0

12345

DACK0

3332313029282726252423

1234567891011

D-

D+

XIN

GND

TEST1

REQ1

DSEL

LE/PUCTL

XOUT

RESE

D10

D11

DACK1

TEST2

D12

D13

D14

D15

INTR

Package dimensions (unit: mm)

44QFP 44TQFP

XB 10.5 ±0.1 10.0 ±0.1 XL 14.5 ±0.2 12.0 ±0.2 YB 9.5 ±0.1 10.0 ±0.1 YL 13.5 ±0.2 12.0 ±0.2

Height 2.25MAX 1.2MAX

Lead pitch 0.8 0.8

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56-pin LGA (Top View)

PEDL60852-01

ML60852

NC D8 D9 D11 TEST2 D12 D14

ALE/

PUCTL

A7 ADSEL

A5 A6 XOUT

A4 NC NC XIN

A2 A3 TEST1 GND

A0 A1

DACK0 NC AD7 AD5 NC V

NC D10 DACK1 NC D13 D15 NC

Pin No.1 Marking

→

AD2 NC D+

INTR

RD WR

D- V

RESET

DREQ0

AD6 AD4 GND AD3 AD1 AD0 NC

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PIN DESCRIPTION

Pin name Pin count I/O Description

D+, D- 2 I/O USB data

XIN, XOUT 2 — Pins for external crystal

AD7:AD0 8 I/O Data bus (LSB)/address inputs

A6:A0 7 I Address inputs

D15:D8 8 I/O Data bus (MSB)

CS RD WR

INTR DREQ0 DREQ1

DACK0 1 I DMA0 reception signal input pin

DACK1 1 I DMA1 reception signal input pin

ALE/PUCTL 1 I,O Address latch enable signal input pin/pull-up control pin

ADSEL 1 I Address input format select input pin

RESET

TEST1, TEST2 2 I Test pin. (Normally at “L”)

GND 2 GND

1 I Chip select signal input pin. Active “L”

1 I Read signal input pin. Active “L”

1 I Write signal input pin. Active “L”

1 O Interrupt request signal output pin

1 O DMA0 request output pin

1 O DMA1 request output pin

1 I Reset signal input pin

2 3.3 V power supply pin

PEDL60852-01

ML60852

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BLOCK DIAGRAM

A6:A0

Local

MCU

AD8:AD0

D15:D8

Application

Interface

PEDL60852-01

ML60852

INTR

RESET

DREQ0,1

DACK0,1

ML60852

Set

XIN

6/12MHz

8-byte

6/12MHz

Oscillator

Setup

EP0

Receive

FIF0

EP4

EP5

EP3

Ω

1.5 k

Ω

D+

FIF0

USB

Transceiver

Ω

EP1

FIF0

EP0

Transmit

FIF0

Circuit

Multiplication

XOUT

Consult with

a crystal maker

Engine

Protocol

for crystal

peripheral parts

EP2

ALE/PUCTL

FIF0

D-

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ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit

Power Supply V

Input Voltage (Tolerant) V

Input Voltage (Normal) V

Storage Temperature T

STG

TJ = 25°C

VSS = 0 V

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Range Unit

Power Supply V

Operating Temperature V

Oscillation Frequency F

OSC

PEDL60852-01

ML60852

–0.3 to + 4.6 V

–0.3 to + 6.0 V

–0.3 to + V

— –65 to + 150 °C

— 3.0 to 3.6 V

— 0 to 70 °C

—12MHz

+ 0.3 V

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ELECTRICAL CHARACTERISTICS

DC Characteristics (1)

= 3.0 to 3.6 V, Ta = 0 to +70 °C)

Parameter Symbol Condition Min. Typ. Max. Unit Applicable pin

High-level Input

Voltage

Low-level Input

Voltage

High-level Input

Voltage

Low-level Input

Voltage

Schmitt Trigger

Input Voltage

High-level

Output Voltage

Low-level

Output Voltage

High-level Input

Current

Low-level Input

Current

3-state Output

Leakage Current

Power Supply

Current (Operating)

Power Supply

Current (Standby)

∆V

OZH

OZL

CCS

— 2.0 — 5.5 V

— –0.3 — –0.8 V

—V

× 0.8 — VCC + 0.3 V

— –0.3 — VCC × 0.2 V

——1.52.0V

—0.71.0—V

(Vt+) – (Vt-)0.4 0.5 — V

IOH = –100 µA VCC – 0.2 — — V

IOH = –4 mA 2.4 — — V

IOL = 100 µA — — 0.2 V

IOL = 4 mA — — 0.4 V

VIH = V

—0.110µA

VIL = 0V –10 –0.1 — µA

VOH = V

VOL = 0V –10 –0.1 — µA

—0.110µA

AD7:AD0

———50µAV

Note 4 — — 100 µA V

ML60852

Note 1

XIN

RESET

Note 2

Note 3

D15:D8

Notes: 1. Applied to D15: D8, AD7: AD0, A6: A0, CS, RD, WR, DACK0, DACK1, ALE, and ADSEL.

2. Applied to D15: D8, AD7: AD0, A6: A0,

INTR, DREQ

0, and

DREQ

3. Applied to XIN, AD7: AD0, CS, RD, WR, DACK, ALE, and ADSEL.

4. The XIN pin is fixed at a high level or a low level in the suspend state. All the output pins are open.

The test specification of ON resistance for ALE/PUCTL is not defined.

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DC Characteristics (2) USB Port

(VCC = 3.0 to 3.6 V, Ta = 0 to +70 °C)

Parameter Symbol Condition Min. Typ. Max. Unit Applicable pin

Differential Input

Sensitivity

Differential Common

Mode Range

Single Ended

Receiver Threshold

High-level Output

Voltage

Low-level Output

Voltage

Output Leakage

Current

(D+) – (D –) 0.2 — — V

Includes VDI range 0.8 — 2.5 V

— 0.8 — 2.0 V

RL of 15 kΩ to GND 2.8 — 3.6 V

RL of 1.5 kΩ to 3.6 V v — 0.3 V

0 V <VIN <3.3 V –10 — +10 µA

ML60852

D+, D-

AC Characteristics USB Port

(VCC = 3.0 to 3.6 V, Ta = 0 to +70 °C)

Parameter Symbol Condition Min. Typ. Max. Unit Applicable pin

Rise Time t

Fall Time t

Rise/Fall Time

Matching

Output Signal

Crossover Voltage

Driver Output

Resistance

Data Rate T

RFM

CRS

DRV

DRATE

CL = 50 pF 4 — 20 ns

(tR/ tF) 90 — 111.11 %

—1.3—2V

Steady State Driver 28 — 44 Ω

Ave. Bit Rate

(12 Mbps ±0.25%)

11.97 — 12.03

Mbp

Notes: 1. 1.5 kΩ pull-up to 3.3 V on the D + data line.

and

are measured from 10% to 90% of the data signal.

D+, D-

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SIGNAL DESCRIPTIONS

USB Interface

Signal Type Assertion Description

USB data (Plus). This signal and the D- signal are the transmitted or received data from/to USB Bus. The table below shows values and results for these signals.

D+ D- Result

D+ I/O —

D- I/O —

USB Data (Minus). This signal and the D+ signal are the transmitted or received data from/to USB Bus. The table above shows values and results for these signals.

0 0 Single end 0

0 1 Differential "0"

1 0 Differential "1"

1 1 Undefined

PEDL60852-01

ML60852

Crystal Oscillator Interface

Signal Type Assertion Description

XIN I —

XOUT O —

For internal oscillation, connect a crystal to XIN and XOUT.

For external oscillation, supply an external 12 MHz clock signal to XIN.

Set XOUT to be open.

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Application Interface

Signal Type Assertion Description

D15: D8 I/O — Upper byte (MSB) of data bus.

AD7: AD0 I/O —

A6: A0 I — Address when ADSEL is LOW.

INTR

DREQ0 DREQ1

DACK0 I (Note 2)

DACK1 I (Note 2)

ALE/PUCTL I or O HIGH

ADSEL I —

RESET

ILOW

O (Note 1)

O (Note 1) DMA Request. This signal requests the DMA0 to make a DMA transfer.

O (Note 1) DMA Request. This signal requests the DMA1 to make a DMA transfer.

ILOW

Lower byte (LSB) of data bus when ADSEL is LOW.

Address and lower byte of data bus are multiplexed when ADSEL is HIGH.

Chip Select. When this signal is asserted LOW, the ML60852 is selected and ready to read or write data. This signal is invalid in single address mode during DMA transfer.

Read Strobe. When this signal is asserted LOW, the Read instruction is executed.

Write Strobe. When this signal is asserted LOW, the Write instruction is executed.

Interrupt Request. When this signal is asserted, the ML60852 makes an interrupt request to the application.

DMA Acknowledge Signal for accessing FIFOs, without address bus setting.

DMA Acknowledge Signal for accessing FIFO, without address bus setting.

When ADSEL is HIGH, the address and CS on AD7: AD0 are latched at the trailing edge of this signal. D+ pull-up resistor connection output when ADSEL is LOW.

potential when bit D3 of SYSCON register is “1”, and high-impedance

when it is “0”.

When ADSEL is LOW, the address is input on A6: A0 and data is input on AD7: AD0. When ADSEL is HIGH, address and data are multiplexed on AD7: AD0.

System Reset. When this signal is asserted LOW, the ML60852 is reset. When the ML60852 is powered on, this signal must be asserted for 1 µs or

more.

DREQ0

DREQ1

PEDL60852-01

ML60852

. This signal, when asserted, enables

Notes: 1. The assertion can be set by using the assertion select register.

The default is LOW.

2. The assertion can be set by using the assertion select register. The default is HIGH.

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FUNCTIONAL DESCRIPTIONS

(1) USB Interface

The ML60852 is a USB device controller. The ML60852 provides the following functions which are bases for a USB protocol. Therefore, the application can process a lot of its own functions.

•

Bit synchronization

•

Encoding and decoding NRZI signals.

•

Generating and detecting Sync bytes.

•

Bit stuffing

•

Generating and checking CRCs (CRC5, CRC16).

•

Encoding and decoding PID (packet identifier).

1. Decoding token.

2. Encoding and decoding handshake.

•

Generating and detecting SOP.

•

Enpacket (packing) and depacket (unpacking)

•

Comparing device addresses.

•

Storing 8-byte setup data from a host into the setup register.

•

Transmitting data in transmit FIFO.

•

Storing receive data into receive FIFO of the corresponding endpoint.

(2) USB Transfer Modes

The ML60852 supports four kinds of transfer modes such as control transfer mode , interrupt transfer mode, bulk transfer mode, and isochronous transfer mode, which are specified by USB Standards. (a) The control transfer mode is used to receive and respond to configurations and commands from a host, and to

exchange status information between the host and peripherals.

(b) The bulk transfer mode is used to transfer a lot of data in the limited service period when the band width of

USB bus becomes sufficient. (c) The interrupt transfer mode is used to transfer a small amount of data unfreguently in the limited service period. (d) The isochronous transfer mode is used to continuously transfer audio data, moving pictures data and other data.

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(3) Endpoints and FIFOs

In the ML60852, it is possible to select, by making appropriate setting in the SYSCON register, the 5EP mode in which there are five end points or the 6EP mode in which there are six end points. Although the transfer mode that can be used by EP0 is fixed, it is possible to select either the bulk transfer mode or the interrupt transfer mode for the end points EP1, EP2, and EP3, and one of the modes of isochronous, bulk, or interrupt transfer can be selected for EP4 and EP5. In addition, it is possible to selectively set the direction of data transfer for EP1 to EP5.

5EP Mode 6EP ModeEnd

point

EP0 Reception 32

EP1 64x2 B/Int

EP2 64x2 B/Int

EP3 32 B/Int

EP4 512x2

EP5 — — 256x2 (64x2) Iso/B/Int

FIFO

Capacity

Transmission 32

(64x2)

Transfer

mode

C Reception 32

(IN/OUT)

Iso/B/Int

(IN/OUT)

Remarks FIFO

Capacity

Transmission 32

DMA

Possible

DMA

Possible

Rate 32 B/Int

DMA

Possible

256x2 (64x2) Iso/B/Int

Transfer

mode

Control transfer

64x2 B/Int

(IN/OUT)

64x2 B/Int

(IN/OUT)

Remarks

DMA

Possible

DMA

Possible

Rate

DMA

Possible

DMA

Possible

FIFO Capacity: The unit is bytes.

Note: Transfer modes:

C = Control transfer B = Bulk transfer Int = Interrupt transfer Iso = Isochronous transfer Rate = Compatible with data sequence toggling of rate feedback.

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ML60852

(4) Operation of control transfer

(a) Setup stage

The setup token and 8 bytes of setup data are transmitted from the host. The ML60852 decodes the setup token,

and automatically stores the 8 bytes of setup data in the setup register. When this is completed normally, the

ML60852 returns ACK to the host.

The 8-byte setup data is the standard request code defined in Section 9.3 of the USB Standards, or a code of the

requests unique to each device class, etc. The request is decoded on the local MCU side. (b) Data stage

If the request specified by the 8-byte setup data is also accompanied by transfer of parameter data from the host

to the device, the transfer is a control write transfer, and the OUT token and the data packet are transmitted

from the host. When these are received normally, the ML60852 stores the parameter data in the EP0 receive

FIFO and returns ACK to the host.

If the request is accompanied by transfer of parameter data from the device to the host, the transfer is a control

read transfer, and when the host sends the IN token, the ML60852 sends the parameter data that was already

stored beforehand in the EP0 transmit FIFO by the local MCU. When the host receives this normally, it returns

an ACK to the ML60852.

On the other hand, in the case of requests that do not contain any parameter data that need to be transmitted or

received, this data stage will not be present and the processing proceeds directly to the status stage from the

setup stage. (c) Status stage

The status stage is a stage intended for reporting the status of the result of executing a request from the device

to the host. During a control write transfer or a control transfer without data, the IN token is sent by the host,

and the ML60852 returns a response to it. During a control read transfer, the OUT token and data of zero

length are sent by the host, and the ML60852 returns a response to it.

During the above control transfers, the local MCU need only read from or write to the 8-byte setup registers

mapped at 00h to 07h, the EP0 transmit FIFO mapped at 70h, and the EP0 receive FIFO mapped at 78h

according to the interrupt cause, and all other operations will be carried out automatically by the ML60852.

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ML60852

(5) Data packet transmission and reception procedure during bulk transfer and interrupt transfer modes

The ML60852 is normally used on the peripheral device side. In this method of use, the ML60852 is connected on one side to the host via the USB bus and is connected on the other side via a parallel interface to the local microcontroller (local MCU) inside the peripheral device. The transfer of data is the major function in all types of transfer modes other than the control transfer mode. When carrying out transfer of data packets between the ML60852 and the host, the following packet communication is carried out via the USB bus for the data transfer of each packet.

(a) Token packet transfer (IN token or OUT token) from the host to the ML60852. (b) Data packet transfer in the desired direction (from the host to the device or from the device to the host). (c) Transfer of handshake packet in a direction opposite to that of the data packet.

When packet transfer is completed normally, an ACK packet is returned in step (c) and the operation proceeds

to the next packet transfer.

The ML60852 requests the local MCU to transmit or receive a packet of data by asserting the

INTR

pin. The interrupt cause will be “packet ready”. The transmit packet ready interrupt is one that requests that the packet of data to be transmitted be written in the transmit FIFO, and the receive packet ready interrupt is one that requests the local MCU to read out the data that has been received and stored in the receive FIFO. The above procedures of transferring one packet of data are explained below for transmission and reception separately.

1) During transmission The local MCU writes one packet of data that has to be transmitted in the transmit FIFO of the corresponding EP in the ML60852, and sets the transmit packet ready bit of the corresponding EP status register of the ML60852. When the host transmits the IN token packet to the ML60852 specifying the communication method, etc., the ML60852 transmits to the host the data packet stored in the above transmit FIFO. When the host receives one data packet normally, it returns the ACK packet to the ML60852. Consequently, the ML60852 resets the transmit packet ready status, thereby completing the transfer of one data packet over the USB bus. When the transmit packet ready status is reset, the ML60852 gives a request to the local MCU in terms of a transmit packet ready interrupt thereby prompting the local MCU to write the next packet of data to be transmitted.

2) During reception The host sends to the ML60852 an OUT token followed by a data packet. The ML60852 stores the received data packet in the receive FIFO of the corresponding EP. When it is confirmed that all the data packets have been accumulated and that there is no error, the ML60852 returns an ACK packet to the host. At the same time, the receive packet ready bit of the corresponding EP status register will also be set and a request is sent to the local MCU in terms of an interrupt. Upon receiving this interrupt, the local MCU reads out the received data from the ML60852 and resets the receive packet ready bit.

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ML60852

(6) Data packet transmission and reception procedure during isochronous transfer mode

Transfer of data is the major function in the isochronous transfermode. When carrying out isochronous transfer between the ML60852 and the host, the following packet communications are carried out via the USB bus for the data transfer of each packet.

(a) Token packet transfer (IN token or OUT token) from the host to the ML60852. (b) Data packet transfer in the desired direction (from the host to the device or from the device to the host).

In the isochronous transfer mode, there is no handshaking that reports whether or not the packet transfer was done normally.

The ML60852 requests the local MCU to send or receive packet data by asserting the

INTR

pin. The interrupt cause is SOF. Upon receiving this interrupt, the local MCU writes the packet data into the transmit FIFO of the EP set for transmission (ISO IN) in the isochronous transfer mode, or reads out data from the receive FIFO of the EP set for reception (ISO OUT) in the isochronous transfer mode. The above procedures of transferring one packet of data are explained below for transmission and reception separately.

1) During transmission The EP for ISO IN has a two-layer FIFO configuration. One FIFO is used for storing the packet data that is written in by the MCU via the local bus. The other FIFO is used for transmitting the stored data to the USB bus when an IN token is received. The roles of the two FIFOs are interchanged when an SOF packet is received. Upon receiving an SOF interrupt, the local MCU writes the data to be transmitted during the next frame into the corresponding transmit FIFO of the EP of the ML60852. When the host transmits an IN token packet, the ML60852 transmits to the host the packet data written in the transmit FIFO during one frame before the current frame.

2) During reception The EP for ISO OUT has a two-layer FIFO configuration. One FIFO is used for storing the packet data that is output to the local bus when the MCU reads the received packet data. The other FIFO is used for storing the packet data received from the USB bus. The roles of the two FIFOs are interchanged when an SOF packet is received. Upon receiving an SOF interrupt, the local MCU reads out the data that has been received during the previous frame from the corresponding receive FIFO of the EP of the ML60852. When the host transmits an OUT token and a data packet to the ML60852, the ML60852 stores that received data packet in the receive FIFO, and that data packet is read out by the local MCU during the next frame.

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ML60852

(7) Packets and packet sizes

The ML60852 packs the transmit data into packets and unpacks (restores to the original form) the received data. The packed data that is recognized by the software client is a set of data consisting of one or more packets, and this is called an I/O request (IRP). Among the several packets in an IRP, all the packets other than the last packet are transferred with the maximum packet size. Only the last packet can be transferred as a "short packet", that is, a packet whose size is less than the maximum packet size.

I/O Request Packet (IRP

Packet

n-1

Packet

1 Packet

M Bytes

Maximum packet size

The ML60852 has payload registers corresponding to each end point, and it is possible to set the maximum packet size for each end point in these registers. The maximum packet size should be within the capacity of the corresponding FIFO, and can be set as follows:

(1) EP0 Receive packet size can be 32 bytes or less; (2) EP0 Transmit packet size can be 32 bytes or less; (3) EP1 Transmit/receive packet size can be 64 bytes or less; (4) EP2 Transmit/receive packet size can be 64 bytes or less; (5) EP3 Transmit/receive packet size can be 32 bytes or less; (6) EP4 Bulk/interrupt transmit/receive packet size can be 64 bytes;

In the 5EP mode, the EP4 isochronous packet size can be 512 bytes or less; In the 6EP mode, the EP4 isochronous packet size can be 256 bytes or less;

(7) In the 6EP mode, the EP5 bulk/interrupt packet size can be 64 bytes or less;

In the 6EP mode, the EP5 isochronous packet size can be 256 bytes or less.

On the USB bus, the separation between successive packets is distinguished by appending a special signal condition called EOP (End of Packet) at the end of each packet. The appending of EOP during transmission and the detection and removal of EOP during reception are carried out by the ML60852 automatically.

(1) At the time of transmission, the packet is deemed to have ended when the local MCU has completed writing the

required number of bytes of data in the transmit FIFO and has then asserted the transmit ready status bit. (The actual addition of EOP is executed at the time of transmitting the data over the USB bus after waiting for the IN token from the host.) The packet will be a short packet if the transmit packet ready status bit is asserted after writing data with less number of bytes than the maximum packet size. In particular, by asserting the transmit packet ready status bit without writing any data, it is possible to form a null packet whose data length is zero.

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(2) At the time of reception, when an EOP is detected in the received data string, the ML608522 recognizes it as

the end of the received packet and asserts the receive packet ready status bit. The number of bytes in the received packet is counted automatically by the receive byte count register (Note 1) corresponding to that end point. Note 1: Receive byte count register address: 58h to 5Dh and 74h to 75h.

(8) Interrupts

The ML60852 requests interrupts to the local MCU, etc., by asserting the -INTR pin. The interrupt causes are the following:

(a) Setup ready for the 8-byte setup data (b) EP0 receive packet ready (c) EP0 transmit packet ready (d) EP1 transmit/receive packet ready (e) EP2 transmit/receive packet ready (f) EP3 transmit/receive packet ready (g) EP4 transmit/receive packet ready (h) EP5 transmit/receive packet ready (i) SOF (j) USB Bus reset assert (k) USB Bus reset de-assert (l) Suspend (m) Awake

Although there is only one

INTR

pin, the local MCU can identify the contents of the interrupt by reading out the interrupt status register 1 (INTSTAT1) and the interrupt status register 2 (INTSTAT2). These interrupts can also be masked dynamically by making individual settings in the interrupt enable register 1 (INTENBL1) and the interrupt enable register 2 (INTENBL2). The causes of the interrupts, their setting and resetting conditions, and the responses to them are described below. The functions of the setup ready bit and the packet ready bit can, in some situations, be different from those described here because of some special automatic operations done by the ML60852. Please see the descriptions of the registers EP0STAT to EP5STAT for more details of such functions.

(1) Setup ready interrupt

Operation Source of operation Description (conditions, responses, etc.)

Setup ready

interrupt generation

End of setup ready interrupt Local MCU (firmware)

ML60852

The setup ready bit (D2 of EP0STAT) is asserted when the 8-byte setup control data is received normally and has been stored in the set of setup registers.

An interrupt is generated at this time if D1 of INTENBL1 has been asserted.

→ The firmware can now read the set of setup registers.

After making the firmware read the 8-byte setup data, write a “1” in bit D2 of EP0 status register (EP0STAT). This causes the interrupt to be de-asserted.

The interrupt will not be de-asserted If a new 8-byte setup data is received during this period. In this case, discard the setup data that was being read at that time and read the new 8-byte setup data.

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(2) EP0 Receive packet ready interrupt

This is used mainly during the reception of a data packet in a control write transfer.

Operation Source of operation Description (conditions, responses, etc.)

EP0 Receive packet ready

interrupt generation

End of EP0 receive

packet ready interrupt

ML60852 The EP0 receive packet ready bit (D0 of EP0STAT) is

asserted during a control write transfer when the processing has changed from the setup stage to the data stage, and the ML60852 has detected EOP of the data packet and has stored the data without error in the EP0 receive FIFO. The end of a packet is recognized when an EOP has arrived in the cases of both full packets and short packets.

An interrupt is generated at this time, if the EP0 receive packet ready interrupt enable bit (D6 of INTENBL1) has been asserted.

(EOP: End of packet)

Local MCU (firmware) In the case of EP0 reception, after the number of bytes of

the EP0 receive FIFO data indicated by the EP0 receive byte count register (EP0RXCNT) has been read, write a “1” to the EP0 receive packet ready bit (bit D0 of EP0STAT). (This status is reset when a “1” is written in this bit.)

PEDL60852-01

ML60852

Note: A short packet is a packet with a number of bytes less than the maximum packet size.

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(3) EP0 Transmit packet ready interrupt

This is used mainly during the transmission of a data packet in a control read transfer.

Operation Source of operation Description (conditions, responses, etc.)

EP0 Transmit packet ready

interrupt generation

End of EP0 transmit

packet ready interrupt

ML60852 The EP0 transmit packet ready bit (D1 of EP0STAT) is de-

asserted during a control read transfer when the processing has changed from the setup stage to the data stage, and it is possible to write the transmit data to the FIFO.

At this time, an interrupt is generated if the EP0 transmit packet ready interrupt enable bit (bit D7 of INTENBL1) has been asserted.

For the second and subsequent packets, in addition to this condition, before the interrupt is generated, it is necessary for an ACK response to come from the host for the packet that has just been sent.

Local MCU (firmware) In the case of EP0 transmission, after the one packet of the

EP0 transmit data has been written in EP0TXFIFO, write a “1” into the EP0 transmit packet ready bit (bit D1 of EP0STAT). This puts the ML60852 in a state in which it can transmit the data (that is, it can transmit the data packet when an IN token arrives), and the at the same time.

Even when the number of bytes in the write data is less than the maximum packet size, it is possible to transmit the data by writing a “1” into the transmit packet ready status bit. This makes it possible to transmit a short packet.

PEDL60852-01

INTR

pin is de-asserted

ML60852

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(4) Receive packet ready interrupts (EP1, EP2, EP3, EP4 bulk, EP5 bulk)

These interrupts are generated when the respective EP has received an appropriate data packet from the USB bus and the local MCU can read that data.

Operation Source of operation Description (conditions, responses, etc.)

Receive packet ready

interrupt generation

End of receive packet ready interrupt

ML60852 The receive packet ready bit (D0) of the corresponding EP

status register (EPnSTAT) is asserted during data reception when the EOP of the data packet has been received and the data has been stored without error in the corresponding FIFO. The end of a packet is recognized when an EOP has arrived in the cases of both full packets and short packets.

An interrupt is generated at this time, if the corresponding receive packet ready interrupt enable bit has been asserted.

(EOP: End of packet)

Local MCU (firmware) After the number of bytes in the receive FIFO data

(EPnFIFO) indicated by the corresponding receive byte count register (EPnRXCNT) has been read, write a “1” into the receive packet ready bit D0 of the corresponding EP status register (EPnSTAT). (This status is reset when a “1” is written in this bit.)

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(5) Transmit packet ready interrupts (EP1, EP2, EP3, EP4 bulk, EP5 bulk)

These interrupts are generated when it is possible for the local MCU to write the data packet to be sent to the USB bus from the corresponding EP.

Operation Source of operation Description (conditions, responses, etc.)

Transmit packet ready

interrupt generation

End of transmit packet ready interrupt

ML60852 (1) In the case of bulk transfer and interrupt transfer

When the respective EP has been set for transmission, the transmit packet ready bit of the corresponding EP (bit D1 of EPnSTAT) is de-asserted when it is possible to write the transmit data into the FIFO.

At this time, an interrupt is generated if the corresponding EP transmit packet ready interrupt enable bit (INTENBL1) has been asserted.

Local MCU (firmware) (1) In the case of bulk transfer and interrupt transfer

After the one packet of the corresponding EP transmit data has been written in EPnTXFIFO, write a “1” into the corresponding transmit packet ready bit (bit D1 of EPnSTAT). This puts the ML60852 in a state in which it can transmit the data and the the same time.

Even when the number of bytes in the write data is less than the maximum packet size, it is possible to end the pocket transmission by writing a “1” into the transmit packet ready status bit.

INTR

pin is de-asserted at

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(6) SOF Interrupt

Operation Source of operation Description (conditions, responses, etc.)

SOF Interrupt generation ML60852 When an SOF packet is detected on the USB bus.

End of SOF interrupt Local MCU (firmware) When a “1” is written in the corresponding bit of the

interrupt status register 2 (INTSTAT2).

(7) USB Bus reset assert interrupt

Operation Source of operation Description (conditions, responses, etc.)

USB Bus reset assert

interrupt generation

End of USB bus reset assert interrupt

ML60852 The ML60852 automatically detects the condition when the

SE0 state continues for 2.5µs or longer at the D+ and Dpins.

→ Carry this out by firmware processing for bus reset.

Local MCU (firmware)

When a “1” is written in the corresponding bit of the interrupt status register 2 (INTSTAT2).

(8) USB Bus reset de-assert interrupt

Operation Source of operation Description (conditions, responses, etc.)

USB Bus reset de-assert

interrupt generation

End of USB bus reset

de-assert

ML60852 When there is a recovery to the J state from the SE0 state

of 2.5µs or longer at the D+ and D- pins. → Carry this out by firmware processing for bus reset

release.

Local MCU (firmware) When a “1” is written in the corresponding bit of the

interrupt status register 2 (INTSTAT2).

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(9) Suspend state interrupt

Operation Source of operation Description (conditions, responses, etc.)

Suspend state

interrupt generation

End of suspend state

interrupt

ML60852 When the idle condition persists for 3ms or more at the D+

and D- pins. → The internal oscillations in the ML60852 are stopped

automatically when the idle condition continues for an additional 2ms after this interrupt has been generated. The firmware can take steps to put the device in the power save mode.

Local MCU (firmware) When a “1” is written in the corresponding bit of the

interrupt status register 2 (INTSTAT2).

(10) Awake interrupt

Operation Source of operation Description (conditions, responses, etc.)

Awake interrupt generation ML60852

End of awake interrupt Local MCU (firmware) When a “1” is written in the corresponding bit of the

When the Resume signal (the SE0 state of about 1344ns immediately after the K state) is detected at the D+ and Dpins.

interrupt status register 2 (INTSTAT2).

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(9) DMA (Direct Memory Access)

It is possible to carry out 8-bit wide or 16-bit wide DMA transfer for the bulk transfer of EP1, EP2, EP4, and EP5, and for the isochronous transfer of EP4 and EP5. The data bus used is the following:

During 8-bit transfer: AD7 to AD0

During 16-bit transfer: D15 toD8, AD7 to AD0 It is possible to carry out DMA transfers over two channels, Channel 0 and Channel 1. Both demand transfer and single transfer are supported. The settings of the DMA transfer mode and parameters are done using the DMA control register and the DMA interval register described later in this manual.

In the demand transfer mode, the possible. The

DREQ

pin is de-asserted when the transfer of all the data of the receive packets is completed by the

DREQ

pin is asserted when the reading or writing of a data packet becomes

external DMA controller. Therefore, other devices cannot access the local bus during DMA transfer. On the other hand, in the single transfer mode, the

DREQ

pin is de-asserted at the end of transfer of the number of

bytes (or words) of one transfer, and the other devices can access the local bus during this period.

(10) Power-down

When the ML60852 detects the suspend state on the USB bus, it automatically stops the internal oscillations and enters the power-down state. When the resume signal is detected on the USB bus, the oscillations are restarted automatically and the power-down state is released.

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