OKI ML60851C User Manual

PEDL60851C-02

Semiconductor

ML60851C

USB Device Controller

Preliminary

This version: Dec. 1999

GENERAL DESCRIPTION

The ML60851C is a general purpose Universal Serial Bus (USB) device controller. The ML60851C provides a USB interface, control/status block, application interface, and FIFOs. The FIFO interface and two types of transfer have been optimized for BulkOut devices such as printers and BulkIn devices such as digital still cameras and image scanners. In addition, Mass Storage devices are also applicable to this device.

FEATURES

•

USB 1.0 compliant

•

Built-in USB transceiver circuit

•

Full-speed (12 Mb/sec) support

•

Supports printer device class, image device class, and Mass Storage device class

•

Supports three types of transfer; control transfer, bulk transfer, and interrupt transfer

•

Built-in FIFOs for control transfer

Two 8-byte FIFOs (one for receive FIFO and the other for transmit FIFO)

•

Built-in FIFOs for bulk transfer (available for either receive FIFO or transmit FIFO)

One 64-byte FIFO

Two 64-byte FIFOs

•

Built-in FIFO for interrupt transfer

One 8-byte FIFO

•

Supports one control endpoint, two bulk endpoint addresses, and one interrupt endpoint address

•

Two 64-byte FIFOs enable fast BulkOut transfer and BulkIn transfer

•

Supports 8 bit/16 bit DMA transfer

•

is 3.0 V to 3.6 V

•

Supporting dual power supply enables 5 V application interface

•

Built-in 48 MHz oscillator circuit

•

Package options: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: ML60851CGA) 44-pin plastic TQFP (TQFP44-P-1010-0.80-K) (Product name: ML60851CTB)

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BLOCK DIAGRAM

Application

Module

(Local MCU)

PEDL60851C-02

ML60851C

A7:A0

ML60851C

D15:D0

Application

Status/Control

DPLL

, ,

Interface

Protocol

Engine

DACK

Endpoint FIFO/ 8-byte Setup Register

XIN

Oscillator

XOUT

48 MHz

D+

USB

Transceiver

D-

USB Bus

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PIN CONFIGURATION (TOP VIEW)

PEDL60851C-02

ML60851C

D+ D-

CC3

TEST1 TEST2

XIN

XOUT

RESET

CC5

GND

AD3

AD2

AD1

AD0

4443424140393837363534

1 2 3 4 5 6 7 8

9 10 11

1213141516171819202122

D15

D14

D13

D12

INTR

GND

44-Pin Plastic QFP

AD4

CC5

AD5

D11

AD6

D10

AD7

DREQ

DACK

ADSEL

ALE

D+ D-

CC3

TEST1 TEST2

XIN

XOUT

RESET

CC5

AD3

AD2

AD1

AD0

D15

D14

D13

INTR

D12

AD5

AD4

VSSV

CC5

D11

AD6

D10

AD7

DREQ

DACK

ADSEL

ALE

44-Pin Plastic TQFP

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PIN DESCRIPTION

Pin Symbol Type Description

1,2 D+, D- I/O USB data 6, 7 XIN, XOUT — Pins for external crystal oscillator 4, 5 TEST14, 2 I Test pins (normally “L”)

13 to 16,

19 to 22

35 to 38,

41 to 44 25 to 32 A7 to A0 I Address inputs

9 10 12 34 33 DACK I DMA acknowledge signal input pin

23 ALE I Address latch enable signal input pin 24 ADSEL I Address input mode select input pin. “H”: address/data multiplex 11

D15 to D18 I/O

AD7 to AD0 I/O

CS RD

INTR

DREQ

RESET

O O

I I I

Data bus (MSB)

Data bus (LSB)/address inputs

Chip select signal input pin. LOW active Read signal input pin. LOW active Write signal input pin. LOW active Interrupt request signal output pin DMA request output pin

System reset signal input pin. LOW active.

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INTERNAL REGISTERS

Addresses and Names of Registers

Addresses Register Page

A5:A0

00h 01b — 01h 01b — 02h 01b — EP2RXFIFO Endpoint 2 Receive FIFO Data 03h 01b — Reserved 00h — 11b 01h — 11b 02h — 11b 03h — 11b

Read

A7, A6

Write

A7, A6

Symbol Register name

EP0RXFIFO Endpoint 0 Receive FIFO Data EP1RXFIFO Endpoint 1 Receive FIFO Data

EP0TXFIFO Endpoint 0 Transmit FIFO Data EP1TXFIFO Endpoint 1 Transmit FIFO Data EP2TXFIFO Endpoint 2 Transmit FIFO Data EP3TXFIFO Endpoint 3 Transmit FIFO Data

PEDL60851C-02

ML60851C

7 7 8

9 10 10

00h 11b 01b DVCADR Device Address Register 01h 11b 01b 02h 11b — 03h 11b — 04h 11b — 08h 11b 01b PKTRDY Endpoint Packet-Ready Register 09h 11b — EP0RXCNT Endpoint 0 Receive-Byte Count Register 0Ah 11b —

0Bh 11b — 0Ch 11b — 0Dh 11b — 0Eh — 01b CLRFIFO Transmit FIFO Clear Register 0Fh — 01b SYSCON System Control Register

10h 11b —

11h 11b —

12h 11b —

13h 11b —

14h 11b — wIndexLSB wIndexLSB Setup Register

15h 11b — wIndexMSB wIndexMSB Setup Register

16h 11b —

17h 11b — 1Ah 11b 01b 1Bh 11b 01b 1Ch 11b — INTSTAT Interrupt Status Register 1Dh 11b 01b DMACON DMA Control Register 1Eh 11b 01b 1Fh — —

DVCSTAT Device Status Register PKTERR Packet Error Register FIFOSTAT1 FIFO Status Register 1 FIFOSTAT2 FIFO Status Register 2

EP1RXCNT Endpoint 1 Receive-Byte Count Register EP2RXCNT Endpoint 2 Receive-Byte Count Register

Reserved

REVISION Revision Register

bmRequestType bmRequestType Setup Register bRequest bRequest Setup Register wValueLSB wValueLSB Setup Register wValueMSB wValueMSB Setup Register

wLengthLSB wLengthLSB Setup Register wLengthMSB wLengthMSB Setup Register POLSEL Assertion Select Register INTENBL Interrupt Enable Register

DMAINTVL DMA Interval Register

Reserved

11 11 13 13 14 15 19 19 20

21 21 22 23 23 24 24 24 24 25 25 26 27 28 30 31

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Addresses and Names of Registers (Continued)

Addresses Symbol Register name Page

20h 11b — EP0RXCON Endpoint 0 Receive Control Register 32

21h 11b — EP0RXTGL Endpoint 0 Receive Data Toggle Register 32

22h 11b 01b EP0RXPLD Endpoint 0 Receive Payload Register 33

23h — — Reserved

24h 11b 01b EP1CON Endpoint 1 Control Register 34

25h 11b 01b EP1TGL Endpoint 1 Data Toggle Register 35

26h 11b 01b EP1PLD Endpoint 1 Payload Register 35

27h — — Reserved

28h — — Reserved

29h — — Reserved 2Ah — — Reserved 2Bh — — Reserved 2Ch — — Reserved 2Dh — — Reserved 2Eh — — Reserved 2Fh — — Reserved

30h 11b — EP0TXCON Endpoint 0 Transmit Control Register 36

31h 11b — EP0TXTGL Endpoint 0 Transmit Data Toggle Register 36

32h 11b 01b EP0TXPLD Endpoint 0 Transmit Payload Register 37

33h 11b 01b EP0STAT Endpoint 0 Status Register 38

34h 11b 01b EP2CON Endpoint 2 Control Register 40

35h 11b 01b EP2TGL Endpoint 2 Data Toggle Register 41

36h 11b 01b EP2PLD Endpoint 2 Payload Register 41

37h — — Reserved

38h 11b 01b EP3CON Endpoint 3 Control Register 42

39h 11b 01b EP3TGL Endpoint 3 Data Toggle Register 43 3Ah 11b 01b EP3PLD Endpoint 3 Payload Register 43 3Bh — — Reserved 3Ch — — Reserved 3Dh — — Reserved 3Eh — — Reserved 3Fh — — Reserved

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FUNCTIONS OF REGISTERS

End Point 0 Receive FIFO (EP0RXFIFO)

Read address 40h Write address -

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware resetxxxxxxxx After a bus reset xxxxxxxx Definition EP0 Receive data (R)

The receive data from the host computer in the data state during a control Write transfer is stored in EP0RXFIFO. The EP0 receive data can be read out by the local MPU through reading the address 40h when the ML60851C issues an EP0 receive packet ready interrupt request. It is possible to read successively the data in the packet by reading cont inuousl y.

The EP2RXFIFO is cleared under the following conditions:

1. When the local MPU resets the EP0 receive packet ready bit (A “1” is written in PKTRDY(0)).

2. When a setup packet is received.

3. When the local MCU writes a “0” in the stall bit (EP0STAT(2)).

End Point 1 Receive FIFO (EP1RXFIFO)

Read address 41h Write address —

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware resetxxxxxxxx After a bus reset xxxxxxxx Definition EP1 Receive data (R)

It is possible to read out the EP1 receive data by reading the address 41h. When EP1 is set for bulk reception (BULK OUT), The local MCU should read EP1RXFIFO when the ML60851C issues an EP2 packet ready interrupt request. It is possible to read successively th e data in the packet by readin g continuously. When the data transfer direction of EP1 is set as “Transmit”, all accesses to this address will be invalid. The EP1RXFIFO is cleared under the following conditions:

1. When an OUT token is received for EP1.

2. When the EP1 receive packet ready bit is reset. (A “1” is written in PKTRDY(1).)

3. When the local MCU writes a “0” in the stall bit (EP1CON(1)).

Even when a DMA read with a 16-bit width is made from EP1RXFIFO, the address is A7:A0 = 41h.

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End Point 2 Receive FIFO (EP2RXFIFO)

Read address 42h Write address

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware resetxxxxxxxx After a bus reset xxxxxxxx Definition EP2 Receive data (R)

—

It is possible to read out the EP2 receive data by reading the address 42h. When EP2 is set for bulk reception (Bulk OUT), the local MCU should read EP2R XFIFO when the ML 60851C issues an EP2 packet ready int errupt request. It is possible to read successively the data in the packet by reading con t inuously. When th e data transfer direction of EP2 is set as ‘Transmit’, all accesses to this address will be invalid. The EP2RXFIFO is cleared under the following conditions:

1. When an OUT token is received for EP2.

2. When the EP2 receive packet ready bit is reset. (A “1” is written in PKTRDY(2).)

3. When the local MCU writes a “0” in the stall bit (EP2CON(1)).

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End Point 0 Transmit FIFO (EP0TXFIFO)

Read address — Write address C0h

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware resetxxxxxxxx After a bus reset xxxxxxxx Definition EP0 Transmit data (W)

The EP0 transmit data can be written in by writing to the address C0h. The receive data from the host in the data stage during a control read transfer is stored in EP0TXFIFO . When the ML60851C issues an EP0 transm it pack et ready interrupt request, the local MC U writes the transmit data to the addres s C0h. It is possible to write the packet data successively by writing continuously.

The EP0 TXFIFO is cleared under the following conditions:

1. When an ACK is received from the host for the data transmission from EP0.

2. When a setup packet is received.

End Point 1 Transmit FIFO (EP1TXFIFO)

Read address Write address C1h

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware resetxxxxxxxx After a bus reset xxxxxxxx Definition EP1 Transmit data (W)

—

The EP1 transmit data can be written in by writing to the address C1h. When EP1 has been set for bulk transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851C issues an EP1 packet ready interrupt request. It is possible to write the packet data successively by writing continuously. When the data transfer direction of EP 1 is set as ‘Receive’, all accesses to this add ress will be invalid.

The EP1 transmit FIFO is cleared under the following conditions:

1. When an ACK is received from the host for the data transmission from EP1.

2. When the local MCU writes a “1” in the EP1FIFO clear bit (CLRFIFO(1)).

Even when a DMA write with a 16-bit width is made in EP1TXFIFO, the address is A7:A0 = 41h.

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End Point 2 Transmit FIFO (EP2TXFIFO)

Read address — Write address C2h

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware resetxxxxxxxx After a bus reset xxxxxxxx Definition EP2 Transmit data (W)

The EP2 transmit data can be written in by writing to the address C2h. When EP2 has been set for bulk transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851C issues an EP2 packet ready interrupt request. It is possible to write the packet data successively by writing continuously. When the data transfer direction of EP2 is set as “Receive”, all accesses to this address will be invalid.

The EP2 TXFIFO is cleared under the following conditions:

1. When an ACK is received from the host for the data transmission from EP2.

2. When the local MCU writes a “1” in the EP2FIFO clear bit (CLRFIFO(2)).

End Point 3 Transmit FIFO (EP3TXFIFO)

Read address — Write address C3h

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware resetxxxxxxxx After a bus reset xxxxxxxx Definition EP3 Transmit data (W)

The EP3 transmit data can be written in by writing to the address C3h. Make the local MCU write the transmit data in EP3TXFIFO when the ML60851C issues an EP3 packet ready interrupt request. It is possible to write the packet data successivel y by writing continuously.

The EP3 TXFIFO is cleared under the following conditions:

1. When an ACK is received from the host for the data transmission from EP3.

2. When the local MCU writes a “1” in the EP3FIFO clear bit (CLRFIFO(3)).

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Device Address Register (DVCADR)

Read address C0h Write address 40h

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset00000000 After a bus reset 00000000 Definition Device address (R/W)

The local MCU writes in this register the device address given by the SET_ADDRESS command from the host. Thereafter, the ML60851C responds only to the token specifying this address among all the tokens from the host computer. The default value is the address D6:D0 = 00h.

Note 1: It is possible to carry out addr es s ing usin g a 7- bit ad dr ess because up to 127 devices can be

connected according to the USB standard.

Note 2: The bit D7 is fixed at “0”, and even if a “1” is written in the bit D7, it will be invalid.

Device State Register (DVCSTAT)

Read address C1h Write address 41h

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset00000001 After a bus reset 00000001 Definition 0 0

Default state (R/W) Address state (R/W) Configuration state (R/W) Suspend state (R) Remote wake-up (R/W) USB bus reset status clear (W)

This is a register for displaying the status of the device. The functions of the different bits are described below: The bits D7 and D6 are fixed at “0” and even if a “1” is written in these bits, the write operation will be invalid.

Default state:

This bit is asserted in the initial state. The default state is valid from the time the power is switched ON and the hardware resetting is complete. There is no need to write a “0” in this bit.

Address state:

When a SET_ADDRESS request arrives, the local MCU writes the device address in the device address register. If necessary, by writing a “1” in this bit also at that time, it is possible to give an indication that the ML60851C has entered the address state. Since the content of this bit does not affect the operation of the ML60851C, there is no need to write in this bit if it will not be read out.

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Configuration state:

When the local MPU asserts the configuration bits EP1CON, EP2CON, or EP3CON in response to a SET_CONFIGURATION request from the host computer when this IC is in the address state, by writing a “1” in this bit also, if necessary, at that time, it is possible to give an indication that the ML60851C has entered the configuration st ate. Since the con tent of this bit does n ot affect th e operation of the ML60851C, there is no need to write in this bit if it will not be read out.

Remarks: When all these three states are “1”, it m eans that this IC is normally operating. How ever, since these bits do not affect the operation of the ML60851C, there is no n eed to write in these bits if they will not be read out.

Suspend state:

When the idle condition continues for more than 3ms in the USB bus, the ML60851C au tomatically asserts this bit thereby indicating that it is going into the suspend state. At the same time, bit D6 of the interrupt

status register INTSTAT is asserted and the

INTR

pin is asserted. With this, the local MCU can suppress the current consumption. This bit is deasserted when the EOP of any type of packet is received.

Remote wake-up:

The ML60851C is in the suspend state, the remote wake-up function is activated when the local MCU asserts this bit. When this bit is written while 5ms have not yet elapsed in the idle condit ion, the remote wake-up signal is output after waiting for the idle condition to continue for the full 5ms period. Further, when this bit is written after the idle condition has persisted for 5ms or more, the remote wake-up signal is output immediately after this bit is written. This bit is deasserted auto matically when the suspe nd state is released by receiving the resume instruction over the USB bus.

PEDL60851C-02

ML60851C

USB bus reset status clear:

When the ML60851C is in the USB bu s reset interru pt state (bit D5 of the interrupt statu s register, that is the USB bus reset interrupt status bit is “1” and the

INTR

pin is asserted), it is possible to clear the interrupt

status by writing a “1” in this bit. (This makes the USB bus reset interrupt status bit “0” and deassertes

INTR

.) Although this bit can be read out, the read out value will always be “0”.

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Packet Error Register (PKTERR)

Read address C2h Write address —

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset00000000 After a bus reset 00000000 Definition 0 0

Bit stuff error (R) Data CRC error (R) Address CRC error (R) PID Error (R)

Each bit is asserted when the corresponding error occurs and is deasserted when SOP is received. This register is used to report the error information. This register is useful for the tests during development, or for preparing the error frequency measurement report. This register is n ot particularly required f or the specification of commercial a product.

FIFO Status Register 1 (FIFOSTAT1)

Read address C3h Write address —

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset00001010 After a bus reset 00001010 Definition 0 0

Receive FIFO0 Full (R) Receive FIFO0 Empty (R) FIFO1 Full (R) FIFO1 Empty (R)

This register reports the statuses of the EP0RXFIFO and the FIFO for EP1. N orm ally, there is n o need to read this register because it is sufficient to read the packet ready status before reading out or writing in a FIFO.

Receive FIFO0 Full: This bit becomes “1” when 8-bytes of data are stored in the EP0RXFIFO. This bit is

not set to “1” when a packet less than 8 bytes long (a short packet) is stored in. Receive FIFO0 Empty: This bit will be “1” when the EP0RXFIFO0 is empty. FIFO1 Full: This bit becomes “1” when 64 bytes of data is stored in the FIFO for EP1. This is true

during both transmission and reception. This bit does not become “1” in the case of a

short packet. The FIFO for EP1 has a two-layer structure and can store up to 128

bytes of data. This bit indicates the status of the FIFO in which data being written at

that time. In other words, this bit indicates the status of the FIFO into which the host

computer is writing data when EP1 is receiving data, and of the FIFO into which the

local MCU is writing data when EP1 is transmitting data. FIFO1 Empty: This bit becomes “1” when the FIFO for EP1 is empty. This is true during both

transmission and reception. The FIFO for EP1 has a tw o-layer s tructure and can s tore

up to 128 bytes of data. This bit indicates the status of the FIFO which is being read

out at that time.

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FIFO0 Status Register 2 (FIFOSTAT2)

Read address C4h Write address —

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset00101010 After a bus reset 00101010 Definition 0 0

PEDL60851C-02

ML60851C

Transmit FIFO0 Full (R) Transmit FIFO0 Empty (R) FIFO2 Full (R) FIFO2 Empty (R) FIFO3 Full (R) FIFO3 Empty (R)

This register reports the statuses of the EP0TXFIFO, the FIFO for EP2, and the FIFO for EP3. Normally, there is no need to read this register because it is sufficient to read the packet ready status before reading out or writing in a FIFO.

Transmit FIFO0 Full: This bit becomes “1” when 8-bytes o f data is stored in the EP0TXFIFO. T his bit is

not set to “1” when a packet less than 8 bytes (a short packet) is written in. Transmit FIFO0 Empty: This bit will be “1” when the EP0 transmit FIFO0 is empty. FIFO2 Full: This bit becomes “1” when 64 bytes of data is either stored or written in the FIFO for

EP2. This bit does not become “1” in the case of a short packet. FIFO2 Empty: This bit becomes “1” when the FIFO of EP2 is empty. FIFO3 Full: This bit becomes “1” when 64 bytes are written in the FIFO for EP3. This bit does not

become “1” in the case of a short packet. FIFO3 Empty: This bit becomes “1” when the FIFO for EP3 is empty.

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End Point Packet Ready Register (PKTRDY)

This register indicates whether or not the preparations for reading out or writing in a packet data have been completed. In addition, this register is also used for controlling the handshake packet (ACK/NAK)

Read address C8h Write address 48h

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset00000000 After a bus reset 00000000 Definition 0

EP0 Receive packet ready (R/Reset ) EP1 Receive packet ready (R/Reset ) EP2 Receive packet ready (R/Reset )

EP0 Transmit packet ready (R/Set) EP1 Transmit packet ready (R/Set) EP2 Transmit packet ready (R/Set) EP3 Transmit packet ready (R/Set)

This is the register for indicating that the local MCU can request a read/write of the FIFO for each EP. The logical sums (AND) of each of these bits and the corresponding bits of INTENBL become the bits of INTSTAT.

The ML60851C asserts a receive packet ready bit (set to “0”) and generates an interrupt cause. The local MCU resets the receive packet ready bit after completion of the interrupt servicing (such as taking out data from the corresponding receive FIFO, etc.,).

The ML60851C deasserts a transmit packet ready bit and generates an interrupt cause. The local MCU sets the receive packet ready bit after completion of the interrupt servicing (such as writing data in the corresponding transmit FIFO, etc.,). The bit D3 is fixed at “0”, and even if a “1” is written in this bit, that write operation will be invalid. The operations of the different bits of PKTRDY are described in detail below.

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EP0 Receive packet ready bit (D0)

This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D0 bit.

The conditions of asserting and deasserting this bit are the following.

Bit name Asserting condition Action when asserted

EP0 Receive packet ready (D0)

1. When data is received in EP0 and storing of one packet of receive data in EP0RXFIFO is completed.

2. When a setup packet is received during a control Re ad or a contr ol Write transfer.

EP0 is locked (that is, an NAK is returned automatically when a data packet is received from the host computer).

(In the case of the asserting condition 1, the local MCU can read EP0RXFIFO.)

Bit name Deasserting condition Action when deasserted

EP0 Receive packet ready (D0)

1. When the local MCU resets (writes a “1” in) this bit.

2. When the local MCU resets the setup ready bit during a control Write transfer.

Reception is possible in EP0.

ML60851C

R/Reset: Reading possible/ Reset when a “1” is written R/Set: Reading possible/ Set when a “1” is written

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EP1 Receive Packet Ready Bit (D1)

This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D1 bit. The conditions of asserting and deasserting this bit are the following. EP1 has a two-layer FIFO, and even the packet ready bits are present independently for layer A and layer B. The switching between these two layers is done automatically by the ML60851C.

Bit name Asserting condition Action when asserted

EP1 Receive packet ready (D1)

When an error-free packet is received in either layer A or layer B.

The local MCU can read the EP1RXFIFO. EP1 is locked when both layer A and layer B have received a packet data.

Bit name Deasserting condition Action when deasserted

EP1 Receive packet ready (D1) When the local MCU resets (writes a

“1”) in the bits of both layer A and layer B.

Reception is possible in EP1 w hen at least one of the bits of layer A and layer B has been reset.

See the explanation of the operation of the two-layer FIFO given in the Section on ‘Functional Description’.

EP2 Receive Packet Ready Bit (D2)

This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D2 bit. The conditions of asserting and deasserting this bit are the following.

Bit name Asserting condition Action when asserted

EP2 Receive packet ready (D2) When an error-free packet is

received.

EP2 is locked.

Bit name Deasserting condition Action when deasserted

EP2 Receive packet ready (D2) When the local MCU resets (writes a

“1” in) this bit.

Data reception is possible in EP2.

EP0 Transmit Packet Ready Bit (D4)

This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D4 bit. The conditions of asserting and deasserting this bit are the following.

Bit name Asserting condition Action when asserted

EP0 Transmit packet ready (D4) When the local MCU sets this bit. Data transmission is possible from

EP0.

Bit name Deasserting condition Action when deasserted

EP0 Transmit packet ready (D4)

1. When an ACK is receiv ed from the host computer in response to the data transmission from EP0.

2. When a setup packet is received.

EP0 is locked. In other words, an NAK is returned automatically when an IN token is received from the host computer.

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EP1 Transmit Packet Ready Bit (D5)

This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D5 bit. The conditions of asserting and deasserting this bit are the following. EP1 has a two-layer FIFO, and even the packet ready bits are present independently for layer A and layer B. The switching between these two layers is performed automatically by the ML60851C.

Bit name Asserting condition Action when asserted

EP1 Transmit packet ready (D5)

When the local MCU has set the bits of both layer A and layer B.

Data transmission is possible from EP1 when the bit for at least one of layer A and layer B has been asserted.

Bit name Deasserting condition Action when deasserted

EP1 Transmit packet ready (D5) When an ACK is received from the

host computer for the data transmission from either layer A or layer B.

EP1 is locked when both layer A and layer B have not prepared the transmit data.

See the explanation of the operation of the two-layer FIFO given in the Section on ‘Functional Description’.

EP2 Transmit Packet Ready Bit (D6)

This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D6 bit. The conditions of asserting and negating this bit are the following.

Bit name Asserting condition Action when asserted

EP2 Transmit packet ready (D6) When the local MCU has set this bit. Data transmission is possible from

EP2.

Bit name Deasserting condition Action when deasserted

EP2 Transmit packet ready (D6)

When an ACK is received from the host computer in response to the data transmission from EP2.

EP2 is locked.

EP3 Transmit Packet Ready Bit (D7)

This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D7 bit. The conditions of asserting and deasserting this bit are the following.

Bit name Asserting condition Action when asserted

EP3 Transmit packet ready (D7) When the local MCU has set this bit. Data transmission is possible from

EP3.

Bit name Deasserting condition Action when deasserted

EP2 Transmit packet ready (D7) When an ACK is received from the

host computer in response to the data transmission from EP3.

EP3 is locked.

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PEDL60851C-02

Semiconductor

ML60851C

End Point 0 Receive Byte Count Register (EP0RXCNT)

Read address C9h Write address —

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset00000000 After a bus reset 00000000 Definition 0 Byte count of EP0 (R)

The ML60851C automatically counts the number of bytes in the packet being received by EP0 an d stored it in this register. Although the coun t ing is performed up to the maxim um pack et si ze ente red i n th e payl oad reg i s ter in the case of a full packet, the count will be less than this value in t he case o f a short p acket. The local MCU refers to this value and reads the data of one packet from the EP0RXFIFO.

The EP0 receive byte count register is cleared under the following conditions:

1. When the local MCU resets the EP0 receive packet ready bit (by writing a “1” in PKTRDY(0)).

2. When a setup packet is received.

3. When the local MCU writes a “0” in the stall bit (EP0STAT(2)).

End Point 1 Receive Byte Count Register (EP1RXCNT)

Read address CAh Write address —

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset00000000 After a bus reset 00000000 Definition 0 Byte count of EP1 (R)

The ML60851C automatically counts the number of bytes in the packet being received by EP1 an d stored it in this register. Although the coun t ing is performed up to the maxim um pack et si ze ente red i n th e payl oad reg i s ter in the case of a full packet, the count will be less than this value in t he case o f a short p acket. The local MCU refers to this value and reads the data of one packet from the EP1 receive FIFO.

This register is invalid when the EP1 transfer direction is set as ‘Transmit’.

The EP1 receive byte count register is cleared under the following conditions:

1. When an OUT token is received for EP1.

2. When the EP1 receive packet ready bit is reset (by writing a “1” in PKTRDY(1)).

3. When the local MCU writes a “0” in the stall bit (EP1CON(1)).

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PEDL60851C-02

Semiconductor

ML60851C

End Point 2 Receive Byte Count Register (EP2RXCNT)

Read address CBh Write address —

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset00000000 After a bus reset 00000000 Definition 0 Byte Count of EP2 (R)

The ML60851C automatically counts the number of bytes in the packet being received by EP2 an d stored it in this register. Although the coun t ing is performed up to the maxim um pack et si ze ente red i n th e payl oad reg i s ter in the case of a full packet, the count will be less than this value in the case o f a short packet. T he local MCU refers to this value and reads the data of one packet from the EP2RXFIFO.

This register is invalid when the EP2 transfer direction is set as ‘Transmit’.

The EP2 receive byte count register is cleared under the following conditions:

1. When an OUT token is received for EP2.

2. When the EP2 receive packet ready bit is reset (by writing a “1” in PKTRDY(2)).

3. When the local MCU writes a “0” in the stall bit (EP2CON(1)).

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Semiconductor

Revision Register (REVISION)

Read address CDh Write address —

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset After a bus reset Definition

Revision No. of Chip

Transmit FIFO Clear Register (CLRFIFO)

Read address — Write address 4Eh

D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset After a bus reset Definition 0 0 0 0

Cannot be read (indeterminate) Cannot be read (indeterminate)

PEDL60851C-02

ML60851C

EP1 Transmit FIFO Clear EP2 Transmit FIFO Clear EP3 Transmit FIFO Clear

EP1 to EP3 FIFO Clear: When each EP has been set for transmission, by writing a “1” in these bits, the

corresponding FIFOs are cleared at the Write pulse and also the corresponding EP Packet Ready bits are reset.

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