NXP Semiconductors UM10310 User Manual

UM10310

P89LPC9321 User manual

Rev. 2 — 1 November 2010 User manual

Document information

Info Content Keywords P89LPC9321 Abstract Technical information for the P89LPC9321 device

NXP Semiconductors

UM10310

P89LPC9321 User manual

Revision history

Rev Date Description

v.2 20101101

• Section 2.3: added low speed oscillator information.

• Section 15.1: added low speed oscillator information.

• Section 15.3: added low speed oscillator information.

• Section 15.5: added low speed oscillator information.

• Table 8: added low speed oscillator information.

v.1 20081201 Initial version.

Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

User manual Rev. 2 — 1 November 2010 2 of 139

NXP Semiconductors

P89LPC9321FDH

002aae104

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

18

17

20

19

22

21

24

23

26

25

28

27

P2.0/ICB

P2.1/OCD

P0.0/CMP2/KBI0

P1.7/OCC

P1.6/OCB

P1.5/RST

V

SS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

V

DD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

1. Introduction

The P89LPC9321 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC9321 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9321 in order to reduce component count, board space, and system cost.

1.1 Pin configuration

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P89LPC9321 User manual

User manual Rev. 2 — 1 November 2010 3 of 139

Fig 1. TSSOP28 pin configuration

NXP Semiconductors

P89LPC9321FA

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5

6

7

8

9

10

11

25

24

23

22

21

20

19

121314

15

161718

4

3

2

1

28

27

26

P1.6/OCB

P1.5/RST

V

SS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.7/OCC

P0.0/CMP2/KBI0

P2.1/OCD

P2.0/ICB

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

V

DD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P2.4/SS

P1.1/RXD

P1.0/TXD

P89LPC9321FN

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2

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24

23

26

25

28

27

P2.0/ICB

P2.1/OCD

P0.0/CMP2/KBI0

P1.7/OCC

P1.6/OCB

P1.5/RST

V

SS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

V

DD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

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User manual Rev. 2 — 1 November 2010 4 of 139

Fig 2. PLCC28 pin configuration

Fig 3. DIP28 pin configuration

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1.2 Pin description

Table 1. Pin description

Symbol Pin Type Description

P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset

P0.0/CMP2/ KBI0 3 I/O P0.0 — Port 0 bit 0.

P0.1/CIN2B/ KBI1

P0.2/CIN2A/ KBI2

P0.3/CIN1B/ KBI3

P0.4/CIN1A/ KBI4

P0.5/CMPREF/ KBI5

P0.6/CMP1/ KBI6 20 I/O P0.6 — Port 0 bit 6. High current source.

P0.7/T1/KBI7 19 I/O P0.7 — Port 0 bit 7. High current source.

P1.0 to P1.7 I/O, I

Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 4.1 “

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

O CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0.

26 I/O P0.1 — Port 0 bit 1.

I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1.

25 I/O P0.2 — Port 0 bit 2.

I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2.

24 I/O P0.3 — Port 0 bit 3. High current source.

I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3.

23 I/O P0.4 — Port 0 bit 4. High current source.

I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — ADC1 channel 3 analog input.

22 I/O P0.5 — Port 0 bit 5. High current source.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5.

O CMP1 — Comparator 1 output. I KBI6 — Keyboard input 6.

I/O T1 — Timer/counter 1 external count input or overflow output. I KBI7 — Keyboard input 7.

Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for

[1]

three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to

Section 4.1 “

used as outputs. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

Port configurations” for details.

Port configurations” for details. P1.2 to P1.3 are open drain when

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P89LPC9321 User manual

Table 1. Pin description

Symbol Pin Type Description

P1.0/TXD 18 I/O P1.0 — Port 1 bit 0.

P1.1/RXD 17 I/O P1.1 — Port 1 bit 1.

P1.2/T0/SCL 12 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).

P1.3/INT0

P1.4/INT1

P1.5/RST

P1.6/OCB 5 I/O P1.6 — Port 1 bit 6. High current source.

P1.7/OCC 4 I/O P1.7 — Port 1 bit 7. High current source.

P2.0 to P2.7 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset

P2.0/ICB 1 I/O P2.0 — Port 2 bit 0.

P2.1/OCD 2 I/O P2.1 — Port 2 bit 1.

P2.2/MOSI 13 I/O P2.2 — Port 2 bit 2.

P2.3/MISO 14 I/O P2.3 — Port 2 bit 3.

P2.4/SS

/SDA 11 I/O P1.3 — Port 1 bit 3 (open-drain when used as output).

10 I/O P1.4 — Port 1 bit 4. High current source.

6IP1.5 — Port 1 bit 5 (input only).

15 I/O P2.4 — Port 2 bit 4.

…continued

O TXD — Transmitter output for serial port.

I RXD — Receiver input for serial port.

I/O T0 — Timer/counter 0 external count input or overflow output (open-drain when

used as output).

2

I/O SCL — I

I INT0 I/O SDA — I

I INT1

I RST

functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode.

O OCB — Output Compare B

O OCC — Output Compare C.

Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 4.1 “

All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below:

I ICB — Input Capture B.

O OCD — Output Compare D.

I/O MOSI — SPI master out slave in. When configured as master, this pin is output;

when configured as slave, this pin is input.

I/O MISO — When configured as master, this pin is input, when configured as slave,

this pin is output.

I/O SS

C-bus serial clock input/output.

— External interrupt 0 input.

2

C-bus serial data input/output.

— External interrupt 1 input.

— External Reset input during power-on or if selected via UCFG1. When

Port configurations” for details.

— SPI Slave select.

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P89LPC9321 User manual

Table 1. Pin description …continued

Symbol Pin Type Description

P2.5/SPICLK 16 I/O P2.5 — Port 2 bit 5.

I/O SPICLK — SPI clock. When configured as master, this pin is output; when

configured as slave, this pin is input.

P2.6/OCA 27 I/O P2.6 — Port 2 bit 6.

O OCA — Output Compare A.

P2.7/ICA 28 I/O P2.7 — Port 2 bit 7.

I ICA — Input Capture A.

P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset

Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 4.1 “

All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below:

P3.0/XTAL2/ CLKOUT

P3.1/XTAL1 8 I/O P3.1 — Port 3 bit 1.

V

SS

V

DD

9I/OP3.0 — Port 3 bit 0.

O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is

selected via the flash configuration.

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).

It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer.

I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not

used to generate the clock for the RTC/system timer. 7IGround: 0 V reference. 21 I Power supply: This is the power supply voltage for normal operation as well as

Idle and Power-down modes.

Port configurations” for details.

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

User manual Rev. 2 — 1 November 2010 7 of 139

NXP Semiconductors

V

DD

V

SS

PORT 0

PORT 3

TXD RXD T0 INT0 INT1 RST

SCL SDA

002aae103

CMP2 CIN2B CIN2A CIN1B CIN1A

CMPREF

CMP1

T1

XTAL2

XTAL1

KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7

MOSI MISO SS SPICLK

PORT 1

PORT 2

P89LPC9321

OCB OCC

ICB OCD

OCA ICA

CLKOUT

1.3 Functional diagram

Fig 4. Functional diagram

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P89LPC9321 User manual

User manual Rev. 2 — 1 November 2010 8 of 139

NXP Semiconductors

ACCELERATED 2-CLOCK 80C51 CPU

8 kB

CODE FLASH

256-BYTE

DATA RAM

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU clock

CONFIGURABLE

OSCILLATOR

ON-CHIP RC OSCILLATOR WITH CLOCK

DOUBLER

internal bus

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aae102

UART

ANALOG

COMPARATORS

512-BYTE

AUXILIARY RAM

I2C-BUS

512-BYTE

DATA EEPROM

PORT 3

CONFIGURABLE I/Os

CCU (CAPTURE/ COMPARE UNIT)

P89LPC9321

WATCHDOG TIMER

AND OSCILLATOR

TIMER 0 TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

SPI

P3[1:0]

P2[7:0]

P1[7:0]

P0[7:0]

TXD RXD

SCL SDA

T0 T1

CMP2 CIN2B CIN2A CMP1 CIN1A CIN1B

OCA OCB OCC OCD ICA ICB

SPICLK MOSI MISO SS

CRYSTAL

OR

RESONATOR

XTAL2

XTAL1

1.4 Block diagram

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P89LPC9321 User manual

Fig 5. Block diagram

User manual Rev. 2 — 1 November 2010 9 of 139

NXP Semiconductors

1.5 Special function registers

Remark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

UM10310

P89LPC9321 User manual

– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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User manual Rev. 2 — 1 November 2010 11 of 139

Table 2. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 0000 0000 AUXR1 Auxiliary

B* B register F0H 00 0000 0000 BRGR0

BRGR1

BRGCON Baud rate

CCCRA Capture

CCCRB Capture

CCCRC Capture

CCCRD Capture

CMP1 Comparator 1

CMP2 Comparator 2

DEECON Data EEPROM

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Bit functions and addresses Reset value

function register

[2]

Baud rate generator 0 rate low

[2]

Baud rate generator 0 rate high

generator 0 control

compare A control register

compare B control register

compare C control register

compare D control register

control register

addr.

Bit addressE7E6E5E4E3E2E1E0

A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0

Bit addressF7F6F5F4F3F2F1F0

BEH 00 0000 0000

BFH 00 0000 0000

BDH------SBRGSBRGEN00

EAH ICECA2 ICECA1 ICECA0 ICESA ICNFA FCOA OCMA1 OCMA0 00 0000 0000

EBH ICECB2 ICECB1 ICECB0 ICESB ICNFB FCOB OCMB1 OCMB0 00 0000 0000

ECH - - - - - FCOC OCMC1 OCMC0 00 xxxx x000

EDH - - - - - FCOD OCMD1 OCMD0 00 xxxx x000

ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00

ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00

F1H EEIF HVERR ECTL1 ECTL0 - EWERR1 EWERR0 EADR8 08 00001000

MSB LSB Hex Binary

[2]

[1]

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User manual Rev. 2 — 1 November 2010 12 of 139

Table 2. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

DEEDA T Data EEPROM

DEEADR Data EEPROM

DIVM CPU clock

DPTR Data pointer

DPH Data pointer

DPL Data pointer

FMADRH Program flash

FMADRL Program flash

FMCON Program flash

FMDATA Program flash

I2ADR I

I2CON* I

I2DAT I

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data register

address register

divide-by-M control

(2 bytes)

high

low

address high

address low

control (Read) Program flash

control (Write)

data

2

C-bus slave address register

Bit address DF DE DD DC DB DA D9 D8

2

C-bus control register

2

C-bus data register

…continued

Bit functions and addresses Reset value

addr.

F2H 00 0000 0000

F3H 00 0000 0000

95H 00 0000 0000

83H 00 0000 0000

82H 00 0000 0000

E7H 00 0000 0000

E6H 00 0000 0000

E4H BUSY - - - HVA HVE SV OI 70 0111 0000

E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0

E5H 00 0000 0000

DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000

D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0

DAH

MSB LSB Hex Binary

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User manual Rev. 2 — 1 November 2010 13 of 139

Table 2. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

I2SCLH Serial clock

I2SCLL Serial clock

I2STAT I

ICRAH Input capture A

ICRAL Input capture A

ICRBH Input capture B

ICRBL Input capture B

IEN0* Interrupt

IEN1* Interrupt

IP0* Interrupt

IP0H Interrupt

IP1* Interrupt

IP1H Interrupt

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generator/SCL duty cycle register high

generator/SCL duty cycle register low

2

C-bus status register

register high

register low

register high

register low

Bit address AF AE AD AC AB AA A9 A8

enable 0

Bit address EF EE ED EC EB EA E9 E8

enable 1

Bit address BF BE BD BC BB BA B9 B8

priority 0

priority 0 high

Bit address FF FE FD FC FB FA F9 F8

priority 1

priority 1 high

…continued

Bit functions and addresses Reset value

addr.

MSB LSB Hex Binary

DDH 00 0000 0000

DCH 00 0000 0000

D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 1111 1000

ABH 00 0000 0000

AAH 00 0000 0000

AFH 00 0000 0000

AEH 00 0000 0000

A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 0000

[1]

00x0 0000

x000 0000

E8H EIEE EST - ECCU ESPI EC EKBI EI2C 00

B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00

B7H - PWDRTH PBOH PSH/

PT1H PX1H PT0H PX0H 00

PSRH

[1]

00x0 0000

F8H PIEE PST - PCCU PSPI PC PKBI PI2C 00

F7H PIEEH PSTH - PCCUH PSPIH PCH PKBIH PI2CH 00

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User manual Rev. 2 — 1 November 2010 14 of 139

Table 2. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

KBCON Keypad control

KBMASK Keypad

KBPA TN Keypad pattern

OCRAH Output

OCRAL Output

OCRBH Output

OCRBL Output

OCRCH Output

OCRCL Output

OCRDH Output

OCRDL Output

P0* Port 0 80H T1/KB7 CMP1

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…continued

Bit functions and addresses Reset value

addr.

94H------PATN

register

86H 00 0000 0000 interrupt mask register

93H FF 1111 1111 register

EFH 00 0000 0000 compare A register high

EEH 00 0000 0000 compare A register low

FBH 00 0000 0000 compare B register high

FAH 00 0000 0000 compare B register low

FDH 00 0000 0000 compare C register high

FCH 00 0000 0000 compare C register low

FFH 00 0000 0000 compare D register high

FEH 00 0000 0000 compare D register low

Bit address8786858483828180

Bit address9796959493929190

MSB LSB Hex Binary

/KB6

CMPREF

/KB5

CIN1A

/KB4

CIN1B

/KB3

CIN2A

/KB2

_SEL

CIN2B

/KB1

KBIF 00

CMP2

/KB0

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[1]

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[1]

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User manual Rev. 2 — 1 November 2010 15 of 139

Table 2. Special function registers …continued

* indicates SFRs that are bit addressable.

Name Description SFR

P1* Port 1 90H OCC OCB RST INT1 INT0/SDA T0/SCL RXD TXD

P2* Port 2 A0H ICA OCA SPICLK SS

P3*Port3B0H------XTAL1XTAL2 P0M1 Port 0 output

P0M2 Port 0 output

P1M1 Port 1 output

P1M2 Port 1 output

P2M1 Port 2 output

P2M2 Port 2 output

P3M1 Port 3 output

P3M2 Port 3 output

PCON Power control

PCONA Power control

PSW* Program status

PT0AD Port 0 digital

RSTSRC Reset source

RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

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Bit functions and addresses Reset value

addr.

Bit addressA7A6A5A4A3A2A1A0

Bit addressB7B6B5B4B3B2B1B0

84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF

mode 1

85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00

mode 2

91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3

mode 1

92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00

mode 2

A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF mode 1

A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00 mode 2

B1H------(P3M1.1)(P3M1.0)03 mode 1

B2H------(P3M2.1)(P3M2.0)00 mode 2

87H SMOD1 SMOD0 - BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000

register

B5H RTCPD DEEPD VCPD - I2PD SPPD SPD CCUPD 00 register A

Bit addressD7D6D5D4D3D2D1D0

D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000 word

F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x input disable

DFH - BOIF BOF POF R_BK R_WD R_SF R_EX

register

MSB LSB Hex Binary

MISO MOSI OCD ICB

NXP Semiconductors

[1]

1111 1111

[1]

0000 0000

[1]

11x1 xx11

[1]

00x0 xx00

[1]

1111 1111

[1]

0000 0000

[1]

xxxx xx11

[1]

xxxx xx00

[1]

0000 0000

P89LPC9321 User manual

UM10310

[3]

[1][6]

011x xx00

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Table 2. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

RTCH RTC register

RTCL RTC register

SADDR Serial port

SADEN Serial port

SBUF Serial Port data

SCON* Serial port

SSTAT Serial port

SP Stack pointer 81H 07 0000 0111 SPCTL SPI control

SPSTAT SPI status

SPDAT SPI data

TAMOD Timer 0 and 1

TCON* Timer 0 and 1

TCR20* CCU control

TCR21 CCU control

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…continued

Bit functions and addresses Reset value

addr.

D2H 00 high

D3H 00 low

A9H 00 0000 0000 address register

B9H 00 0000 0000 address enable

99H xx xxxx xxxx

buffer register

Bit address 9F 9E 9D 9C 9B 9A 99 98

98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000

control

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 extended status register

E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 0000 0100

register

E1HSPIFWCOL------0000xxxxxx

register

E3H 00 0000 0000

register

8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0

auxiliary mode

Bit address 8F 8E 8D 8C 8B 8A 89 88

88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000

control

C8H PLEEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 00 0000 0000

register 0

F9H TCOU2 - - - PLLDV.3 PLLDV.2 PLLDV.1 PLLDV.0 00 0xxx 0000

register 1

MSB LSB Hex Binary

[6]

NXP Semiconductors

0000 0000

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UM10310

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User manual Rev. 2 — 1 November 2010 17 of 139

Table 2. Special function registers …continued

* indicates SFRs that are bit addressable.

Name Description SFR

TH0 Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TH2 CCU timer high CDH 00 0000 0000 TICR2 CCU interrupt

TIFR2 CCU interrupt

TISE2 CCU interrupt

TL0 Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TL2 CCU timer low CCH 00 0000 0000 TMOD Timer 0 and 1

TOR2H CCU reload

TOR2L CCU reload

TPCR2H Prescaler

TPCR2L Prescaler

TRIM Internal

WDCON Watchdog

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Bit functions and addresses Reset value

addr.

C9H TOIE2 TOCIE2D T OCIE2C TOCIE2B TOCIE2A - TICIE2B TICIE2A 00 0000 0x00

control register

E9H TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A - TICF2B TICF2A 00 0000 0x00

flag register

DEH - - - - - ENCINT.2 ENCINT.1 ENCINT.0 00 xxxx x000 status encode register

89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 0000 0000

mode

CFH 00 0000 0000 register high

CEH 00 0000 0000 register low

CBH------TPCR2H.1TPCR2H.000xxxx xx00 control register high

CAH TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L .0 00 0000 0000 control register low

96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 oscillator trim register

A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK

control register

MSB LSB Hex Binary

[5][6]

[4][6]

NXP Semiconductors

P89LPC9321 User manual

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User manual Rev. 2 — 1 November 2010 18 of 139

Table 2. Special function registers …continued

* indicates SFRs that are bit addressable.

Name Description SFR

WDL Watchdog load C1H FF 1111 1111 WFEED1 Watchdog

WFEED2 Watchdog

[1] All ports are in input only (high-impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the UM10310 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.

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Bit functions and addresses Reset value

addr.

C2H

feed 1

C3H

feed 2

reset value is x0110000.

Other resets will not affect WDTOF.

MSB LSB Hex Binary

NXP Semiconductors

P89LPC9321 User manual

UM10310

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User manual Rev. 2 — 1 November 2010 19 of 139

Table 3. Extended special function registers

Name Description SFR

BODCFG BOD

CLKCON CLOCK Control

PGACON1 PGA1 control

PGACON1B PGA1 control

PGA1TRIM8X16X PGA1 trim

PGA1TRIM2X4X PGA1 trim

RTCDATH Real-time clock

RTCDATL Real-time clock

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configuration register

register

register B

register

data register high

data register low

[1]

Bit functions and addresses Reset value

addr.

FFC8H - - - - - - BOICFG1 BOICFG0

FFDEH CLKOK - - XTALWD CLKDBL FOSC2 FOSC1 FOSC0

FFE1H ENPGA1 PGASEL11PGASEL10PGATRIM

MSB LSB Hex Binary

[2]

[3]

1000 0100

- - PGAG11 PGAG10 00 0000 0000

1

FFE4H - - - - - - - PGAENO

00 0000 0000

FF1

FFE3H 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIM0 8XTRIM3 8XTRIM2 8XTRIM1 8XTRIM0

FFE2H 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIM0 2XTRIM3 2XTRIM2 2XTRIM1 2XTRIM0

[4]

FFBFH 00 0000 0000

FFBEH 00 0000 0000

NXP Semiconductors

[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDAT A). The MOVX A,@DPTR and MOVX @DPTR,A instructions are

used to access these extended SFRs. [2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset. [3] CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit

comes from UCFG2.7. [4] On power-on reset and watchdog reset, the PGAxTRIM8X16X and PGAxTRIM2X4X registers are initialized with a factory preprogrammed value. Other resets will not cause

initialization.

P89LPC9321 User manual

UM10310

NXP Semiconductors

002aae090

0000h

03FFh

0400h

07FFh

0800h

0BFFh

0C00h

0FFFh

SECTOR 0

SECTOR 1

SECTOR 2

SECTOR 3

1000h

13FFh

1400h

17FFh

1800h

1BFFh

1C00h

1E00h

1FFFh

SECTOR 4

SECTOR 5

SECTOR 6

FFEFh

FF00h

IAP entry-

points

SECTOR 7

ISP CODE

(512B)

(1)

SPECIAL FUNCTION

REGISTERS

(DIRECTLY ADDRESSABLE)

128 BYTES ON-CHIP

DATA MEMORY (STACK,

DIRECT AND INDIR. ADDR.)

4 REG. BANKS R[7:0]

data memory

(DATA, IDATA)

data EEPROM

DATA

128 BYTES ON-CHIP

DATA MEMORY (STACK

AND INDIR. ADDR.)

IDATA (incl. DATA)

FFEFh FFh

80h

7Fh

00h

FF1Fh

FF00h

entry points for:

-51 ASM. code

-C code

IDATA routines

1FFFh

1E00h

entry points for:

-UART (auto-baud)

-I2C, SPI, etc.

(1)

ISP serial loader

entry points

read-protected

IAP calls only

DATA EEPROM

(512 BYTES)

[SFR ACCESS]

01FFh

0000h

EXTENDED SFRs

FFFFh

FFB0h

RESERVED

01FFh

XDATA

(512 BYTES)

0000h

1.6 Memory organization

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P89LPC9321 User manual

Fig 6. P89LPC9321 memory map

The various P89LPC9321 memory spaces are as follows: DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or

indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack

User manual Rev. 2 — 1 November 2010 20 of 139

may be in this area. IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Sele cted CPU registers and peripheral control and status registers, accessible only via direct addressing.

XDATA — ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC9321 has 512 b ytes of on-chip XDATA memory, plus extended SFRs located in XDATA.

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9321 has 8 kB of on-chip Code memory.

The P89LPC9321 also has 512 bytes of on-chip Data EEPROM that is accessed via SFRs (see Section Section 17 “

Data EEPROM”).

NXP Semiconductors

Table 4. Data RAM arrangement

Type Data RAM Size (bytes)

DATA Directly and indirectly addressable memory 128 IDATA Indirectly addressable memory 256 XDATA Auxiliary (‘External Data’) on-chip memory that is accessed using

2. Clocks

2.1 Enhanced CPU

The P89LPC9321 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definitions

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P89LPC9321 User manual

512

the MOVX instructions

The P89LPC9321 device has several internal clocks as defined below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources and can also be optionally divided to a slower frequency (see Figure 8

Section 2.10 “

CPU Clock (CCLK) modification: DIVM register”). Note: f

the OSCCLK frequency. CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.The clock doubler option, when enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is

2.2.1 Oscillator Clock (OSCCLK)

The P89LPC9351 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source.

2.3 External crystal oscillator option

The external crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK and RTC. Low speed oscillator option can be the clock source of WDT.

CCLK

⁄2.

and

is defined as

osc

2.3.1 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

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NXP Semiconductors

2.3.2 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

2.3.3 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration.

2.4 Clock output

The P89LPC9321 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-time Clock and Watchdog Timer are not using the crystal oscillator as their clock source. This allows external devices to synchronize to the P89LPC9321. This output is enabled by the ENCLK bit in the TRIM register.

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P89LPC9321 User manual

The frequency of this clock output is

1

⁄2 that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of other bits of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

2.5 On-chip RC oscillator option

The P89LPC9321 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. (Note: the initial value is better than 1 %; please refer to the P89LPC9321 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency. When the clock doubler option is enabled (UCFG2.7 = 1), the output frequency is doubled. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be se t in software if CCLK is runni ng at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until V its specified level.

Table 5. On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 Reset 0 0 Bits 5:0 loaded with factory stored value during reset.

has reached

DD

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002aad364

XTAL1

XTAL2

quartz crystal or

ceramic resonator

(1)

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P89LPC9321 User manual

Table 6. On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit Symbol Description

0 TRIM.0 Trim value. Determines the frequency of the internal RC oscillator. During reset, 1TRIM.1 2TRIM.2 3TRIM.3

these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to

this register. 4TRIM.4 5TRIM.5

CCLK

6 ENCLK when = 1,

⁄2 is output on the XTAL2 pin provided the crystal oscillator is not

being used. 7 RCCLK when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for

fast switching between any clock source and the internal RC oscillator without

needing to go through a reset cycle.

2.6 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to ± 5 % at room temperature. This oscillator can be used to save power when a high clock frequency is not needed.

2.7 External clock input option

In this configuration, the processor clock is derived from an external source driving the XT AL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 Mhz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until V

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low

frequency crystals (see text).

Fig 7. Using the crystal oscillator.

has reached its specified level.

DD

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NXP Semiconductors

÷2

002aae108

RTC

CPU

WDT

DIVM

CCLK

UART

OSCCLK

I2C-BUS

PCLK

TIMER 0 AND

TIMER 1

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

RC OSCILLATOR

WITH CLOCK DOUBLER

WATCHDOG

OSCILLATOR

(7.3728 MHz/14.7456 MHz ± 1 %)

PCLK

RCCLK

SPI

CCU

32 × PLL

(400 kHz ± 5 %)

UM10310

P89LPC9321 User manual

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals (see text).

Fig 8. Block diagram of oscillator control.

Table 7. Clock control register (CLKCON - address FFDEh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol CLKOK - - XTALWD CLKDBL FOSC2 FOSC1 FOSC0 Reset1000xxxx

Table 8. Clock control register (CLKCON - address FFDEh) bit description

Bit Symbol Description

2:0 FOSC2, FOSC1,

3 CLKDBL Clock doubler option for clock switch. When set, doubles the output frequency of the

4 XTALWD Low speed external crystal oscillator as the clock source of watchdog timer. When

6:5 - reserved 7 CLKOK Clock switch completed flag. When = 1, clock switch is completed. When =0, clock

User manual Rev. 2 — 1 November 2010 24 of 139

2.8 Clock sources switch on the fly

P89LPC9321 can implement clock source switch in any sources of watchdog oscillator, 7/14MHz IRC oscillator, external crystal oscillator and external clock input during code is running. CLKOK bit in register CLKCON is read only and used to indicate the clock switch status. When CLKOK is ‘0’, clock switch is processing, not completed. When CLKOK is ‘1’, clock switch is completed. When start new clock source switch, CLKOK is cleared automatically. Notice that when CLKOK is ‘0’, Writing to CLKCON register is not allowed. During reset, CLKCON register value comes from UCFG1 and UCFG2. Th e reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.

CPU oscillator type selection for clock switch. See Section 2

FOSC0

information. Combinations other than those shown in Table 9

use should not be used.

internal RC oscillator.

= 0, disable the external crystal oscillator as the clock source of watchdog timer.

switch is processing and writing to register CLKCON is not allowed.

for additional are reserved for future

NXP Semiconductors

UM10310

P89LPC9321 User manual

Table 9. Oscillator type selection for clock switch

FOSC[2:0] Oscillator configuration

111 External clock input on XTAL1. 100 Watchdog Oscillato r, 400 kHz ± 5 %. 011 Internal RC oscillator, 7.373 MHz ± 1 %. 010 Low frequency crystal, 20 kHz to 100 kHz. 001 Medium frequency crystal or resonator, 100 kHz to 4 MHz. 000 High frequency crystal or resonator, 4 MHz to 18 MHz.

2.9 Oscillator Clock (OSCCLK) wake-up delay

The P89LPC9321 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 μsto100μs. If the clock source is the internal RC oscillator, the delay is 200 μsto300μs. If the clock source is watchdog oscillator or external clock, the delay is 32 OSCCLK cycles.

2.10 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

2.1 1 Low power select

3. Interrupts

CCLK frequency = f

Where: f

is the frequency of OSCCLK, N is the value of DIVM.

osc

Since N ranges from 0 to 255, the CCLK frequency can be in the range of f (for N = 0, CCLK = f

osc

).

/ (2N)

osc

to f

osc

/510.

This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

The P89LPC9321 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be se t to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

The P89LPC9321 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC9321’s 15 interrupt sources.

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NXP Semiconductors

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a glo bal enable bit, EA, which enables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbit ra tio n ra nk ing is only us ed for pen din g req ue sts of the same priority level. Table 11 addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake-up the CPU from a Power-down mode.

3.1 Interrupt priority structure

Table 10. Interrupt priority level

Priority bits IPxH IPx Interrupt priority level

0 0 Level 0 (lowest priority) 0 1 Level 1 1 0 Level 2 1 1 Level 3

UM10310

P89LPC9321 User manual

summarizes the interrupt sources, flag bits, vector

There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt has two bits in IPx and IPxH (x = 0, 1) and can therefore be assigned to one of four levels, as shown in Table 11

.

The P89LPC9321 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is triggered by a low level detected at the INTn triggered. In this mode if consecutive samples of the INTn

pin. If ITn = 1, external interrupt n is edge

pin show a high level in one cycle and a low level in the next cycle, interrupt request flag IEn in TCON is set, causing an interrupt request.

Since the external interrupt pins are sample d once each machine cycle, an input high or low level should be held for at least one machine cycle to ensure proper sampling. If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU when the service routine is called.

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If the external interrupt is level-triggered, the external source must h old the re quest a ctive until the requested interrupt is generated. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.

If an external interrupt has been programmed as level-triggered and is enabled when the P89LPC9321 is put into Power-down mode or Idle mode, the interrupt occurrence will cause the processor to wake-up and resume operation. Refer to Section 5.3 “

Power reduction modes” for details. Note: the external interrupt must be programmed as

level-triggered to wake-up from Power-down mode.

3.2 External Interrupt pin glitch suppression

Most of the P89LPC9321 pins have glitch suppression circuits to reject short glitches (please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter specifications). However, pins SDA/INT0 suppression circuits. Therefore, INT1

Table 11. Summary of interrupts

Description Interrupt flag

External interrupt 0 IE0 0003h EX0 (IEN0.0) IP0H.0, IP0.0 1 (highest) Yes Timer 0 interrupt TF0 000Bh ET0 (IEN0.1) IP0H.1, IP0.1 4 No External interrupt 1 IE1 0013h EX1 (IEN0.2) IP0H.2, IP0.2 7 Yes Timer 1 interrupt TF1 001Bh ET1 (IEN0.3) IP0H.3, IP0.3 10 No Serial port Tx and Rx TI and RI 0023h ES/ESR (IEN0.4) IP0H.4, IP0.4 13 No Serial port Rx RI Brownout detect BOIF 002Bh EBO (IEN0.5) IP0H.5, IP0.5 2 Yes Watchdog timer/Real-time

clock

2

C interrupt SI 0033h EI2C (IEN1.0) IP0H.0, IP0.0 5 No

I KBI interrupt KBIF 003Bh EKBI (IEN1.1) IP0H.0, IP0.0 8 Yes Comparators 1 and 2

interrupts SPI interrupt SPIF 004Bh ESPI (IEN1.3) IP1H.3, IP1.3 14 No Capture/Compare Unit 005Bh ECCU(IEN1.4) IP1H.4, IP1.4 6 No Serial port Tx TI 006Bh EST (IEN1.6) IP0H.0, IP0.0 12 No Data EEPROM write

complete

Vector

bit(s)

WDOVF/RTCF 0053h EWDRT (IEN0.6) IP0H.6, IP0.6 3 Yes

CMF1/CMF2 0043h EC (IEN1.2) IP0H.0, IP0.0 11 Yes

address

0073h EAD (IEN1.7) IP1H.7, IP1.7 15 (lowest) No

Interrupt enable bit(s)

/P1.3 and SCL/T0/P1.2 do not have the glitch

has glitch suppression while INT0 does not.

Interrupt priority

Arbitration ranking

Powerdown wake-up

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002aae160

IE0

EX0

IE1

EX1

BOIF

EBO

KBIF

EKBI

interrupt to CPU

wake-up (if in power-down)

EWDRT

CMF2 CMF1

EC

EA (IE0.7)

TF1

ET1

TI & RI/RI

ES/ESR

TI

EST

SI

EI2C

SPIF ESPI

RTCF ERTC

(RTCCON.1)

WDOVF

TF0

ET0

any CCU interrupt

ECCU

EEIF

EIEE

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P89LPC9321 User manual

Fig 9. Interrupt sources, interrupt enables, and power-down wake-up sources.

4. I/O ports

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The P89LPC9321 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1,and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen (see Table 12

Table 12. Number of I/O pins available

Clock source Reset option Number of I/O

On-chip oscillator or watchdog oscillator

External clock input No external reset (except during power up) 25

Low/medium/high speed oscillator (external crystal or resonator)

No external reset (except during power up) 26 External RST

External RST No external reset (except during power up) 24 External RST

).

pins

pin supported 25

pin supported 24

pin supported 23

NXP Semiconductors

4.1 Port configurations

All but three I/O port pins on the P89LPC9321 may be configured by software to one of four types on a pin-by-pin basis, as shown in Table 13 (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin.

UM10310

P89LPC9321 User manual

. These are: quasi-bidirectional

P1.5 (RST P1.2 (SCL/T0) and P1.3 (SDA/INT0

) can only be an input and cannot be configured.

) may only be configured to be either input-only or

open drain.

Table 13. Port output configuration settings

PxM1.y PxM2.y Port output mode

0 0 Quasi-bidirectional 0 1 Push-pull 1 0 Input only (high-impedance) 1 1 Open drain

4.2 Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low . When the pin is driven low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch for the pin contains a logic 1. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by an external device, the weak pull-up turns of f, and only the very weak pu ll-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch cha nges from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high.

The quasi-bidirectional port configuration is shown in Figure 10

.

Although the P89LPC9321 is a 3 V device most of the pins are 5 V-tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V

causing extra power consumption. Therefore, applying 5 V to pins

DD

configured in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch

suppression circuit

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2 CPU

CLOCK DELAY

port latch

data

weakstrong

input data

very

weak

PP P

V

DD

port

glitch rejection

002aaa915

port latch

data

input

data

glitch rejection

port

(Please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter specifications).

UM10310

P89LPC9321 User manual

Fig 10. Quasi-bidirectional output.

4.3 Open drain output configuration

The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V

The open drain port configuration is shown in Figure 11 An open drain port pin has a Schmitt-triggered input that also has a glitch suppression

circuit. Please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter

specifications.

. The pull-down for this mode is the same as for the quasi-bidirectional mode.

DD

.

Fig 11. Open drain output.

User manual Rev. 2 — 1 November 2010 30 of 139

NXP Semiconductors UM10310 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

1.1 Pin configuration

1.2 Pin description

1.3 Functional diagram

1.4 Block diagram

1.5 Special function registers

1.6 Memory organization

2. Clocks

2.1 Enhanced CPU

2.2 Clock definitions

2.2.1 Oscillator Clock (OSCCLK)

2.3 External crystal oscillator option

2.3.1 Low speed oscillator option

2.3.2 Medium speed oscillator option

2.3.3 High speed oscillator option

2.4 Clock output

2.5 On-chip RC oscillator option

2.6 Watchdog oscillator option

2.7 External clock input option

2.8 Clock sources switch on the fly

2.9 Oscillator Clock (OSCCLK) wake-up delay

2.10 CPU Clock (CCLK) modification: DIVM register

2.1 1 Low power select

3. Interrupts

3.1 Interrupt priority structure

3.2 External Interrupt pin glitch suppression

4. I/O ports

4.1 Port configurations

4.2 Quasi-bidirectional output configuration

4.3 Open drain output configuration