NXP Semiconductors TJA1100 User Manual

TR1329

TJA1100 Customer Evaluation Board - User Guide

Rev. 01.20 — 31 January 2018

User Manual

Document information

Info

Content

Title

TJA1100 Customer Evaluation Board - User Guide

Author(s)

Steffen Lorenz; Simon Zhu

Department

Systems & Applications

Keywords

TJA1100, 100BASE-T1, Ethernet, PHY

NXP Semiconductors

TR1329

Systems & Applications

TR1329

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2018. All rights reserved.

User Manual

Rev. 01.20 — 31 January 2018

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Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Revision history

Rev

Date

Description

1.0

20160112

Initial version

1.1

20160816

Updated for board revision V6, with latest EMC filter and ESD protection

- Fig. 1, 2, 4, 5, 6, 7, 8 updated

- Section 4.1: schematics updated

1.2

20180131

Updated for board revision V7, with latest MDI circuitry and new connector

- CE compliancy statement added

- Fig. 1, 2, 3, 4, 5, 6, 7 updated

- Section 2.2.1 description of bit strapping added

- Section 4.1 schematics updated

NXP Semiconductors

TR1329

Systems & Applications

TR1329

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2018. All rights reserved.

User Manual

Rev. 01.20 — 31 January 2018

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1. Introduction

This document describes the usage of the TJA1100 Customer Evaluation Board. The
Board supports the evaluation of the TJA1100 with providing (MII) a 40-pins standard
header (including MII/SMI/control signals/power supplies. Details can be found in section

2.3.1) with 2,54mm pinning distance to a host controller board, the bus interface (MDI)
including a srew terminal (SMKDS) connector as well as needed components for the
power supply and operation. Further information is given in the following sections.

Please note: the evaluation board has been designed for functional evaluation of the
PHY in your environment. The evaluation board is not intended for EMC or compliance
qualification measurements.

This product has not undergone formal EU EMC assessment. As a component used in a
research environment, it will be the responsibility of the user to ensure the finished
assembly does not cause undue interference when used and cannot be CE marked
unless assessed.

Fig 1. Customer PHY Board Top View

NXP Semiconductors

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Systems & Applications

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© NXP B.V. 2018. All rights reserved.

User Manual

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1.1 Acronyms

Table 1. Acronyms used in the document

Acronym

Description

BAT

Battery

DC

Direct Current

GND

Ground

MAC

Medium Access Controller

MDI

Medium Dependent Interface

MII

Medium Independent Interface

PHY

Physical

uC

Microcontroller

NXP Semiconductors

TR1329

Systems & Applications

TR1329

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2018. All rights reserved.

User Manual

Rev. 01.20 — 31 January 2018

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2. Board Setup

2.1 PHY Assembly

The TJA1100 is provided in a HVQFN-36 package (8x8sqmm). In case the TJA1100 on
the customer evaluation board must be changed, please ensure the correct placement.
The Pin 1 is located at the bottom right and is marked with a small white arrow (see Fig

2).

Fig 2. Pin 1 Location

2.2 Jumper Settings

2.2.1 Bit Strapping

The TJA1100 has several configuration pins for a pre-configuration during startup. The
following tables give an overview of the related jumpers and possible configurations, as
shown also in Fig 3. At the PCB (Fig 4) the orientation for High (H) and Low (L) is
marked.

Please note: all pre-configuration (except for the PHY addresses) can be overwritten via
SMI command.

PHY address is used for the SMI address and for initialization of the Cipher scrambler

key. The PHY address is five bits (PHYAD4…PHYAD0), and PHYAD4 is the MSB of the

address.
PHYAD[4:2] are set to “001” in the TJA1100. PHYAD[1:0] are pre-determined by bit

strapping.

NXP Semiconductors

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© NXP B.V. 2018. All rights reserved.

User Manual

Rev. 01.20 — 31 January 2018

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Table 2. Bit Strapping PHY-address

Jumper

Function

Address 4

Address 5

Address 6

Address 7

JP16

Configuration of PHYAD0

L H L

H

JP17

Configuration of PHYAD1

L L H

H

The TJA1100 can be configured as Master or Slave, as well as Managed or Autonomous
operation. When the TJA1100 is configured for Autonomous operation, the PHY will
automatically enter Normal mode and activate the link on power-on without further
interaction with a host controller.

Table 3. Bit Strapping Master/Slave Configuration

Jumper

Function

Master

Slave

JP18

Configuration of CONFIG0

H

L

Table 4. Bit Strapping Managed/autonomous Operation

Jumper

Function

Managed

Autonomous

JP19

Configuration of CONFIG1

L

H

The TJA1100 provides below MII modes, which can be configured via bit strapping.

Table 5. Jumper Settings for Bit Strapping

Jumper

Function

MII

RMII
50MHz

RMII
25MHz

Reverse
MII

JP21

Configuration of CONFIG2

L H L H JP20

Configuration of CONFIG3

L L H

H